PowerPC 440SP Embedded Processor PowerPC, processor core operatin
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Part Number 440SP Revision 1.12 November 2005
PowerPC 440SP Embedded Processor
PowerPC, processor core operating 667MHz with 32-KB D-caches (with parity checking) On-chip 256-KB SRAM configurable Cache Ethernet Packet/Code store memory Selectable Processor:Bus clock ratios (Refer Clocking chapter PPC440SP Embedded Processor User's Manual details) Supports Chip Selects) 64-bit/32bit SDRAM with DDR1 266-333-400 DDR2 400-533-667 Three PCI-X interfaces (32-bit 64-bit) (DDR 266) with support conventional Accelerator with controller Processor boot from memory Messaging Unit with controllers External Peripheral (24-bit Address, 8-bit Data) three devices Ethernet 10/100/1000 Mbps half- fullduplex interface. Operational modes supported GMII. Programmable Interrupt Controller supports interrupts from variety sources. Programmable General Purpose Timers (GPT) Three serial ports (16750 compatible UART) interfaces General Purpose (GPIO) interface available JTAG interface board level testing
Description
Designed specifically address high-end embedded applications storage, PowerPC 440SP Embedded Processor (PPC440SP) provides highperformance, power solution that interfaces wide range peripherals incorporating on-chip power management features lower power dissipation. This chip contains high-performance RISC processor core, DDR2 SDRAM controller, configurable 256KB SRAM used cache software-controlled on-chip memory, three PCI-X interfaces, Ethernet interface, I2O/DMA controller, control external peripherals, unit, serial ports, interfaces, general purpose I/O. Technology: CMOS Cu-11, 0.13mm Package: 29mm, 783-ball, pitch, Flip ChipPlastic Ball Grid Array (FC-PBGA) Power (estimated): Less than @533MHz Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5V
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PowerPC 440SP Embedded Processor Contents
Ordering Information Block Diagram Address Maps PowerPC Processor Core Internal Buses On-Chip SRAM/L2 Cache PCI-X Interface DDR1 DDR2 SDRAM Memory Controller External Peripheral Controller (EBC) Ethernet Controller Interface I2O/DMA Controller XOR/DMA Controller Serial Port Interface General Purpose Timers (GPT) General Purpose (GPIO) Controller Universal Interrupt Controller (UIC) JTAG Signal Lists Signal Description Device Characteristics Test Conditions Spread Spectrum Clocking Specifications Input/Output Timing SDRAM Specifications SDRAM Write Operation SDRAM Read Operation Initialization Strapping Serial Bootstrap Document Revision History
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Figures
PowerPC 440SP Embedded Processor
Figure Order Part Number Figure PPC440SP Functional Block Diagram Figure 29mm, 783-Ball FC-PBGA Core Package Figure Clock Timing Waveform Figure Input Setup Hold Timing Waveform Figure Output Delay Hold Timing Waveform Figure SDRAM Simulation Signal Termination Model Figure SDRAM Write Cycle Timing Figure SDRAM Read Data Path. Figure SDRAM Memory Data Figure SDRAM Read Cycle Timing Example
Tables
Table System Memory Address Table Address (4KB Device Configuration Registers) Table Signals Listed Alphabetically Table Signals Listed Ball Assignment Table Summary Table Signal Functional Description Table Absolute Maximum Ratings Table Package Thermal Specifications Table Recommended Operating Conditions Table Input Capacitance Table Power Supply Loads Table Clocking Specifications Table Peripheral Interface Clock Timings Table Specifications-All Speeds Table Specifications-533MHz Table SDRAM Output Driver Specifications Table SDRAM Read Write Timing-TSA Table SDRAM Clock Write Timing-TDS Table SDRAM Write Data Timing-TSD Table SDRAM Read Timing-TSD Table Strapping Assignments
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PowerPC 440SP Embedded Processor Ordering Information
information availability following parts, contact your local AMCC sales office.
Product Name PPC440SP Notes:
Order Part Number (see Notes:) PPC440SP-xpCfffC
Package 29mm, FC-PBGA
Level
Value 0x53221891
JTAG 0x12056049
Product Feature RAID6 enabled RAID6 enabled Module Package Type leaded FC-PBGA lead free FC-PGBA (RoHS compliant) Chip Revision Level Processor Frequency 533MHz 667MHz Case Temperature Range -40°C +100°C
Each part number contains revision code. This mask revision number included part number identification purposes only. (Processor Version Register) JTAG register software accessible (read-only) contain information that uniquely identifies part. PPC440SP Embedded Processor User's Manual details about accessing these registers. Figure Order Part Number
PPC440SP-RNC667C
AMCC Part Number Product Feature Package Case Temperature Range
Processor Speed Revision Level
Note: example part number above RAID6 enabled, lead-free package, Chip Revision Level capable running MHz, shipped tray packaging.
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Block Diagram
Figure PPC440SP Functional Block Diagram
Clock, Control, Reset Universal Interrupt Controller Timers DCRs
PowerPC 440SP Embedded Processor
Power Mgmt
UART2 IIC1 GPIO IIC0 UART1 UART0
PPC440
Processor Core JTAG 32KB D-Cache Trace 32KB I-Cache
On-chip Peripheral (OPB)
Cache/SRAM
Bridge
Processor Local (PLB)
Arbiter Ethernet 10/100/ 1000 (EMAC) MII, GMII External Controller (EBC)
Latency (LL) Segment High Bandwidth (HB) Segment
I2O/DMA Controller (DMA0 DMA1)
Memory Queue DDR2 SDRAM Controller
XOR/DMA Accelerator Unit (DMA2)
PCI-X
PCI2 PCI0 PCI1 Host Local Local bits bits bits
PPC440SP System chip, which uses IBM® CoreConnect BusArchitecture. Implemented with Crossbar option, CoreConnect buses provide: 128-bit Data, 64-bit Address interfaces 166.66MHz, 2.6GB/s both Read Write data paths (10.6GB/sec total) 32-bit interfaces 83.33MHz, 333MB/s
Address Maps
PPC440SP incorporates address maps. first fixed processor system memory address map. This address defines possible contents various processor accessible address regions. second address identifies system Device Configuration Registers (DCRs). DCRs accessed software running PPC440SP processor through mtdcr mfdcr instructions.
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PowerPC 440SP Embedded Processor
Table System Memory Address (Sheet
Function Function SDRAM Local Memory (LL)1 SRAM Reserved Registers Registers Registers Internal Interfaces (LL) I20/DMA Buffers Reserved XOR/DMA2 Reserved Reserved UART0 Reserved UART1 Reserved IIC0 Reserved IIC1 Reserved Internal Peripherals (LL) UART2 Reserved GPIO Controller Registers Reserved Ethernet Controller Registers Reserved General Purpose Timers Reserved Memory Additional Boot ROM6 Boot ROM2, Reserved Local Memory Alias (HB) Aliased SDRAM Start Address 0000 0000 0000 0000 0000 0001 0000 0000 0000 0001 0004 0000 0000 0001 0010 0000 0000 0001 0010 0100 0000 0001 0010 0200 0000 0001 0010 0300 0000 0001 0010 1000 0000 0001 0020 0000 0000 0001 0020 4000 0000 0001 F000 0000 0000 0001 F000 0200 0000 0001 F000 0208 0000 0001 F000 0300 0000 0001 F000 0308 0000 0001 F000 0400 0000 0001 F000 0420 0000 0001 F000 0500 0000 0001 F000 0520 0000 0001 F000 0600 0000 0001 F000 0608 0000 0001 F000 0700 0000 0001 F000 0780 0000 0001 F000 0800 0000 0001 F000 0900 0000 0001 F000 0A00 0000 0001 F000 0B40 0000 0001 F800 0000 0000 0001 FFC0 0000 0000 0001 FFE0 0000 0000 0002 0000 0000 0000 0008 0000 0000 Address 0000 0000 FFFF FFFF 0000 0001 0003 FFFF 0000 0001 000F FFFF 0000 0001 0010 00FF 0000 0001 0010 01FF 0000 0001 0010 02FF 0000 0001 0010 0FFF 0000 0001 001F FFFF 0000 0001 0020 3FFF 0000 0001 EFFF FFFF 0000 0001 F000 01FF 0000 0001 F000 0207 0000 0001 F000 02FF 0000 0001 F000 0307 0000 0001 F000 03FF 0000 0001 F000 041F 0000 0001 F000 04FF 0000 0001 F000 051F 0000 0001 F000 05FF 0000 0001 F000 0607 0000 0001 F000 06FF 0000 0001 F000 077F 0000 0001 F000 07FF 0000 0001 F000 08FF 0000 0001 F000 09FF 0000 0001 F000 0B3F 0000 0001 F7FF FFFF 0000 0001 FFBF FFFF 0000 0001 FFDF FFFF 0000 0001 FFFF FFFF 0000 0007 FFFF FFFF 0000 0008 FFFF FFFF 124MB 320B 256B 248B 128B 16KB 256B 256B 256B 3.25KB Size 256KB
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Table System Memory Address (Sheet
Function Reserved PCIX0 PCIX1 PCIX2 Function
PowerPC 440SP Embedded Processor
Start Address 0000 0009 0000 0000 0000 0009 0800 0000 0000 0009 1800 0000 0000 0009 2800 0000
Address 0000 0009 07FF FFFF 0000 0009 0800 FFFF 0000 0009 1800 FFFF 0000 0009 2800 FFFF
Size
64KB 64KB 64KB
PCIX0 Addressing Config. Regs PCIX1 Addressing Config. Regs PCIX2 Addressing Config. Regs
0000 0009 0EC0 0000 0000 0009 1EC0 0000 0000 0009 2EC0 0000
0000 0009 0EC0 0007 0000 0009 1EC0 0007 0000 0009 2EC0 0007
PCIX0 Core Config. Regs PCIX1 Core Config. Regs PCIX2 Core Config. Regs PCI-X Space (HB) PCIX0 Simple Message Passing PCIX1 Simple Message Passing PCIX2 Simple Message Passing
0000 0009 0EC8 0000 0000 0009 1EC8 0000 0000 0009 2EC8 0000
0000 0009 0EC8 0FFF 0000 0009 1EC8 0FFF 0000 0009 2EC8 0FFF
0000 0009 0EC8 1100 0000 0009 1EC8 1100 0000 0009 2EC8 1100
0000 0009 0EC8 11FF 0000 0009 1EC8 11FF 0000 0009 2EC8 11FF
256B 256B 256B
PCIX0 Special Cycle PCIX1 Special Cycle PCIX2 Special Cycle Reserved Memory Reserved Boot (PCI Memory) Memory Reserved4 Reserved5 PCI-X Space (HB) Notes: Memory
0000 0009 0ED0 0000 0000 0009 1ED0 0000 0000 0009 2ED0 0000 0000 0009 2EE0 0000 0000 0009 2F00 0000 0000 0009 FFC0 0000 0000 0009 FFE0 0000 0000 000A 0000 0000 0000 0010 0000 0000 0400 0010 0000 0000 0800 0000 0000 0000
0000 0009 0EDF FFFF 0000 0009 1EDF FFFF 0000 0009 2EDF FFFF 0000 0009 2EFF FFFF 0000 0009 FFBF FFFF 0000 0009 FFDF FFFF 0000 0009 FFFF FFFF 0000 000F FFFF FFFF 03FF FFFF FFFF FFFF 07FF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
3.3GB
24GB
15.7EB
SDRAM on-chip SRAM located anywhere Local Memory area memory map. Boot Expansion areas memory intended Flash-type devices. While locating volatile SDRAM SRAM this region supported, these regions this purpose recommended. When optional boot from PCI-X memory selected, PCI-X Boot address space begins FFE0 0000 (128 KB). Never decoded. Unpredictable results Read Write operations. Accessed means Peripheral Bank Configuration Registers
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PowerPC 440SP Embedded Processor
Table Address (4KB Device Configuration Registers)
Function Total Address Space1 function: Reserved Clocking Power Reset System DCRs Memory Controller External Controller Reserved SRAM Controller Memory Queue Reserved I2O/DMA Bridge Reserved Reserved Reserved Interrupt Controller Interrupt Controller Power Management Reserved Ethernet Reserved Notes: address space addressable with bits (1024 unique addresses). Each unique address represents single 32-bit (word) register. (1024W) equals (4096 bytes). 152W 128W 512W Start Address Address Size (4KB)1
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PowerPC Processor Core
PowerPC 440SP Embedded Processor
PowerPC processor core designed high-end applications such RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, first processor core implement Book PowerPC embedded architecture first 128-bit version IBM's on-chip CoreConnect Architecture. Features include: 667MHz operation PowerPC Book architecture 32KB I-cache, 32KB D-cache Parity Data address checking parity with error injection Three logical regions D-cache: Locked, Transient, Normal D-cache full-line flush capability 41-bit virtual address, 36-bit (64GB) physical address Superscalar, out-of-order execution Seven-stage pipeline Three execution pipelines Dynamic branch prediction Memory management unit 64-entry, full associative, unified with parity Separate instruction data micro-TLBs Storage attributes write-through, cache-inhibited, guarded, little endian Debug facilities Multiple instruction data range breakpoints Data value compare Single step, branch, trap events Non-invasive real-time trace interface instructions Single cycle multiply multiply-accumulate integer multiply
Internal Buses
PowerPC 440SP Embedded Processor features three standard on-chip buses: Processor Local (PLB), On-Chip Peripheral (OPB), Device Control Register (DCR). high performance, high bandwidth cores such PowerPC processor core, SDRAM memory controller, PCI-X bridge connect PLB. hosts lower data rate peripherals. daisy-chained provides lower bandwidth path passing status control information between processor core other on-chip cores. Crossbar arbiter that supports data transfer between master slave segments identified Latency (LL) High Bandwidth (HB) segments. segment allows masters I2O, that adversely affected latency, communicate with slave devices with minimal latency. segment allows masters DMA, XOR, exchange large blocks data with SDRAM without interfering with latency masters. features include: 128-bit Data implementation architecture Separate simultaneous read write data paths 64-bit address Simultaneous control, address, data phases Four levels pipelining Byte enable capability supporting unaligned transfers
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PowerPC 440SP Embedded Processor
64-byte burst transfers 166MHz, maximum 5.2GB/s (simultaneous read write) Processor:Bus clock ratios Dynamic sizing: 32-, 16-, 8-bit data path 32-bit address 83.33MHz, maximum 333MB/s 32-bit data path 10-bit address
On-Chip SRAM/L2 Cache
Features include: Four banks 64KB each total 256KB Configurable either cache SRAM Memory cycles supported: Single beat read write, bytes Quadword Read Write burst 12-bit master Guarded memory accesses boundaries Sustainable 2.6GB/s peak bandwidth 166MHz cache improves processor performance reduces load Cache coherency maintained hardware snoop mechanism software Data Array Array parity Unified data instruction cache Four-way associative 36-bit addressing Full replacement algorithm Write through, look aside Ethernet packet store allows Ethernet packets held processing Ethernet core
PCI-X Interface
PCI-X interface allows connection PCI-X devices PowerPC processor local memory. There three separate interfaces supporting 64-bit PCI-X buses mode. three interfaces configured either host adapter mode. 32/64-bit legacy mode, compatible with Version 2.3, also supported. Features include: PCI-X Split transactions Frequency 266MHz 64-bit address/data supported 266MHz Mode only backward compatibility Frequency 66MHz 64-bit Host Bridge Adapter Device interface Optional arbitration function with PCI-X mode supporting four external devices, that disabled with external arbiter Support Message Signaled Interrupts (MSI) both out-bound interrupts Simple message passing capability Asynchronous Power Management Version
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PowerPC 440SP Embedded Processor
arbitration function with PCI-X Mode support (optional) register addressable both from on-chip processor device sides Ability boot from PCI-X memory Error tracking/status Supports initiation transfer following address spaces: Single beat reads writes Single beat burst memory reads writes Single beat configuration reads writes (Type Type Single beat special cycles PCI-X initialization sequence support (frequency mode determination) Support unexpected split completions Outbound transaction split discard timers Vital Product Data (VPD) support PCI-to-PCI opaque bridge
DDR1 DDR2 SDRAM Memory Controller
DDR2 SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, other discrete devices. Global memory timings, address bank sizes, memory addressing modes programmable. DDR2 SDRAM controller interfaces through Memory Queue (MQ) function that includes highspeed FIFO buffers. Features include: Registered non-registered industry standard DIMMs DDR1 266-333-400 DDR2 400-533-667 64-and 32-bit memory interfaces with optional 8-bit (SEC/DED) 5.32GB/s peak bandwidth 64-bit interface 2.66GB/s peak bandwidth 32-bit interface chip (bank) select signals supporting external banks latencies supported Page mode accesses open pages) with configurable paging policy Look-ahead request queue with programmable depth four commands. Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing current bank) external banks Programmable address mapping timing Hardware software initiated self-refresh Sync DRAM configuration means mode register extended mode register commands Power management (self-refresh, suspend, sleep) Latency High Bandwidth ports Selectable read response (immediate deferred) Programmable Latency High Bandwidth arbitration schemes High Bandwidth port four read buffers two1KB write buffers Latency port four 128B read buffers 128B write buffers
External Peripheral Controller (EBC)
Features include: Support Boot three ROM, EPROM, SRAM, Flash memory, slave peripherals supported Burst non-burst devices 8-bit data 24-bit address, 16MB address space
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PowerPC 440SP Embedded Processor
Peripheral Device pacing with external "Ready" Latch data Ready, synchronous asynchronous Programmable access timing device Wait States non-burst Burst Wait States first access Wait States subsequent accesses Programmable CSon, CSoff relative address Programmable OEon, WEon, WEoff clock cycles) relative Programmable address mapping
Ethernet Controller Interface
Ethernet support interfaces physical layer, included chip. Features include: 10/100/1000 interface running full- half-duplex modes full Media Independent Interface (MII) with 4-bit parallel data transfer Gigabit Media Independent Interface (GMII)
I2O/DMA Controller
I20/DMA controller provides support messaging controllers (DMA0 DMA1). manages message frame address (MFA) FIFOs queues memory response register reads writes transfers message frames. DMAs provide normal memory access support ease burden. features include: pull- push-messaging methods Dynamic message frame size Programmable FIFO size (4096 64-bit MFAs maximum) 64-bit 32-bit sizes Three interrupt gathering methods Registered prefetch posting 32-bit inbound outbound doorbell registers Four 32-bit scratch registers features include: Programmable Command Pointer FIFO Completion FIFO size 2048 operations queued) 512-byte/1KB buffering DMA0/DMA1 Simultaneous fill drain (PLB read/write pipelining) source address destination address memory alignment restrictions source destination 32-byte command descriptor block Maximum transfer size 16MB 64-bit addressing Prefetch indicators PCI-X buffer management (DMA1 only)
XOR/DMA Controller
XOR/DMA controller performs functions needed support RAID applications including parity generation check functions used across data stripes RAID system. Features include: Computes bit-wise data streams with result stored designated target Performs check data streams Driven linked list Command Block structure specifying control information, source operands, target operand, status information, link
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PowerPC 440SP Embedded Processor
Source target streams reside anywhere address space. Provides completion status Command Block handled software later time 96-byte 160-byte Command Block formats supported memory alignment restrictions operands target Internal register arrays data buffers parity protected used controller (DMA2) with single source target addresses
Serial Port
serial port compatible with 16570 UART interface. Features include: 8-pin, 4-pin, 2-pin interfaces provided Selectable internal external serial clock allow wide range baud rates Register compatibility with 16750 register Complete status reporting capability Fully programmable serial-interface characteristics Supports using internal engine
Interface
Features include: interfaces provided Support Philips, Semiconductors Specification, dated 1995 Operation 100kHz 400kHz 8-bit data 7-bit address Slave transmitter receiver Master transmitter receiver Multiple masters Supports fixed interface independent byte data buffers Twelve memory-mapped, fully programmable configuration registers programmable interrupt request signal Full management protocols Programmable error recovery Port supports serial Bootstrap with default parameters override initialization
General Purpose Timers (GPT)
Provides time base counter system timers additional those defined processor core. 32-bit time base counter driven clock Seven 32-bit compare timers
General Purpose (GPIO) Controller
Controller functions GPIO registers programmed accessed means memory-mapped master accesses. GPIOs pin-shared with other functions. DCRs control whether particular that GPIO capabilities acts GPIO used another purpose. Each GPIO output separately programmable tri-state driver (pull-up, pull-down, open-drain).
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PowerPC 440SP Embedded Processor Universal Interrupt Controller (UIC)
cascaded Universal Interrupt Controllers (UIC) process internal on-chip external processor interrupts. Note: Processor specific interrupts (for example, page faults) resources. Features include: external interrupts internal interrupts Edge-triggered level-sensitive Positive- negative-active Non-critical critical interrupt on-chip processor core Programmable interrupt priority ordering Programmable critical interrupt vector faster vector processing
JTAG
Features include: IEEE 1149.1 Test Access Port RISCWatch Debugger support JTAG Boundary Scan Description Language (BSDL)
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Figure 29mm, 783-Ball FC-PBGA Core Package
PowerPC 440SP Embedded Processor
View
Corner
Product Family
PPC440SP XXXXXX LLLLLLLL OOOOOO PPC440SP-xpCfffC
Country Origin
Number Part Number
Note: dimensions
Bottom View
29.0
29.0 SOLDERBALL 3.27
1.00
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PowerPC 440SP Embedded Processor Signal Lists
following table lists external signals alphabetical order shows ball (pin) number which signal appears. Multiplexed signals shown with default signal (following reset) brackets alternate signal signals brackets. Multiplexed signals appear alphabetically multiple times list-once each signal name ball. page number listed gives page "Signal Functional Description" page which signals indicated interface group begin. Table Signals Listed Alphabetically (Sheet
Signal Name A1GND A2GND A1VDD A2VDD AP0GND AP0VDD AP1GND AP1VDD AP2GND AP2VDD BankSel0 BankSel1 ClkEn0 ClkEn1 Ball AG28 AF28 AG01 Power AF01 AD21 AE20 AE25 SDRAM AH25 AE23 AE24 AE26 AA26 AA24 SDRAM Interface Group Page
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Table Signals Listed Alphabetically (Sheet
Signal Name DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DQS8 DQS8 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMCCD EMCCrS EMCMDClk EMCMDIO EMCRefClk EMCRxClk Ball AD26 AD25 AA28 AA27 SDRAM AB26 AB25 AC24 AC23 AD23 AA23 AF20 Ethernet
PowerPC 440SP Embedded Processor
Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name EMCRxD0 EMCRxD1 EMCRxD2 EMCRxD3 EMCRxD4 EMCRxD5 EMCRxD6 EMCRxD7 EMCRxDV EMCRxErr EMCTxClk EMCGTxClk EMCTxD0 EMCTxD1 EMCTxD2 EMCTxD3 EMCTxD4 EMCTxD5 EMCTxD6 EMCTxD7 EMCTxEn EMCTxErr ExtReset Ball Ethernet External Slave Peripheral Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name Ball Power
PowerPC 440SP Embedded Processor
Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name Ball Power Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name Ball AB05 AB09 AB13 AB16 AB20 AB24 AC14 AC15 AD02 Power AD07 AD11 AD18 AD22 AD27 AF13 AF16 AG02 AG05 AG09 AG20 AG24 AG27
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Interface Group
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PowerPC 440SP Embedded Processor
Table Signals Listed Alphabetically (Sheet
Signal Name GPIO00[TrcClk][PCIX0Req2] GPIO01[TrcBS0][PCIX0Req3] GPIO02[TrcBS1][PCIX0Gnt2] GPIO03[TrcBS2][PCIX0Gnt3] GPIO04[TrcES0][PCIX1Req2] GPIO05[TrcES1][PCIX1Req3] GPIO06[TrcES2][PCIX1Gnt2] GPIO07[TrcES3][PCIX1Gnt3] [GPIO08][TrcES4]PerReady [GPIO09]PerCS1[TrcTS0] [GPIO10]PerCS2[TrcTS1] GPIO11[IRQ0][TrcTS2] GPIO12[IRQ1][TrcTS3] GPIO13[IRQ2][TrcTS4] GPIO14[IRQ3][TrcTS5] GPIO15[IRQ4][TrcTS6] GPIO16[IRQ5][UART2_Rx] [GPIO17]PerBE0[UART2_Tx] [GPIO18]PCIX0Gnt0 [GPIO19]PCIX0Gnt1 [GPIO20]PCIX0Req0 [GPIO21]PCIX0Req1 [GPIO22]PCIX1Gnt0 [GPIO23]PCIX1Gnt1 [GPIO24]PCIX1Req0 [GPIO25]PCIX1Req1 [GPIO26]PCIX2Gnt0 [GPIO27]PCIX2Gnt1 [GPIO28]PCIX2Req0 [GPIO29]PCIX2Req1 [GPIO30]UART1_Rx [GPIO31]UART1_Tx Halt HISRRst Ball AA12 AC13 AF11 System AF14 AG13 AH11 AG12 Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name IIC0SClk IIC0SDA IIC1SClk IIC1SDA [IRQ0]GPIO11[TrcTS2] [IRQ1]GPIO12[TrcTS3] [IRQ2]GPIO13[TrcTS4] [IRQ3]GPIO14[TrcTS5] [IRQ4]GPIO15[TrcTS6] [IRQ5]GPIO16[UART2_Rx] MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemAddr13 MemAddr14 MemClkOut0 MemClkOut0 MemClkOut1 MemClkOut1 Ball Peripheral Interrupts AF23 AE21 AD19 AE19 AH22 AH23 AE22 AF21 AF22 AG23 AG21 AF19 AH20 AH21 AF24 AG26 AG25 AH26 AH27 SDRAM
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Table Signals Listed Alphabetically (Sheet
Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 Ball AD28 AE27 AF27 AC26 AC27 AE28 AF25 AC25 AB28 AC28 AA25 AB23 SDRAM Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 MemData49 MemData50 MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 MemData59 MemData60 MemData61 MemData62 MemData63 MemDCFdbkD MemDCFdbkR Ball SDRAM AB21 AC21
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Table Signals Listed Alphabetically (Sheet
Signal Name MemODT0 MemODT1 MemVRef0 MemVRef1 ball OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Ball AA22 AC22 SDRAM AA20 AA21 Power physical ball does exist this coordinate Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name P0VDD P0VDD P0VDD P0VDD P0VDD P0VDD P0VDD P0VDD P0VDD P0VDD P0VDD P0VDD P0VDD P1VDD P1VDD P1VDD P1VDD P1VDD P1VDD P1VDD P1VDD P1VDD P1VDD P2VDD P2VDD P2VDD P2VDD P2VDD P2VDD P2VDD P2VDD Ball AB07 AB11 AB18 AB22 AG07 AG11 AG14 AG15 AG18 AG22 AB02 AF03 Power
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Table Signals Listed Alphabetically (Sheet
Signal Name PCIX0Ack64 PCIX0AD00 PCIX0AD01 PCIX0AD02 PCIX0AD03 PCIX0AD04 PCIX0AD05 PCIX0AD06 PCIX0AD07 PCIX0AD08 PCIX0AD09 PCIX0AD10 PCIX0AD11 PCIX0AD12 PCIX0AD13 PCIX0AD14 PCIX0AD15 PCIX0AD16 PCIX0AD17 PCIX0AD18 PCIX0AD19 PCIX0AD20 PCIX0AD21 PCIX0AD22 PCIX0AD23 PCIX0AD24 PCIX0AD25 PCIX0AD26 PCIX0AD27 PCIX0AD28 PCIX0AD29 PCIX0AD30 PCIX0AD31 Ball AH06 AE12 AE11 AE10 AE09 AF10 AH08 AH09 AA11 AC09 AA09 AC08 AD08 AD10 AA10 AB10 AH07 AF06 AF07 AE08 AF05 AF04 AD06 AG04 AF08 AH02 AH03 AF02 AE03 AD04 AE05 AE01 AE02 PCI-X0 Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name PCIX0AD32 PCIX0AD33 PCIX0AD34 PCIX0AD35 PCIX0AD36 PCIX0AD37 PCIX0AD38 PCIX0AD39 PCIX0AD40 PCIX0AD41 PCIX0AD42 PCIX0AD43 PCIX0AD44 PCIX0AD45 PCIX0AD46 PCIX0AD47 PCIX0AD48 PCIX0AD49 PCIX0AD50 PCIX0AD51 PCIX0AD52 PCIX0AD53 PCIX0AD54 PCIX0AD55 PCIX0AD56 PCIX0AD57 PCIX0AD58 PCIX0AD59 PCIX0AD60 PCIX0AD61 PCIX0AD62 PCIX0AD63 Ball AE18 AF18 AH19 AG19 AD17 AA18 AC20 AE17 AA17 AC19 AB17 AC17 AB19 PCI-X0 AC18 AH18 AG16 AF17 AF15 AH15 AE15 AD15 AB14 AB15 AA14 AA16 AC16 AA15
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Interface Group
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PowerPC 440SP Embedded Processor
Table Signals Listed Alphabetically (Sheet
Signal Name PCIX0BE0 PCIX0BE1 PCIX0BE2 PCIX0BE3 PCIX0BE4 PCIX0BE5 PCIX0BE6 PCIX0BE7 PCIX0CalG0 PCIX0CalG1 PCIX0CalR0 PCIX0CalR1 PCIX0Cap PCIX0Clk PCIX0DevSel PCIX0ECC2 PCIX0ECC3 PCIX0ECC4 PCIX0ECC5 PCIX0Frame PCIX0Gnt0[GPIO18] PCIX0Gnt1[GPIO19] [PCIX0Gnt2]GPIO02[TrcBS1] [PCIX0Gnt3]GPIO03[TrcBS2] PCIX0IDSel PCIX0INTA PCIX0IRDY PCIX0M66En PCIX0Par PCIX0Par64 PCIX0PErr Ball AF09 AG10 AE07 AE06 AH16 AG17 AE16 AE14 AA08 AB08 AA19 AA13 AF12 AG03 AH04 AH05 AD03 AC12 AF14 AG13 AC13 AF11 AB12 AD14 AG06 AH14 PCI-X0 Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name PCIX0Req0[GPIO20] PCIX0Req1[GPIO21] [PCIX0Req2]GPIO00[TrcClk] [PCIX0Req3]GPIO01[TrcBS0] PCIX0Req64 PCIX0Reset PCIX0SErr PCIX0Stop PCIX0TRDY PCIX0VC PCIX0VRef0 PCIX0VRef1 Ball AH11 AG12 AA12 AG08 AH13 PCI-X0 AD12 AE13 AH10 AC11 AC10
PowerPC 440SP Embedded Processor
Interface Group
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PowerPC 440SP Embedded Processor
Table Signals Listed Alphabetically (Sheet
Signal Name PCIX1Ack64 PCIX1AD00 PCIX1AD01 PCIX1AD02 PCIX1AD03 PCIX1AD04 PCIX1AD05 PCIX1AD06 PCIX1AD07 PCIX1AD08 PCIX1AD09 PCIX1AD10 PCIX1AD11 PCIX1AD12 PCIX1AD13 PCIX1AD14 PCIX1AD15 PCIX1AD16 PCIX1AD17 PCIX1AD18 PCIX1AD19 PCIX1AD20 PCIX1AD21 PCIX1AD22 PCIX1AD23 PCIX1AD24 PCIX1AD25 PCIX1AD26 PCIX1AD27 PCIX1AD28 PCIX1AD29 PCIX1AD30 PCIX1AD31 Ball PCI-X1 Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name PCIX1AD32 PCIX1AD33 PCIX1AD34 PCIX1AD35 PCIX1AD36 PCIX1AD37 PCIX1AD38 PCIX1AD39 PCIX1AD40 PCIX1AD41 PCIX1AD42 PCIX1AD43 PCIX1AD44 PCIX1AD45 PCIX1AD46 PCIX1AD47 PCIX1AD48 PCIX1AD49 PCIX1AD50 PCIX1AD51 PCIX1AD52 PCIX1AD53 PCIX1AD54 PCIX1AD55 PCIX1AD56 PCIX1AD57 PCIX1AD58 PCIX1AD59 PCIX1AD60 PCIX1AD61 PCIX1AD62 PCIX1AD63 Ball PCI-X1
PowerPC 440SP Embedded Processor
Interface Group
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PowerPC 440SP Embedded Processor
Table Signals Listed Alphabetically (Sheet
Signal Name PCIX1BE0 PCIX1BE1 PCIX1BE2 PCIX1BE3 PCIX1BE4 PCIX1BE5 PCIX1BE6 PCIX1BE7 PCIX1CalG0 PCIX1CalG1 PCIX1CalR0 PCIX1CalR1 PCIX1Cap PCIX1Clk PCIX1DevSel PCIX1ECC2 PCIX1ECC3 PCIX1ECC4 PCIX1ECC5 PCIX1Frame PCIX1Gnt0[GPIO22] PCIX1Gnt1[GPIO23] [PCIX1Gnt2]GPIO06[TrcES2] [PCIX1Gnt3]GPIO07[TrcES3] PCIX1IDSel PCIX1INTA PCIX1IRDY PCIX1M66En PCIX1Par PCIX1Par64/PCIX2ECC7 PCIX1PErr Ball PCI-X1 Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name PCIX1Req0[GPIO24] PCIX1Req1[GPIO25] [PCIX1Req2]GPIO04[TrcES0] [PCIX1Req3]GPIO05[TrcES1] PCIX1Req64 PCIX1Reset PCIX1SErr PCIX1Stop PCIX1TRDY PCIX1VC PCIX1VRef0 PCIX1VRef1 Ball PCI-X1
PowerPC 440SP Embedded Processor
Interface Group
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PowerPC 440SP Embedded Processor
Table Signals Listed Alphabetically (Sheet
Signal Name PCIX2Ack64/PCIX0ECC1 PCIX2AD00 PCIX2AD01 PCIX2AD02 PCIX2AD03 PCIX2AD04 PCIX2AD05 PCIX2AD06 PCIX2AD07 PCIX2AD08 PCIX2AD09 PCIX2AD10 PCIX2AD11 PCIX2AD12 PCIX2AD13 PCIX2AD14 PCIX2AD15 PCIX2AD16 PCIX2AD17 PCIX2AD18 PCIX2AD19 PCIX2AD20 PCIX2AD21 PCIX2AD22 PCIX2AD23 PCIX2AD24 PCIX2AD25 PCIX2AD26 PCIX2AD27 PCIX2AD28 PCIX2AD29 PCIX2AD30 PCIX2AD31 Ball AC03 AC04 AC05 AD01 AB01 AB04 AC01 AC02 AA01 AA03 AA04 AB06 AC06 AA05 PCI-X2 Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name PCIX2BE0 PCIX2BE1 PCIX2BE2 PCIX2BE3 PCIX2CalG0 PCIX2CalR0 PCIX2Cap PCIX2Clk PCIX2DevSel PCIX2ECC2 PCIX2ECC3 PCIX2ECC4 PCIX2ECC5 PCIX2Frame PCIX2Gnt0[GPIO26] PCIX2Gnt1[GPIO27] PCIX2IDSel PCIX2INTA PCIX2IRDY PCIX2M66En PCIX2Par/PCIX2ECC0 PCIX2PErr PCIX2Req0[GPIO28] PCIX2Req1[GPIO29] PCIX2Req64/PCIX2ECC6 PCIX2Reset PCIX2SErr PCIX2Stop PCIX2TRDY PCIX2VC PCIX2VRef0 PCIX2VRef1 Ball AB03 AA02 AA07 AA06 PCI-X2 AC07 AE04
PowerPC 440SP Embedded Processor
Interface Group
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PowerPC 440SP Embedded Processor
Table Signals Listed Alphabetically (Sheet
Signal Name PerAddr00 PerAddr01 PerAddr02 PerAddr03 PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerBE0[GPIO17][UART2_Tx] PerBLast PerClk PerCS0 PerCS1[GPIO09][TrcTS0] PerCS2[GPIO10][TrcTS1] Ball External Slave Peripheral Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name PerData0 PerData1 PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerOE PerReady[GPIO08][TrcES4] PerWE PSRO PSRO PSRO PSRO Ball PSRO AH24 SDRAM
PowerPC 440SP Embedded Processor
Interface Group
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External Slave Peripheral
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PowerPC 440SP Embedded Processor
Table Signals Listed Alphabetically (Sheet
Signal Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Ball Reserved Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SysClk SysErr SysPartSel SysReset Ball Power AB27 AF26 System Reserved
PowerPC 440SP Embedded Processor
Interface Group
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PowerPC 440SP Embedded Processor
Table Signals Listed Alphabetically (Sheet
Signal Name TestEn TmrClk [TrcClk]GPIO00[PCIX0Req2] [TrcBS0]GPIO01[PCIX0Req3] [TrcBS1]GPIO02[PCIX0Gnt2] [TrcBS2]GPIO03[PCIX0Gnt3] [TrcES0]GPIO04[PCIX1Req2] [TrcES1]GPIO05[PCIX1Req3] [TrcES2]GPIO06[PCIX1Gnt2] [TrcES3]GPIO07[PCIX1Gnt3] [TrcES4][GPIO08]PerReady [TrcTS0]PerCS1[GPIO09] [TrcTS1]PerCS2[GPIO10] [TrcTS2]GPIO11[IRQ0] [TrcTS3]GPIO12[IRQ1] [TrcTS4]GPIO13[IRQ2] [TrcTS5]GPIO14[IRQ3] [TrcTS6]GPIO15[IRQ4] TRST UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx Ball System AA12 AC13 AF11 Trace UART Peripheral JTAG JTAG JTAG Interface Group
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Table Signals Listed Alphabetically (Sheet
Signal Name UART1_DSR/CTS UART1_RTS/DTR UART1_Rx[GPIO30] UART1_Tx[GPIO31] [UART2_Rx]GPIO16[IRQ5] [UART2_Tx][GPIO17]PerBE0 UARTSerClk Ball Power UART Peripheral
PowerPC 440SP Embedded Processor
Interface Group
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PowerPC 440SP Embedded Processor
Table Signals Listed Alphabetically (Sheet
Signal Name Ball Power AD05 AD09 AD13 AD16 AD20 AD24 AH01 AH12 AH17 AH28 SDRAM Interface Group
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Signal List
PowerPC 440SP Embedded Processor
following table, only primary (default) signal name shown each pin. Multiplexed multifunction signals marked with asterisk (*). determine what additional signals functions appear those pins, look primary signal name "Signals Listed Alphabetically" page Table Signals Listed Ball Assignment (Sheet
Ball Signal Name ball EMCTxD7 EMCTxErr PerClk GPIO13* UART1_Tx* UART1_Rx* UART0_DCD UARTSerClk UART0_DTR UART0_RI SysPartSel PCIX1AD16 PCIX1AD19 TestEn PCIX1AD03 PCIX1Reset PCIX1VC PCIX1INTA PCIX1SErr PCIX1Par64* PCIX1AD61 PCIX1AD60 PCIX1AD40 Ball Signal Name A1GND PerErr* PerBLast HISRRst OVDD EMCGTxClk TRST OVDD PCIX1AD26 PCIX1AD25 OVDD OVDD PCIX1AD11 PCIX1AD10 P1VDD PCIX1Gnt0* PCIX1Frame P1VDD PCIX1IDSel PCIX1AD56 PCIX1AD51 AP1GND Ball Signal Name A1VDD PerPar0* OVDD EMCTxEn GPIO14* GPIO12* GPIO11* UART0_Tx UART0_CTS UART0_DSR PCIX1AD27 PCIX1AD17 PCIX1AD18 PCIX1AD08 PCIX1AD01 PCIX1Gnt1* PCIX1Req0* PCIX1Stop PCIX1Req1* GPIO04* PCIX1AD57 PCIX1AD59 P1VDD PCIX1AD42 AP1VDD Ball Signal Name EMCMDClk EMCCD EMCRxClk PerData3 GPIO16* GPIO15* Reserved TmrClk IIC0SClk EMCRefClk PCIX1AD24 PCIX1BE2 PCIX1AD20 PCIX1AD09 PCIX1BE1 PCIX1AD00 PCIX1DevSel PCIX1PErr GPIO06* PCIX1IRDY GPIO07* PCIX1AD58 PCIX1AD62 PCIX1BE4 PCIX1AD43 PCIX1AD35
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PowerPC 440SP Embedded Processor
Table Signals Listed Ball Assignment (Sheet
Ball Signal Name EMCTxClk EMCCrS EMCMDIO PerData5 IIC0SDA IIC1SDA PerCS1* PCIX1BE3 PCIX1AD28 PCIX1AD12 PCIX1TRDY PCIX1Clk GPIO05* PCIX1AD50 PCIX1AD52 PCIX1AD32 Ball Signal Name EMCTxD1 EMCTxD0 EMCRxD2 EMCRxD0 EMCRxD6 EMCRxD7 EMCRxDV IIC1SClk Reserved UART1_DSR/CTS UART0_RTS PerOE Reserved PCIX1AD04 PCIX1BE0 PCIX1AD02 PCIX1AD14 PCIX1AD06 PCIX1AD07 PCIX1BE7 PCIX1ECC5 PCIX1AD63 PCIX1BE5 PCIX1AD44 PCIX1AD34 PCIX1AD33 Ball Signal Name EMCRxD3 OVDD EMCTxD3 EMCRxD1 PerData6 OVDD PerData4 UART1_RTS/DTR OVDD PerReady* PCIX1CalG1 SysReset PCIX1AD22 P1VDD PCIX1AD15 PCIX1Cap P1VDD PCIX1M66En PCIX1BE6 PCIX1AD41 P1VDD PCIX1AD36 Ball
Signal Name EMCTxD2 EMCRxD5 EMCRxD4 EMCTxD4 PerData0 PerR/W* PerData2 Reserved Reserved PerCS2* ExtReset UART0_Rx Reserved PCIX1CalR1 PCIX1ECC4 PCIX1AD30 PCIX1AD21 PCIX1AD23 PCIX1AD13 PCIX1AD05 PCIX1ECC2 PCIX1ECC3 PCIX1AD55 PCIX1Req64 PCIX1AD48 MemData39 MemData36 MemData35
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Table Signals Listed Ball Assignment (Sheet
Ball Signal Name EMCRxErr SysClk PerAddr00 PerData7 PerData1 Reserved Reserved Reserved PCIX1AD31 PCIX1VRef0 SysErr PCIX1AD54 PCIX1AD53 PCIX1AD49 MemData32 MemData37 Ball Signal Name PerAddr19 PerAddr20 EMCTxD6 EMCTxD5 PerAddr02 PerAddr01 PerAddr07 PerAddr08 Reserved PerWE Reserved Reserved Reserved OVDD OVDD PCIX1AD29 PCIX1VRef1 Halt PCIX1Par PCIX1AD47 PCIX1AD46 PCIX1AD45 PCIX1Ack64 MemData45 DQS4 DQS4 MemData33 Ball
PowerPC 440SP Embedded Processor
Signal Name PerAddr17 OVDD PerAddr15 PerAddr16 PerAddr04 OVDD PerAddr06 Reserved OVDD Reserved Reserved Reserved Reserved P1VDD PCIX1CalG0 PCIX1CalR0 P1VDD PCIX1AD39 DQS5 DQS5 P1VDD MemData34 Ball PCIX2Stop PCIX2DevSel PerAddr18 PerAddr09 PerCS0 PerAddr05 PerAddr03 Reserved Reserved Reserved PSRO Reserved Reserved Reserved Reserved PSRO Reserved PCIX1AD38 PCIX1AD37 MemData42 MemData41 MemData46 MemData31 MemData28 MemData27 Signal Name
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PowerPC 440SP Embedded Processor
Table Signals Listed Ball Assignment (Sheet
Ball Signal Name PCIX2ECC4 PCIX2TRDY PCIX2Req1* PerAddr11 PerAddr10 Reserved Reserved Reserved MemData47 MemData44 MemData43 MemData24 DQS3 DQS3 Ball Signal Name PCIX2Gnt0* P2VDD PCIX2Gnt1* PCIX2IRDY PerAddr13 PerAddr14 PerAddr12 Reserved OVDD Reserved Reserved OVDD P1VDD Reserved Reserved SVDD MemData40 MemData38 BankSel1 MemData54 MemData29 SVDD MemData25 Ball Signal Name AP2VDD P2VDD PCIX2Clk PCIX2VRef0 PerAddr22 PerAddr21 PerAddr23 PerBE0* P2VDD Reserved Reserved P0VDD SVDD Reserved Reserved SVDD MemData53 MemData49 MemData50 DQS6 DQS6 SVDD MemData26 Ball
Signal Name AP2GND PCIX2AD27 PCIX2AD26 PCIX2M66En PCIX2Cap PCIX2IDSel Reserved Reserved MemData52 MemData55 BankSel0 MemData19 MemData20 MemData23
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Table Signals Listed Ball Assignment (Sheet
Ball PCIX2BE3 PCIX2AD25 PCIX2AD28 PCIX2Req0* PCIX2PErr PCIX2INTA PCIX2Frame PCIX2ECC3 PCIX2VRef1 Reserved PSRO Reserved Reserved Reserved Reserved PSRO Reserved MemData57 MemData58 MemData51 MemData48 MemData30 DQS2 DQS2 MemData16 Signal Name Ball Signal Name PCIX2AD24 P2VDD PCIX2BE2 PCIX2AD20 PCIX2Reset P2VDD PCIX2SErr PCIX2VC P2VDD Reserved Reserved Reserved Reserved SVDD MemData62 SVDD MemData61 MemData21 SVDD MemData17 Ball
PowerPC 440SP Embedded Processor
Signal Name PCIX2AD17 PCIX2AD16 PCIX2AD18 PCIX2AD19 PCIX2AD31 PCIX2AD30 PCIX2AD29 PCIX2CalG0 PCIX2CalR0 PCIX2Ack64* PCIX0PErr PCIX0TRDY PCIX0IRDY P0VDD P0VDD PCIX0AD60 PCIX0AD42 PCIX0AD38 ECC6 MemData63 MemData60 MemData56 MemData22 MemData59 MemData15 DQS7 DQS7 MemData18 Ball Signal Name PCIX2AD11 PCIX2AD10 PCIX2AD08 PCIX2AD21 PCIX2AD22 PCIX0DevSel GPIO01* PCIX0IDSel PCIX0AD59 PCIX0AD41 PCIX0CalG1 ECC2 ECC1 MemData12 MemData08 MemData11
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PowerPC 440SP Embedded Processor
Table Signals Listed Ball Assignment (Sheet
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 Signal Name PCIX2AD09 PCIX2BE1 PCIX2AD12 PCIX2AD13 PCIX2AD23 PCIX2ECC5 PCIX2ECC2 PCIX0CalG0 PCIX0AD09 PCIX0AD13 PCIX0AD07 GPIO00* PCIX0Cap PCIX0AD58 PCIX0AD63 PCIX0AD61 PCIX0AD43 PCIX0AD37 PCIX0CalR1 MemVRef0 MemVRef1 MemODT0 ECC5 MemData13 DQS1 DQS1 Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 Signal Name PCIX2AD04 P2VDD PCIX2BE0 PCIX2AD05 PCIX2AD14 P0VDD PCIX0CalR0 PCIX0AD14 P0VDD PCIX0INTA PCIX0AD56 PCIX0AD57 PCIX0AD45 P0VDD PCIX0AD47 MemDCFdbkD P0VDD MemData14 DQS8 DQS8 SVDD MemData09 Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 Signal Name PCIX2AD06 PCIX2AD07 PCIX2AD00 PCIX2AD01 PCIX2AD02 PCIX2AD15 PCIX2Par* PCIX0AD10 PCIX0AD08 PCIX0VRef1 PCIX0VRef0 PCIX0Frame GPIO02* PCIX0AD62 PCIX0AD46 PCIX0AD48 PCIX0AD44 PCIX0AD39 MemDCFdbkR MemODT1 ECC3 ECC0 MemData07 MemData03 MemData04 MemData10 Ball AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28
Signal Name PCIX2AD03 PCIX0ECC5 PCIX0AD28 PCIX0AD21 PCIX0AD11 PCIX0AD12 PCIX0SErr PCIX0M66En PCIX0AD55 PCIX0AD36 MemAddr02 ECC4 DQS0 DQS0 MemData00
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Table Signals Listed Ball Assignment (Sheet
Ball AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 Signal Name PCIX0AD30 PCIX0AD31 PCIX0AD27 PCIX2Req64* PCIX0AD29 PCIX0BE3 PCIX0BE2 PCIX0AD18 PCIX0AD03 PCIX0AD02 PCIX0AD01 PCIX0AD00 PCIX0Stop PCIX0BE7 PCIX0AD54 PCIX0BE6 PCIX0AD40 PCIX0AD32 MemAddr03 MemAddr01 MemAddr06 ClkEn0 ClkEn1 MemData01 MemData05 Ball AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 Signal Name AP0VDD PCIX0AD26 P2VDD PCIX0AD20 PCIX0AD19 PCIX0AD16 PCIX0AD17 PCIX0AD23 PCIX0BE0 PCIX0AD04 GPIO03* PCIX0Clk PCIX0Gnt0* PCIX0AD52 PCIX0AD51 PCIX0AD33 MemAddr11 ECC7 MemAddr07 MemAddr08 MemAddr00 MemAddr14 MemData06 SVDD MemData02 A2VDD Ball AG01 AG02 AG03 AG04 AG05 AG06 AG07 AG08 AG09 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28
PowerPC 440SP Embedded Processor
Signal Name AP0GND PCIX0ECC2 PCIX0AD22 PCIX0Par P0VDD PCIX0Req64 PCIX0BE1 P0VDD PCIX0Req1* PCIX0Gnt1* P0VDD P0VDD PCIX0AD50 PCIX0BE5 P0VDD PCIX0AD35 MemAddr10 P0VDD MemAddr09 MemClkOut0 MemClkOut0 A2GND Ball AH01 AH02 AH03 AH04 AH05 AH06 AH07 AH08 AH09 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 PCIX0AD24 PCIX0AD25 PCIX0ECC3 PCIX0ECC4 PCIX0Ack64 PCIX0AD15 PCIX0AD05 PCIX0AD06 PCIX0VC PCIX0Req0* PCIX0Reset PCIX0Par64 PCIX0AD53 PCIX0BE4 PCIX0AD49 PCIX0AD34 MemAddr12 MemAddr13 MemAddr04 MemAddr05 MemClkOut1 MemClkOut1 Signal Name
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PowerPC 440SP Embedded Processor Signal Description
PPC440SP embedded controller packaged 783-ball flip-chip plastic ball grid array (FC-PBGA). following table describes package level pinout. Table Summary
Group
Signal pins, non-multiplexed Signal pins, multiplexed Total Signal Pins AxVDD APxVDD AxGND OVDD (3.3V I/Os) PxVDD (3.3V-1.5V PCI) SVDD G(2.5-1.8V SDRAM) (1.5V Logic) Total Power Pins Reserved Total Pins
Pins
table "Signal Functional Description" page each signal listed along with short description function. Active-low signals (for example, RAS) marked with overline. Please "Signals Listed Alphabetically" page (ball) number which each signal assigned.
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Multiplexed Signals
PowerPC 440SP Embedded Processor
Some signals multiplexed same that used different functions. signal names shown Signal Functional Description accompanied signal names that might multiplexed same pin. need know what, any, signals multiplexed with particular signal, look name "Signals Listed Alphabetically" page expected that single application particular will always programmed serve same function. flexibility multiplexing allows single chip offer richer selection than would otherwise possible. Strapping Pins group pins used strapped inputs during system reset. These pins function strapped inputs only during reset used other functions during normal operation (see "Strapping" page 81). Note that these multiplexed pins since function pins programmable. Multipurpose Signals addition multiplexing, some pins also multi-purpose. example, PCIX0Ack function instead PCIX0ECC1 depending interface mode operation.
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PowerPC 440SP Embedded Processor
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name PCI-X0:2 Interfaces Ack64 ECC1. Normally used Ack64 indicating that target transfer data using bits. Used ECC1 PCIX2 mode Address/Data (bidirectional) PCI-X0 PCI-X1. Address/Data (bidirectional) PCI-X PCI-X Byte Enables PCI-X0 PCI-X1. PCI-X Byte Enables PCI-X2. External calibration resistor pads PCI-X0:2 (one each 32-bit group). External calibration resistor pads PCIX0:2 (one each 32-bit group). Capable PCI-X operation. This analog input sampled configure determine state PCIX0:2VC output signal: 0.00VDD (0.0V) Conventional PCIX0:2VC 0.49VDD (1.6V) PCI-X Mode PCIX0:2VC 0.75VDD (2.5V) PCI-X PCIX0:2VC 1.00VDD (3.3V) PCI-X PCIX0:2VC Provides timing interface transactions. PCIX0:2Clk 3.3V 1.5V mode 3.3V 1.5V mode 3.3V 1.5V mode Description Type
Notes
PCIX0:2Ack64/PCIX2ECC1
PCIX0:1AD63:00 PCIX2AD31:00 PCIX0:1BE7:0 PCIX2BE3:0 PCIX0:1CalG0:1 PCIX2CalG0 PCIX0:1CalR0:1 PCIX2CalR0
PCIX0:2Cap
Note: PCI-X interface being used, drive this
with 3.3V clock signal frequency between 66MHz Indicates driving device decoded address target current access. check bits 5-2. bits valid only PCIX mode
3.3V
PCIX0:2DevSel
3.3V
PCIX0:2ECC5:2
Note: PCIX2Par ECC0.
PCIX2Ack64 ECC1. PCIX2Req64 ECC6. PCIX1Par64 ECC7. Driven current master indicate beginning duration access. Indicates that specified agent granted access bus. When using external PCI/PCI-X arbiter, connect external arbiter's Grant line this signal. Used chip select during configuration read write transactions. Level sensitive interrupt.
3.3V 1.5V mode
PCIX0:2Frame PCIX0:2Gnt0:1 PCIX0:1Gnt2:3 PCIX0:2IDSel PCIX0:2INTA
3.3V
3.3V
3.3V 3.3V
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Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name PCIX0:2IRDY Description
PowerPC 440SP Embedded Processor
Type 3.3V 3.3V 1.5V mode 3.3V 1.5V mode 3.3V 1.5V mode
Notes
Indicates initiating agent's ability complete current data phase transaction. Capable 66MHz operation.
PCIX0M66En
PCIX1:2M66En
Capable 66MHz operation. Even parity indicator ECC0. Normally used indicate even parity across PCIAD31:00 BE3:0. Used ECC0 PCIX0:2 mode Even parity indicator ECC7. Normally used indicate even parity across PCIAD63:32 BE7:4 PCI0 PCI1. Used ECC7 PCIX0:1 mode Reports data parity errors during transactions except Special Cycle. indication PCI-X arbiter that specified agent wishes bus. When using external PCI/PCI-X arbiter, connect external arbiter's Request line this signal. Request 64-bit transfer ECC6. Normally used current master indicate 64-bit transfer. Used ECC6 PCIX2 mode Sets device registers logic consistent state. Reports address parity errors, data parity errors Special Cycle command, other catastrophic system errors. Indicates current target requesting master stop current transaction.
PCIX0:2Par/PCIX0:2ECC0
PCIX0:1Par64/PCIX0:1ECC7
3.3V 1.5V mode
PCIX0:2PErr
3.3V
PCIX0:2Req0:1 PCIX0:1Req2:3
3.3V
PCIX0:2Req64/PCIX2ECC6
3.3V 1.5V mode 3.3V 3.3V
PCIX0:2Reset PCIX0:2SErr
PCIX0:2Stop PCIX0:2TRDY
3.3V 3.3V
Indicates target agent's ability complete current data phase transaction.
Voltage control output. Used control voltage regulator supplying voltage. PCI-XCap signal. 3.3V (PCI I/O) =1.5V (PCI-X DDR) Voltage reference input PCI-X (1.5V) I/O.
PCIX0:2VC
3.3(1.5)V
PCIX0:2VRef0:1
VPCIXDDR R0:1
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PowerPC 440SP Embedded Processor
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name SDRAM Interface BA0:2 BankSel0:1 ClkEn0:1 DM0:8 DQS0:8 DQS0:8 ECC0:7 MemAddr14:00 MemClkOut0:1 MemClkOut0:1 MemData63:00 MemDCFdbkD MemDCFdbkR MemODT0:1 Bank Address supporting eight internal banks. Selects external SDRAM banks. Column Address Strobe. Clock Enable. each external bank. Memory write data byte lane masks. MEMDM8 byte lane mask byte lane. Byte lane data strobe. DQS8 data strobe byte lane. These signals differential pairs. check bits 0:7. Memory address bus. 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM DIFF 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM DIFF 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM Volt 2.5(1.8)V SDRAM Volt 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM Description Type
Notes
Note: MemAddr14 most significant (msb).
Subsystem clocks. These signals differential pairs. Memory data bus.
Note: MemData63 most significant (msb).
Feedback driver, timing measurements. Feedback receiver. Connect externally MemDCFdbkD. Memory on-die termination control.
MemVRef0
Memory reference voltage (SVREF) input.
MemVRef1
Memory reference voltage (SVREF) supplemental input.
Address Strobe. Write Enable.
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Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Ethernet Interface EMCCD EMCCrS EMCMDClk EMCMDIO EMCRxD0:7 EMCRxDV EMCRxErr EMCRxClk EMCRefClk EMCTxClk EMCGTxClk EMCTxD0:7 EMCTxEn EMCTxErr, Collision detection. Carrier sense. Management data clock. Description
PowerPC 440SP Embedded Processor
Type
Notes
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Transfer command status information between PHY. Receive data. Receive data valid. Receive error. Receive clock. Reference clock. Transmit clock. Ethernet gigabit transmit clock. Transmit data. Transmit data enabled. Transmit error.
External Slave Peripheral Interface PerAddr00:23 PerBE0 PerBLast PerCS0:2 PerData0:7 Peripheral address bus.
Note: PerAddr00 most significant (msb).
External peripheral data byte enable. Used peripheral controller indicates last transfer memory access. External peripheral device select. Peripheral data bus.
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Note: PerData0 most significant (msb).
Used peripheral controller controller depending upon type transfer involved. When PPC440SP master, enables selected SDRAMs drive bus. External peripheral data byte parity. Used peripheral slave indicate ready transfer data. Used output peripheral controller. High indicates read from memory, indicates write memory. Write Enable. Peripheral clock used synchronous peripheral slaves. External error used input record external slave peripheral errors.
PerOE
3.3V LVTTL
PerPar0 PerReady
3.3V LVTTL 3.3V LVTTL
PerR/W PerWE PerClk PerErr
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
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PowerPC 440SP Embedded Processor
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name UART Peripheral Interface Serial clock input that provides alternative internally generated serial clock. Used cases where allowable internally generated clock rates satisfactory. UART0 Receive data. UART0 Transmit data. UART0 Data Carrier Detect. UART0 Data Ready. UART0 Clear Send. UART0 Data Terminal Ready. UART0 Request Send. UART0 Ring Indicator. UART1 Receive data. UART1 Transmit data. UART1 Data Ready Clear Send. choice determined register setting. UART1 Request Send Data Terminal Ready. choice determined register setting. UART2 Receive data. UART2 Transmit data. Description Type
Notes
UARTSerClk
3.3V LVTTL
UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RTS UART0_RI UART1_Rx UART1_Tx UART1_DSR/CTS UART1_DTR/RTS UART2_Rx UART2_Tx Peripheral Interface IIC0SClk IIC0SDA IIC1SClk IIC1SDA Interrupts Interface IRQ0:5
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
IIC0 Serial Clock. IIC0 Serial Data. IIC1 Serial Clock. IIC1 Serial Data.
3.3V 3.3V 3.3V 3.3V
External interrupt Requests through
3.3V LVTTL
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Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name System Interface Halt GPIO00:17 GPIO18:29 GPIO30:31 SysClk SysErr SysPartSel Halt from external debugger. Description
PowerPC 440SP Embedded Processor
Type
Notes
3.3V LVTTL 3.3V LVTTL 3.3V 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
General purpose through access these functions, software must register bits. General purpose through access these functions, software must register bits. General purpose through access these functions, software must register bits. Main system clock input. when machine check generated. used. Main system reset. External logic drive this bidirectional (minimum cycles) initiate system reset. system reset also initiated software. Hardware initiated self-refresh system reset. External Reset. During PPC440SP's reset phase, this signal down level. Test Enable. Processor timer external input clock.
SysReset
3.3V LVTTL
HISRRst ExtReset TestEn TmrClk JTAG Interface TRST Trace Interface TrcClk TrcBS0:2 TrcES0:4 TrcTS0:6
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Test Clock. Test Data Test Data Out. Test Mode Select. Test Reset.
3.3V LVTTL 3.3V LVTTL w/pull-down 3.3V LVTTL tolerant 2.5V CMOS tolerant 2.5V CMOS
Trace data capture clock, runs frequency processor. Trace branch execution status. Trace Execution Status presented every fourth processor clock cycle. Additional information trace execution branch status.
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
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Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Power AxGND Analog ground. Analog voltage-1.5V. Filtered voltages input PLLs (analog circuits). Description Type
Notes
APxVDD
Note: separate filter analog voltages
recommended. Analog voltage-1.5V. Filtered voltages input system PLLs (analog circuits).
AxVDD
Note: separate filter analog voltages
recommended. Logic ground. supply (except SDRAM PCI-X)- 3.3V. PCI-X voltage supply.
OVDD PxVDD
Note: PCI-X operates 3.3V.
PCI-X operates 1.5V SDRAM voltage supply.
SVDD PSRO
Note: SDRAM operates 2.5V
DDR2 SDRAM operates 1.8V Logic voltage supply-1.5V.
Performance Screen Ring Oscillator. PSRO Reserved Reserved connect voltage, ground, signals these pins.
Note: PSRO signals should connected logic
ground (GND).
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Device Characteristics
Table Absolute Maximum Ratings
PowerPC 440SP Embedded Processor
absolute maximum ratings below stress ratings only. Operation beyond these maximum ratings cause permanent damage device. None performance specifications contained this document guaranteed when operating these maximum ratings.
Characteristic 1.5V Supply Voltage (Internal logic) 3.3V Supply Voltage (I/O interface, except SDRAM) 3.3V Supply Voltage (PCI-X I/O) 1.5V Supply Voltage (PCI-X I/O) 1.5V Supply Voltages (System PLLs) 1.5V Supply Voltages (PCI-X PLLs) 2.5V Supply Voltage (DDR SDRAM logic) 1.8V Supply Voltage (DDR2 SDRAM logic) 3.3V LVTTL receivers Input Voltage Storage temperature range Case temperature under bias Notes: analog voltages used on-chip PLLs derived from logic voltage, must filtered before entering PPC440SP. separate filter, shown below, recommended each voltage: AxVDD, APxVDD Symbol OVDD PxVDD PxVDD AxVDD APxVDD SVDD SVDD TSTG Value +1.6 +3.6 +3.6 +1.6 +1.6 +1.6 +2.7 +1.95 +3.6 +150 +120 Unit Notes
ferrite bead chip, Murata BLM31A700S ceramic
This value specification operational temperature range, stress rating only.
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Table Package Thermal Specifications
Thermal resistance values PPC440SP package convection environment follows:
Airflow ft/min (m/sec) Junction-to-case thermal resistance Case-to-ambient thermal resistance (w/o heat sink) (0.51) 13.1 Range Minimum Junction-to-ball (typical) Notes: Case temperature, measured center case surface with device soldered circuit board. this part junction temperature case temperature essentially identical. case-to-ambient thermal resistance measured JEDEC JESD51-6 standard environment; accurately predict thermal performance production equipment environments. operational case temperature must maintained. °C/W theoretical using infinite heat sink. larger number applies module mounted 1.8mm thick, card using 1oz. copper power planes, with effective heat transfer area 75mm2. Maximum °C/W (1.02) 11.9 °C/W °C/W
Parameter
Symbol
Unit
Notes
15.5
Table Recommended Operating Conditions (Sheet
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Logic Supply Voltage Logic Supply Voltage Supply Voltage PCI-X Supply Voltage PCI-X DDR1 SDRAM Supply Voltage DDR2 SDRAM System Supply Voltages PCI-X Supply Voltages SDRAM Reference Voltage Symbol OVDD PxVDD Minimum +1.4 +1.425 +3.0 +3.0 1.425 +2.3 +1.4 +1.4 +1.15 Typical +1.5 +1.5 +3.3 +3.3 +2.5 (2.6) +1.5 +1.5 +1.25 Maximum +1.6 +1.575 +3.6 +3.6 1.575 +2.7 +1.6 +1.6 +1.35 Unit Notes
SVDD AxVDD APxVDD SVREF
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Table Recommended Operating Conditions (Sheet
PowerPC 440SP Embedded Processor
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Input Logic High (2.5V SDRAM) Input Logic High (1.8V DDR2 SDRAM) Input Logic High (2.5V CMOS, 3.3V tolerant receiver) Input Logic High (3.3V PCI-X) Input Logic High (1.5V PCI-X DDR) Input Logic High (3.3V LVTTL) Input Logic (2.5V SDRAM) Input Logic (1.8V DDR2 SDRAM) Input Logic (2.5V CMOS, 3.3V tolerant receiver) Input Logic (3.3V PCI-X) Input Logic (1.5V PCI-X DDR) Input Logic (3.3V LVTTL) Output Logic High (2.5V SDRAM) Output Logic High (1.8V DDR2 SDRAM) Output Logic High (2.5V CMOS, 3.3V tolerant receiver) Output Logic High (3.3V PCI-X) Output Logic High (1.5V PCI-X DDR) Output Logic High (3.3V LVTTL) Output Logic (2.5V SDRAM) Output Logic (1.8V DDR2 SDRAM) Output Logic (2.5V CMOS, 3.3V tolerant receiver) Output Logic (3.3V PCI-X) Output Logic (1.5V PCI-X DDR) Output Logic (3.3V LVTTL) Input Leakage Current (with internal pull-up pull-down) Input Leakage Current (with internal pull-down) Input Leakage Current (with internal pull-up) IIL1 IIL2 IIL3 (LPDL) -150 (LPDL) +0.4 (MPUL) (MPUL) 0.1OVDD +2.4 OVDD 0.55 0.9OVDD OVDD -0.5 -0.5 +1.95 0.35OVDD Vref -0.10V +0.8 SVDD 0.5OVDD Vref +0.10 +2.0 -0.3 -0.3 OVDD+0.5 VI/O +0.50 +3.6 SVREF-0.18 Vref -0.125 Symbol Minimum SVREF+0.18 Vref +0.125 Typical Maximum SVDD+0.3 VDDQ Unit Notes
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PowerPC 440SP Embedded Processor
Table Recommended Operating Conditions (Sheet
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Input Allowable Overshoot (3.3V LVTTL) Input Allowable Undershoot (3.3V LVTTL) Output Allowable Overshoot (3.3V LVTTL) Output Allowable Undershoot (3.3V LVTTL) Case Temperature Notes: PCI-X drivers meet PCI-X specifications. SVREF SVDD/2 analog voltages used on-chip PLLs derived from logic voltage, must filtered before entering PPC440SP. "Absolute Maximum Ratings" page Power supply sequencing: recommended that 1.5V core reach nominal value before applying power I/Os. Voltage applied I/Os from external source must allowed exceed 0Vdd ramp. power down cycle must complete (0Vdd below 0.4V) before power cycle started. LPDL least positive down level; MPUL most positive level. Case temperature, measured center case surface with device soldered circuit board. Symbol VIMAO VIMAU VOMAO VOMAU3 -0.6 +100 -0.6 +3.9 Minimum Typical Maximum +3.9 Unit Notes
Table Input Capacitance
Parameter Group (2.5V SSTL I/O) Group (3.3V LVTTL I/O) Group (PCI-X I/O) Group (Receivers) Group (3.3V tolerant CMOS I/O) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Maximum Unit Notes
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PowerPC 440SP Embedded Processor
Table Power Supply Loads
Parameter (1.5V) active operating current OVDD (3.3V) active operating current PxVDD (3.3V) active operating current PxVDD (1.5V) active operating current SVDD (2.5V) active operating current SVDD (1.8V) active operating current AxVDD (1.5V) input current APxVDD (1.5V) input current Symbol IODD IPDD IPDD ISDD ISDD IADD IAPDD Minimum Typical Maximum 3000 1600 1100 Unit Notes
Notes: "Absolute Maximum Ratings" page filter recommendations. Valid only CPU/PLB/OPB 533.33/133.33/66.66 MHz.
Test Conditions
Clock timing switching characteristics specified accordance with operating conditions shown table "Recommended Operating Conditions." specifications characterized with 1.5V, 10pF test load shown figure right.
Output
10pF
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PowerPC 440SP Embedded Processor
Table Clocking Specifications
Symbol SysClk Input Frequency Period Edge stability High time time 33.33 nominal period nominal period 83.33 0.15 Parameter
Units
nominal period nominal period
Note: Input slew rate 1V/ns
Processor Clock MemClkOut Clock Frequency Period 83.33 Frequency Period High time nominal period 333.33 nominal period Frequency Period 666.66 Frequency Period 0.75 1333.33 1.66
Figure Clock Timing Waveform
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Spread Spectrum Clocking
PowerPC 440SP Embedded Processor
Care must taken when using spread spectrum clock generator (SSCG) with PPC440SP. This controller uses clock generation inside chip. accuracy with which follows SSCG referred tracking skew. bandwidth phase angle determine much tracking skew there between SSCG given frequency deviation modulation frequency. When using SSCG with PPC440SP following conditions must met: frequency deviation must violate minimum clock cycle time. Therefore, when operating PPC440SP with more internal clocks their maximum supported frequency, SSCG only lower frequency. maximum frequency deviation cannot exceed -1%, modulation frequency cannot exceed kHz. some cases, on-board PPC440SP peripherals impose more stringent requirements. Peripheral Clock logic that synchronous peripheral since this clock tracks modulation. SDRAM MemClkOut since also tracks modulation. PCI-X maximum spread spectrum modulated between 30kHz 33kHz. Notes: serial port baud rates synchronous modulated clock. serial port tolerance approximately 1.5% baud rate before framing errors begin occur. 1.5% tolerance assumes that connected device running precise baud rates. Ethernet operation unaffected. operation unaffected. Important: system designer ensure that SSCG used with PPC440SP meets above requirements does adversely affect other aspects system.
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PowerPC 440SP Embedded Processor Specifications
Table Peripheral Interface Clock Timings
Parameter PCIXxClk input frequency (asynchronous mode) PCIXxClk period (asynchronous mode) PCIXxClk input high time PCIXxClk input time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output time EMCTxClk input frequency EMCTxClk period EMCTxClk input high time EMCTxClk input time EMCRxClk input frequency EMCRxClk period EMCRxClk input high time EMCRxClk input time PerClk output frequency (for sync. slaves) PerClk period PerClk output high time PerClk output time UARTSerClk input frequency UARTSerClk period UARTSerClk input high time UARTSerClk input time TmrClk input frequency TmrClk period TmrClk input high time TmrClk input time Notes: nominal period nominal period nominal period nominal period nominal period nominal period nominal period nominal period 2TOPB+2 TOPB+1 TOPB+1 nominal period nominal period 133.33 nominal period nominal period 83.33 nominal period nominal period 1000/(2TOPB+2ns) nominal period nominal period
Units
Notes
TOPB period clock. internal clock runs integral divisor ratio frequency clock. maximum clock frequency 83.33 MHz. Refer Clocking chapter PPC440SP Embedded Processor User's Manual details. When PCI-X interface used support legacy interface, maximum PCIXClk frequency 66.66MHz.
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Input/Output Timing
PowerPC 440SP Embedded Processor
These timing diagrams illustrate relationship timing parameters defined Specification tables that follow. Figure Input Setup Hold Timing Waveform
Clock
Inputs Valid
Figure Output Delay Hold Timing Waveform
Clock
Outputs
High (Drive) Float (High-Z) (Drive) Valid Valid
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PowerPC 440SP Embedded Processor
Table Specifications-All Speeds
(Sheet Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133.33MHz. PCI-X input setup time requirement 1.2ns 133.33MHz 1.7ns 66.66MHz. timings parentheses) asynchronous operation 66.66MHz. output hold time requirement 66.66MHz 33.33MHz. These signals that change both positive negative clock transitions.
Input (ns) Signal PCI-X Interfaces PCIX0:2Ack64 PCIX0:1AD63:00 PCIX2AD31:00 PCIX0:1BE7:0 PCIX2BE3:0 PCIX0:2CalG0:1 PCIX0:1CalR0:1 PCIX0:2Cap PCIX0:2Clk PCIX0:2DevSel PCIX0:2ECC5:2 PCIX0:2Frame PCIX0:2Gnt0 PCIX0:2Gnt1 PCIX0:1Gnt2:3 PCIX0:2IDSel PCIX0:2INTA PCIX0:2IRDY PCIX0:1M66En PCIX0:2Par PCIX0:1Par64 PCIX0:2PErr PCIX0:1Req0 PCIX0:1Req1:3 PCIX2Req1 PCIX0:2Req64 PCIX0:2Reset PCIX0:2SErr PCIX0:2Stop PCIX0:2TRDY PCIX0:2VC Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk PCIX0:2Clk async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
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Table Specifications-All Speeds
PowerPC 440SP Embedded Processor
(Sheet Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133.33MHz. PCI-X input setup time requirement 1.2ns 133.33MHz 1.7ns 66.66MHz. timings parentheses) asynchronous operation 66.66MHz. output hold time requirement 66.66MHz 33.33MHz. These signals that change both positive negative clock transitions.
Input (ns) Signal Ethernet Interface EMCCD EMCCrS EMCMDClk EMCMDIO EMCRxD0:7 EMCRxDV EMCRxErr EMCRxClk EMCRefClk EMCTxClk EMCGTxClk EMCTxD0:7 EMCTxEn EMCTxErr, IIC0SClk IIC0SDA IIC1SClk IIC1SDA UARTSerClk UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RI UART0_RTS UART1_Rx UART1_Tx UART1_DSR/CTS UART1_RTS/DTR UART2_Rx UART2_Tx Interrupts Interface IRQ0:5 JTAG Interface TRST 19.1 async async async async async async 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 15.3 15.3 15.3 15.3 19.1 10.2 10.2 10.2 10.2 UARTSerClk UARTSerClk async async async async async async UARTSerClk UARTSerClk async async UARTSerClk UARTSerClk IIC0SClk IIC0SClk EMCTxClk EMCTxClk EMCTxClk async async EMCMDClk EMCRxClk EMCRxClk EMCRxClk async async async async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
Internal Peripheral Interface
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PowerPC 440SP Embedded Processor
Table Specifications-All Speeds
(Sheet Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133.33MHz. PCI-X input setup time requirement 1.2ns 133.33MHz 1.7ns 66.66MHz. timings parentheses) asynchronous operation 66.66MHz. output hold time requirement 66.66MHz 33.33MHz. These signals that change both positive negative clock transitions.
Input (ns) Signal System Interface Halt GPIO00:31 SysClk SysErr SysPartSel SysReset HISRRst TestEn TmrClk Trace Interface TrcClk TrcBS0:2 TrcES0:4 TrcTS0:6 19.1 19.1 19.1 19.1 19.1 19.1 19.1 async async async async async async async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
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Table Specifications-533MHz
PowerPC 440SP Embedded Processor
Notes: PerClk rising edge package with 10pF load trails internal clock approximately 1.3ns.
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) 19.1 27.7 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 (minimum) 12.8 Clock Notes
External Slave Peripheral Interface PerAddr00:23 PerBE0 PerBLast PerCS0:2 PerData0:7 PerOE PerPar0 PerReady PerR/W PerWE ExtReset PerClk PerErr PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk
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PowerPC 440SP Embedded Processor SDRAM Specifications
SDRAM controller times operation with internal clock signals generates MemClkOut0 from clock. clock internal signal that cannot directly observed. However MemClkOut0 same frequency clock signal phase with clock signal. Note: MemClkOut0 advanced with respect clock means SDRAM0_CLKTR programming register. typical system, users advance MemClkOut This depends specific application requires thorough understanding memory system general (refer SDRAM controller chapter PPC440SP Embedded Processor User's Manual). following sections, label MemClkOut0(0) refers MemClkOut0 when been phase-shifted, MemClkOut0(90) refers MemClkOut0 when been phase-advanced 90°. Advancing MemClkOut0 creates cycle setup time cycle hold time address control signals relation MemClkOut0(90). rising edge MemClkOut0(90) aligns with first rising edge signal. following data generated means simulation includes logic, driver, package RLC, lengths. used circuit design recommendation. Values calculated over best case worst case processes with speed, temperature, voltage follows: Best Case Fast process, +1.6V Worst Case Slow process, +1.4V Note: following tables timing diagrams, minimum values measured under best case conditions maximum values measured under worst case conditions. signals terminated indicated figure below timing data following sections. Figure SDRAM Simulation Signal Termination Model
MemClkOut0 120W MemClkOut0
PPC440SP
SVDD/2
Addr/Ctrl/Data/DQS
30pF
Note: This diagram illustrates model SDRAM interface used when generating simulation timing data. recommended physical circuit design this interface. actual interface design will depend many factors, including type memory used board layout.
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Table SDRAM Output Driver Specifications
PowerPC 440SP Embedded Processor
Output Current (mA) Signal Path (maximum) Write Data MemData00:07 MemData08:15 MemData16:23 MemData24:31 MemData32:39 MemData40:47 MemData48:55 MemData56:63 ECC0:7 DM0:8 MemClkOut0 MemAddr00:12 BA0:1 BankSel0:3 ClkEn0:3 DQS0:8 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 (minimum)
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PowerPC 440SP Embedded Processor SDRAM Write Operation
following timing chart shows relationship between signals involved write operation. Figure SDRAM Write Cycle Timing
MemClkOut Addr/Cmd
MemData
Setup time address command signals MemClkOut Hold time address command signals from MemClkOut Setup time data signals (minimum time data valid before rising/falling edge DSQ) Hold time data signals (minimum time data valid after rising/falling edge DSQ) Delay from rising/falling edge clock rising/falling edge
SDRAM Read Write Timing-TSA
Note Clock speed MHz. referenced MemClkOut. Note Memory clock signal shifted from internal clock. Table SDRAM Read Write Timing-TSA
Signal Name MemAddr00:12 BA0:1 BankSel0:3 ClkEn0:3 (ns) Minimum 1.32 1.15 1.12 1.29 1.24 1.29 1.35 (ns) Minimum 1.49 1.52 1.45 1.14 1.48 1.43
AMCC Proprietary
Revision 1.12 November 2005
SDRAM Clock Write Timing-TDS
Note signals referenced MemClkOut. Note Clock speed MHz.
PowerPC 440SP Embedded Processor
Note values table include cycle ns). Note obtain adjusted values lower clock frequencies, subtract from values following table cycle time lower clock frequency (TDS TCYC).
Table SDRAM Clock Write Timing-TDS
(ns) Signal Name Minimum DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 4.76 4.78 4.78 4.76 4.79 4.80 4.81 4.79 4.77 Maximum 5.07 5.09 5.10 5.07 5.11 5.13 5.11 5.11 5.07
SDRAM Write Data Timing-TSD
Note measured under worst-case conditions. Note Clock speed values following table MHz.
Table SDRAM Write Data Timing-TSD
Signal Name MemData00:07, MemData08:15, MemData16:23, MemData24:31, MemData32:39, MemData40:47, MemData48:55, MemData56:63, ECC0:7, Reference Signal DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 (ns) 0.58 0.62 0.62 0.63 0.68 0.67 0.62 0.65 0.63 (ns) 0.64 0.55 0.60 0.57 0.54 0.52 0.61 0.55 0.61
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PowerPC 440SP Embedded Processor SDRAM Read Operation
read incoming data from SDRAM done rising falling edges differential signal. data must centered these edges correct operation. PPC440SP delay very small increments means programming MCIF0_RODC[RQFD] register field. SDRAM MemClkOut0 Read Clock Delay accommodate timing variations introduced system designs using this chip, three-stage data path shown Figure below, used eliminate metastability allow data sampling adjusted minimum latency. data stored eight Flip Flops Stage that transferred later, within period. Figure SDRAM Read Data Path.
FeedBack Signals
Clock
Flip-Flop
MemDCFdbkD Driver
Coarse Delay
FeedBack Signal
Delay
Read Start Read Latency adjust circuit
MCIF0_RFDC[RFFD]
Fine Delay
Clock
Stage Store Oversampling Fine Delay
MemDCFdbkR
Feedback Data Capture Window
aligned signal
Cycles Delay
MCIF0_RFDC[RFOS]
MCIF0_RDCC[RDSS]
adjust Oversampling Clock
Q2_Ovs
Package pins
Compare
(x64)
Read FIFO Upper
[0:63]
Data (x64)
Rising Edge Sync Stage
Stage (x64)
Lower
Stage
[64:127]
(Diff)
Programmed Read Delay
Falling Edge Sync Clock Clock
MCIF0_RQDC[RQFD]
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Revision 1.12 November 2005
Table SDRAM Read Timing-TSD
PowerPC 440SP Embedded Processor
Notes: measured under worst case conditions. Clock speed values table 333.33MHz. time values table include cycle 166MHz (3ns 0.25 0.75 ns). obtain adjusted values lower clock frequencies, subtract 0.75 from values table cycle time lower clock frequency (e.g., 0.75 0.25TCYC).
Signal Names MemData00:07 MemData08:15 MemData16:23 MemData24:31 MemData32:39 MemData40:47 MemData48:55 MemData56:63 ECC0:7 Reference Signal DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 Read Data Setup (ns) 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 Read Data Hold (ns) 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00
Figure shows data strobe (DQS) data coincident. There actually slight skew specified SDRAM specifications, there additional skew loading signal routing. recommended that signal length eight signals matched. Figure SDRAM Memory Data
MemData
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PowerPC 440SP Embedded Processor
following figure shows timing relationship between SDRAM Data input store data stage Figure SDRAM Read Cycle Timing Example
Oversampling Guard Band Clock Clock Memclk (Diff.) MemCntl Data
FeedBack output cycle Delayed
Store Data Stage
Data Stage Data Stage
Data Stage Valid High Data Stage
Clock
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Initialization
PowerPC 440SP Embedded Processor
PPC440SP provides option setting initial parameters based default values reading them from serial "bootstrap" attached IIC0 bus. These options defined strapping three external pins (see "Strapping" below).
Strapping
While SysReset input (system reset), state certain pins read enable certain default initial conditions prior PPC440SP start-up. actual capture instant nearest SysClk edge before deassertion reset. These pins must strapped using external pull-up (logical pull-down (logical resistors select desired default conditions. They used strap functions only during reset. Following reset they used normal functions. Figure lists strapping pins along with their functions strapping options:
Table Strapping Assignments
Strapping Function Option (UART0_DCD) (UART0_DSR) Bit2 (UART0_CTS)
Serial Bootstrap disabled (Bit off). Refer Bootstrap Controller chapter PPC440SP Embedded Processor User's Manual details. Serial Bootstrap enabled (Bit on). options being selected IIC0 slave address that responds with strapping data reading bits from Bootstrap ROM. Serial Bootstrap enabled (Bit on). options being selected IIC0 slave address that responds with strapping data reading bits from Bootstrap ROM.
Boot from Boot from 0x54 0x50 0x54 0x50
Serial Bootstrap
During reset, serial device enabled, initial conditions read from connected IIC0 port. this case, de-assertion SysReset, PPC440SP sequentially reads bytes from device IIC0 port uses first bytes SDR0_STRP0 SDR0_STRP1 registers accordingly. Otherwise, default values CPR0 SDR0 registers used initialization. initialization settings their default values described detail PPC440SP Embedded Processor User's Manual.
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Revision 1.12 November 2005
PowerPC 440SP Embedded Processor Document Revision History
Revision
1.12 1.11 1.10 1.09
Date
2005 July 2005 2005 2005
Description
Clarified information about SDRAM specifications, updated note system memory address table updated ordering information, part number list, package diagram, deleted Preliminary from running head. Updated leakage current info, case temp range, SDRAM Signal Termination graphic. Changed numbers pass Corrected functional block diagram. Updated Write timing diagrams. Changed part numbers Ordering Information section reflect pass Removed text unsupported COLA component. Added table document muxed usage GPIO signals. Removed additional references unsupported COLA serial interface. Reformatted comply with AMCC style. Updated Description information first page, sections power supply loads recommended operating conditions. Remove references unsupported COLA serial interface. Update case temp Recommended Conditions table match Ordering Information table. Update Order Part Number information, SDRAM Read data Path block diagram, SDRAM Read Cycle Timing example diagram Update Ordering information. Update table Recommended Operating Conditions section Docs Issue Database #12. Update functional block diagram text, signal functional description table, recommended operating conditions section with GB's comments. First official draft. Create initial data sheet.
1.08
2005
1.07 1.06 1.05 1.04 1.03 1.02 1.01 1.00
2005 2004 2004 2004 2004 2004 Sept 2004 2003
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PowerPC 440SP Embedded Processor
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