SMALL-OUTLINE SDRAM MODULE JEDEC-standard PC100 PC133 compliant 1

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SMALL-OUTLINE SDRAM MODULE JEDEC-standard PC100 PC133 compliant 1

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32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
SMALL-OUTLINE SDRAM MODULE
JEDEC-standard PC100 PC133 compliant 144-pin, small-outline, dual in-line memory module (SODIMM) Unbuffered 32MB (4Meg 64), 64MB 64), 128MB Single +3.3V ±0.3V power supply Fully synchronous; signals registered positive edge system clock Internal pipelined operation; column address changed every clock cycle Internal SDRAM banks hiding access/precharge Programmable burst lengths: full page Auto Precharge Auto Refresh Modes Self Refresh Mode: Standard Power 32MB 64MB: 64ms, 4,096-cycle refresh (15.625µs refresh interval); 128MB: 64ms, 8,192cycle refresh (7.81µs refresh interval) LVTTL-compatible inputs outputs Serial Presence-Detect (SPD)
MT4LSDT464(L)H(I) 32MB MT4LSDT864(L)H(I) 64MB MT4LSDT1664(L)H(I) 128MB
latest data sheet, please refer Micron site: www.micron.com/moduleds
144-Pin SODIMM 190)
ADDRESS TABLE
32MB MODULE 64MB MODULE 128MB MODULE
OPTIONS
Self Refresh Current Standard Low-Power1 Operating Temperature Range Commercial (0°C 70°C) Industrial (-40°C +85°C)2 Package 144-pin SODIMM (gold) Memory Clock/CAS Latency 7.5ns (133 MHz)/CL 7.5ns (133 MHz)/CL 10ns (100 MHz)/CL
NOTE:
MARKING
None
Refresh Count Device Banks (BA0, BA1) (BA0, BA1) (BA0, BA1) Device Conf. (A0-A11) (A0-A11) (A0-A12) Addr. Column Addr. (A0-A7) (A0-A8) (A0-A8) 1(S0) 1(S0) 1(S0) ModuleBanks
TIMING PARAMETERS
None
-13E -133 -10E MODULE MARKINGS -13E -133 -10E PC100 tRCD 2-2-2 2-2-2 2-2-2 PC133 tRCD 2-2-2 3-3-3
Power Industrial Temperature options available concurrently. Consult Micron available option combinations. Consult Micron availability; Industrial Temperature option available -133 speed only.
16Meg SDRAM SODIMMs SD4C4_8_16X64HG_B.fm Rev. 8/02
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32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
PART NUMBERS
PART NUMBER1 MT4LSDT464(L)H(I)G-13E_ MT4LSDT464(L)H(I)G-133_ MT4LSDT464(L)HG-10E_ MT4LSDT864(L)H(I)G-13E_ MT4LSDT864(L)H(I)G-133_
NOTE: designators component revision last characters each part number. Consult factory current revision codes. Example: MT4LSDT1664HG-133B1
CONFIGURASYSTEM TION SPEED
PART NUMBER1 MT4LSDT864(L)HG-10E_ MT4LSDT1664(L)H(I)G-13E_ MT4LSDT1664(L)H(I)G-133_ MT4LSDT1664(L)HG-10E_
CONFIGURASYSTEM TION SPEED
ASSIGNMENT (144-PIN SODIMM FRONT)
NOTE:
ASSIGNMENT (144-PIN SODIMM BACK)
SYMB SYMBO SYMBO SYMBO SYMBO DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB4 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CKE0 CAS# NC/A121 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB6 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SYMB DQMB0 DQMB1
SYMB DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 RAS#
SYMB DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQMB2 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Connect 32MB 64MB modules, 128MB modules.
Locations (144-PIN SODIMM)
Front View
Back View
(all pins)
(all even pins)
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32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
DESCRIPTIONS
numbers correlate with symbols. Refer Assignment table number symbol information.
NUMBERS
SYMBOL
RAS#, CAS#,
TYPE
Input
DESCRIPTION
CKE0
115, 116, 117,
DQMB0-DQMB7
106,
BA0,
31,32, (128MB), 103, 104, 105, 109, 111,
A0-A11 (32MB, 64MB) A0-A12 (128MB)
100, 121, 122, 123, 124, 125, 126, 127, 128, 131, 132, 133, 134, 135, 136, 137, 101, 102, 113, 114, 129, 130, 143,
DQ0-DQ63
Command Inputs: RAS#, CAS#, (along with define command being entered. Input Clock: driven system clock. SDRAM input signals sampled positive edge also increments internal burst counter controls output registers. Input Clock Enable: activates (HIGH) deactivates (LOW) signal. Deactivating clock provides PRECHARGE POWER-DOWN SELF REFRESH operation (all device banks idle), ACTIVE POWER-DOWN (row ACTIVE device bank) CLOCK SUSPEND operation (burst access progress). synchronous except after device enters power-down self refresh modes, where becomes asynchronous until after exiting same mode. input buffers, including disabled during power-down self refresh modes, providing standby power. Input Chip Select: enables (registered LOW) disables (registered HIGH) command decoder. commands masked when registered HIGH. considered part command code. Input Input/Output Mask: DQMB input mask signal write accesses output enable signal read accesses. Input data masked when DQMB sampled HIGH during WRITE cycle. output buffers placed High-Z state (twoclock latency) when DQMB sampled HIGH during READ cycle. Input Bank Address: define which device bank ACTIVE, READ, WRITE, PRECHARGE command being applied. Input Address Inputs: Provide address ACTIVE commands, column address auto precharge (A10) READ/WRITE commands, select location memory array respective device bank. sampled during PRECHARGE command determines whether PRECHARGE applies device bank (A10 LOW, device bank selected BA0, BA1) device banks (A10 HIGH). address inputs also provide op-code during MODE REGISTER command. Input Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module. Input/ Serial Presence-Detect Data: bidirectional used Output transfer addresses data into presencedetect portion module. Input/ Data I/O: Data bus. Output
Supply
Power Supply: +3.3V ±0.3V.
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32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
DESCRIPTIONS
numbers correlate with symbols. Refer Assignment table number symbol information.
NUMBERS
107, 108, 119, 120, 139, (32MB, 64MB),
SYMBOL
TYPE
Supply
DESCRIPTION
Ground.
Connected: These pins should left unconnected. Use: These pins connected these modules, assigned pins other modules this product family.
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32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
Functional Block Diagram
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQML DQMH DQML DQMH DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQML DQMH DQML DQMH
RAS# CAS# CKE0 A0-A11 (32MB, 64MB) A0-A12 (128MB) BA0-BA1
RAS#: SDRAMs CAS#: SDRAMs CKE0: SDRAMs WE#: SDRAMs A0-A11: SDRAMs A0-A12: SDRAMs BA0-BA1: SDRAMs SDRAMs SDRAMs
Notes: resistor values unless otherwise specified. industry standard, Micron modules various component speed grades referenced module part numbering guide www.micron.com/numberguide.
SDRAMs MT48LC4M16A2TG 32MB module, comm. temp. SDRAMs MT48LC8M16A2TG 64MB module, comm. temp. SDRAMs MT48LC16M16A2TG 128MB module, comm. temp. SDRAMs MT48LC4M16A2TG 32MB module, indust. temp. SDRAMs MT48LC8M16A2TG 64MB module, indust. temp. SDRAMs MT48LC16M16A2TG 128MB module, indust. temp. Industrial Temperature modules -75-speed components only.
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32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
GENERAL DESCRIPTION
MT4LSDT464H, MT4LSDT864H, MT4LSDT1664H high-speed CMOS, dynamic random-access 32MB, 64MB, 128MB unbuffered memory modules, organized configurations. These modules internally configured quadbank SDRAMs with synchronous interface (all signals registered positive edge clock signal CK). four banks x16, 64Mb device (for 32MB modules) each configured 4,096 bit-rows, bit-columns, input/output bits. four banks x16, 128Mb device (for 64MB modules) configured 4,096 bit-rows, columns, input/output bits. four banks x16, 256Mb device (for 128MB modules) configured 8,192 bit-rows, columns, input/output bits. Read write accesses SDRAM modules burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed (BA0, select device bank, A0-A11 [32MB 64MB], A0-A12 [128MB] select device row). address bits A0-A7 (32MB), A0-A8 (64MB 128MB), registered coincident with READ WRITE command, used select starting device column location burst access. These modules provide programmable READ WRITE burst lengths locations, full page, with burst terminate option. auto precharge function enabled provide self-timed precharge that initiated burst sequence. These modules internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows column address changed every clock cycle achieve highspeed, fully random access. Precharging device bank while accessing other three device banks will hide precharge cycles provide seamless, high-speed, random-access operation. These modules designed operate 3.3V, lowpower memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs outputs LVTTL-compatible. SDRAM modules offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with auto4, 16Meg SDRAM SODIMMs SD4C4_8_16X64HG_B.fm 8/02
matic column-address generation, ability interleave between internal banks order hide precharge time capability randomly change column addresses each clock cycle during burst access. more information regarding SDRAM operation, refer 64Mb, 128Mb, 256Mb SDRAM component data sheets.
Serial Presence Detect Operation
These modules incorporate serial presence-detect (SPD). function implemented using 2,048-bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type, SDRAM characteristics module timing parameters. remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals, together with SA(2:0), which provide eight unique DIMM/EEPROM addresses.
REGISTER DEFINITION
Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions device operation.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. Once power applied VDDQ (simultaneously) clock stable (stable clock defined signal cycling within timing constraints specified clock pin), SDRAM requires 100µs delay prior issuing command other than COMMAND INHIBIT Starting some point during this 100µs period continuing least through this period, COMMAND INHIBIT commands should applied. Once 100µs delay been satisfied with least COMMAND INHIBIT command having been applied, PRECHARGE command should applied. device banks must then precharged, thereby placing device banks idle state. Once idle state, AUTO REFRESH cycles must performed. After AUTO REFRESH cycles complete, SDRAM ready mode register
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32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
programming. Because mode register will power unknown state, should loaded prior applying operational command.
Mode Register Definition Diagram
32MB 64MB Module
Address
Mode Register
mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode, write burst mode, shown Mode Register Definition Diagram. mode register programmed LOAD MODE REGISTER command will retain stored information until programmed again device loses power. Mode register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), M4-M6 specify latency, specify operating mode, specifies write burst mode, reserved future use. 128MB module, (A12) undefined, should driven during loading mode register. mode register must loaded when device banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation.
Mode Register (Mx) Reserved*
*Should program M11, ensure compatibility with future devices.
Mode
Latency
Burst Length
128MB Module
Address
Mode Register (Mx)
Reserved* Reserved*
Mode
Latency
Burst Length
*Should program M12, M11, ensure compatibility with future devices. Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved
M6-M0 Defined
Operating Mode Standard Operation other states reserved
Write Burst Mode Programmed Burst Length Single Location Access
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32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
BURST LENGTH Read write accesses SDRAM burst oriented, with burst length being programmable, shown Mode Register Definition Diagram. burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. full-page burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached, shown Burst Definition Table. block uniquely selected (where most significant column address given device configuration) when burst length two; A2-Ai when burst length four; A3-Ai when burst length eight. remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached, shown Burst Definition Table.
BURST DEFINITION TABLE
BURST LENGTH STARTING COLUMN ADDRESS ORDER ACCESSES WITHIN BURST TYPE SEQUENTIAL (location TYPE INTERLEAVED
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0
Full Page
Burst Type
Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Burst Definition Table.
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 supported
32MB modules 64MB 128MB modules
NOTE: full-page accesses: (32MB), (64MB 128MB) burst length two, A1-Ai select block-of-two burst; selects starting column within block. burst length four, A2-Ai select block-of-four burst; A0-A1 select starting column within block. burst length eight, A3-Ai select block-ofeight burst; A0-A2 select starting column within block. full-page burst, full selected A0-Ai select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-Ai select unique column accessed, mode register ignored.
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Latency
latency delay, clock cycles, between registration READ command availability first piece output data. latency three clocks. READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, READ command registered latency programmed clocks, will start driving after data will valid shown Latency Diagram. Latency Table indicates operating frequencies which each latency setting used. Reserved states should used, because unknown operation incompatibility with future versions result.
LATENCY TABLE
ALLOWABLE OPERATING CLOCK FREQUENCY (MHz) SPEED -13E -133 -10E LATENCY LATENCY
Operating Mode
normal operating mode selected setting zero; other combinations values reserved future and/or test modes. programmed burst length applies both READ WRITE bursts. Test modes reserved states should used, because unknown operation incompatibility with future versions result.
Write Burst Mode
When burst length programmed M0M2 applies both READ WRITE bursts; when programmed burst length applies READ bursts, write accesses single-location (nonburst) accesses.
Latency Diagram
COMMAND
READ
DOUT
Latency
COMMAND
READ
DOUT
Latency
DON'T CARE UNDEFINED
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32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
COMMANDS
Truth Table provides quick reference available commands. This followed written description each command. more detailed description commands operations, refer 64Mb, 128Mb, 256Mb SDRAM component data sheet.
TRUTH TABLE SDRAM COMMANDS DQMB OPERATION1
NAME (FUNCTION) COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z
NOTE: HIGH commands shown except SELF REFRESH. A0-A11 (32MB 64MB) A0-A12 (128MB) provide device address, BA0, determine which device bank made active. A0-A7 (32MB) A0-A8 (64MB 128MB) provide device column address; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge feature; BA0, determine which device bank being read from written LOW: BA0, determine which device bank being precharged. HIGH: device banks precharged BA0, "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. A0-A11 define op-code written mode register, 128MB module, should driven low. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
RAS# CAS# DQMB L/H8
ADDR Bank/ Bank/Col Bank/Col Code Op-code
Valid Active Active High-Z
NOTES
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ABSOLUTE MAXIMUM RATINGS*
Voltage VDD, VDDQ Supply Relative +4.6V Voltage Inputs Pins Relative +4.6V Operating Temperature (Ambient). +70°C (Industrial Temperature) -40°C +85°C Storage Temperature (plastic) .-55°C +150°C Power Dissipation. Short Circuit Output Current .50mA *Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
Notes: notes appear following parameter tables; VDD, VDDQ +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input (All other pins under test OUTPUT LEAKAGE CURRENT: pins disabled; VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA) SYMBOL VDD, VDDQ Command Address Inputs DQMB -0.3 UNITS NOTES
SPECIFICATIONS CONDITIONS 32MB MODULE
Notes: notes appear following parameter tables; VDD, VDDQ +3.3V ±0.3V PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT tRFC (MIN) HIGH; HIGH 15.625µs SELF REFRESH CURRENT: 0.2V (Low power available with industrial temperature option) Standard Power SYMBOL IDD1 IDD2 IDD3 -13E -133 -10E UNITS NOTES
IDD4 IDD5 IDD6 IDD7 IDD7
31,32
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32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
SPECIFICATIONS CONDITIONS 64MB MODULE
Notes: notes appear following parameter tables; VDD, VDDQ +3.3V ±0.3V PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT tRFC (MIN) HIGH; HIGH 15.625µs SELF REFRESH CURRENT: 0.2V (Low power available with industrial temperature option) Standard Power SYMBOL IDD1 IDD2 IDD3 -13E -133 -10E UNITS NOTES
IDD4 IDD5 IDD6 IDD7 IDD7
1,320
1,240 1,080
SPECIFICATIONS CONDITIONS 128MB MODULE
Notes: notes appear following parameter tables; VDD, VDDQ +3.3V ±0.3V PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT tRFC (MIN) HIGH; HIGH 7.8125µs SELF REFRESH CURRENT: 0.2V (Low power available with industrial temperature option) Standard Power SYMBOL IDD1 IDD2 IDD3 -13E -133 -10E UNITS NOTES
IDD4 IDD5 IDD6 IDD7 IDD7
1,140
1,080 1,080
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CAPACITANCE
Notes: notes appear following parameter tables. PARAMETER Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, WE#, S0#, CKE0, DQMB0-DQMB7 Input Capacitance: Input/Output Capacitance: SCL, SA0-SA2, Input/Output Capacitance: DQ0-DQ63 SYMBOL 15.2 UNITS
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
Notes: notes appear following parameter tables. Module timing parameters comply with PC100 PC133 Design Specs, based component parameters. CHARACTERISTICS PARAMETER Access time from (positive edge) Address hold time Address setup time high-level width low-level width Clock cycle time SYMBOL
-13E AC(3) AC(2) CK(3) CK(2) HZ(3) HZ(2)
-133
-10E UNITS NOTES
hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time load) ACTIVE PRECHARGE command ACTIVE ACTIVE command period ACTIVE READ WRITE delay Refresh period AUTO REFRESH period PRECHARGE command period ACTIVE bank ACTIVE bank command Transition time WRITE recovery time
7.5ns
120,000
120,000
120,000
Exit SELF REFRESH ACTIVE command
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FUNCTIONAL CHARACTERISTICS
Notes: notes appear following parameter tables. PARAMETER READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVE command Data-in PRECHARGE command Last data-in burst STOP command Last data-in READ/WRITE command Last data-in PRECHARGE command LOAD MODE REGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command CL=3
SYMBOL
-13E
-133
-10E
UNITS
NOTES
CKED
ROH(3) ROH(2)
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NOTES
Module timing parameters comply with PC100 PC133 Design Specs, based component parameters. voltages referenced VSS. This parameter sampled. VDD, VDDQ +3.3V; MHz; 25°C; under test biased 1.4V. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range ensured (Commercial temperature: +70°C Industrial Temperature: -40°C +85°C). initial pause 100µs required after powerup, followed AUTO REFRESH commands, before proper device operation ensured. (VDD VDDQ must powered simultaneously. VSSQ must same potential.) AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load: Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate. Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate. Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will increase decrease proportionally according amount frequency alteration test condition. Address transitions average transition every clocks. must toggled minimum times during this period. Based 10ns -10E, 7.5ns -133 -13E. overshoot: (MAX) VDDQ pulse width 3ns, pulse width cannot greater than third cycle rate. undershoot: (MIN) pulse width 3ns. clock frequency must remain constant (stable clock defined signal cycling within timing constraints specified clock pin) during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. precharge timing budget (tRP) begins -13E; 7.5ns -133 -10E after first clock delay, after last WRITE executed. exceed limit precharge mode. Precharge mode only. JEDEC PC100 specify three clocks. -133/-13E with load 4.6ns guaranteed design. Parameter guaranteed design. value tRAS used -13E speed grade module SPDs calculated from 45ns. -10E, 10ns; -133, 7.5ns; -13E, 7.5ns. HIGH during refresh command period (MIN) else LOW. IDD6 limit actually nominal value does result fail value. Leakage number reflects worst case leakage possible through module pin, what each memory device contributes.
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50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have with timing referenced 1.5V crossover point. input transition time longer than 1ns, then timing referenced (MAX) (MIN) longer 1.5V crossover point. Other input signals allowed transition more than once every clocks otherwise valid levels. specifications tested after device properly initialized.
16Meg SDRAM SODIMMs SD4C4_8_16X64HG_B.fm 8/02
32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
CLOCK DATA CONVENTIONS
Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions (Figures
ACKNOWLEDGE
Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data (Figure device will always respond with acknowledge after recognition start condition slave address. both device WRITE operation have been selected, device will respond with acknowledge after receipt each subsequent eight-bit word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
START CONDITION
commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met.
STOP CONDITION
communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode.
Figure Data Validity
Figure Definition Start Stop
DATA STABLE DATA CHANGE DATA STABLE
START
STOP
Figure Acknowledge Response From Receiver
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
16Meg SDRAM SODIMMs SD4C4_8_16X64HG_B.fm 8/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
EEPROM DEVICE SELECT CODE
Note: most significant (b7) sent first. DEVICE TYPE IDENTIFIER Memory Area Select Code (two arrays) Protection Register Select Code CHIP ENABLE
EEPROM OPERATING MODES
MODE Current Address Read Random Address Read Sequential Read Byte Write Page Write BYTES INITIAL SEQUENCE START, Device Select, START, Device Select, Address reSTART, Device Select, Similar Current Random Address Read START, Device Select, START, Device Select,
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
Notes: notes appear following EEPROM operating conditions tables. PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs 3.3V ±10% POWER SUPPLY CURRENT: clock frequency SYMBOL UNITS
16Meg SDRAM SODIMMs SD4C4_8_16X64HG_B.fm 8/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
EEPROM TIMING DIAGRAM
HIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
UNDEFINED
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
Notes: notes appear following EEPROM operating conditions tables. PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time
NOTE: +3.3V ±0.3V voltages referenced VSS. EEPROM WRITE cycle time (tWRC) time from valid stop condition write sequence EEPROM internal erase/program cycle. During WRITE cycle, EEPROM interface circuit disabled, remains HIGH pullup resistor, EEPROM does respond slave address.
SYMBOL
UNITS
NOTES
HD:DAT HD:STA
HIGH
SU:DAT SU:STA
SU:STO
16Meg SDRAM SODIMMs SD4C4_8_16X64HG_B.fm 8/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
SERIAL PRESENCE-DETECT MATRIX
Notes: notes appear Serial Presence-Detect Matrix BYTE DESCRIPTION NUMBER BYTES USED MICRON TOTAL NUMBER MEMORY BYTES MEMORY TYPE NUMBER ROWADDRESSES NUMBER COLUMN ADDRESSES NUMBER MODULE BANKS MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS SDRAM CYCLE TIME, (CAS LATENCY SDRAM ACCESS FROM CLK, (CAS LATENCY MODULE CONFIGURATION TYPE REFRESH RATE/TYPE ENTRY (VERSION) SDRAM LVTTL (-13E) 7.5ns (-133) (-10E) 5.4ns (-13E/-133) (-10E) NONE 15.6µs 7.81µs/SELF MT4LSDT464(L)H(I) MT4LSDT864(L)H(I) MT4LSDT1664(L)H(I) 15ns (-13E) 20ns (-133/-10E) 14ns (-13E) 15ns (-133) 20ns (-10E) 15ns (-13E)20ns (-133/-10E) 45ns (-13E) 44ns (133) 50ns (-10E)
SDRAM WIDTH (PRIMARY SDRAM) ERROR-CHECKING SDRAM DATA WIDTH MINIMUM CLOCK DELAY FROM BACK-TOBACK RANDOM COLUMN ADDRESSES,tCCD PAGE BURST LENGTHS SUPPORTED NUMBER BANKS SDRAM DEVICE LATENCIES SUPPORTED LATENCY LATENCY UNBUFFERED SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES: GENERAL 7.5ns (13E) SDRAM CYCLE TIME 10ns (-133/-10E) (CAS LATENCY SDRAM ACCESS FROM CLK, (CAS LATENCY SDRAM CYCLE TIME, (CAS LATENCY SDRAM ACCESS FROM CLK, (CAS LATENCY MINIMUM PRECHARGE TIME, MINIMUM ACTIVE ACTIVE, tRRD MINIMUM RAS# CAS# DELAY, tRCD MINIMUM RAS# PULSE WIDTH, tRAS (Note 54ns (-13E) (-133/-10E)
16Meg SDRAM SODIMMs SD4C4_8_16X64HG_B.fm 8/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
SERIAL PRESENCE-DETECT MATRIX (CONTINUED)
Notes: notes appear Serial Presence-Detect Matrix BYTE DESCRIPTION 36-61 MODULE BANK DENSITY ENTRY (VERSION) MT4LSDT464(L)H(I) MT4LSDT864(L)H(I) MT4LSDT1664(L)H(I) Variable Data 01-09 Variable Data Variable Data Variable Data Variable Data Variable Data Variable Data Variable Data Variable Data Variable Data Variable Data 01-09 Variable Data Variable Data Variable Data Variable Data
32MB, 64MB, 128MB COMMAND ADDRESS SETUP TIME, 1.5ns (-13E/-133) (-10E) tCMS COMMAND ADDRESS HOLD TIME, 0.8ns (-13E/-133) (-10E) tCMH 1.5ns (-13E/-133) DATA SIGNAL INPUT SETUP TIME, (-10E) 0.8ns (-13E/-133) DATA SIGNAL INPUT HOLD TIME, (-10E) RESERVED REV. REVISION (-13E) CHECKSUM BYTES 0-62 (-133) (-10E) MICRON MANUFACTURER'S JEDEC CODE MANUFACTURER'S JEDEC CODE (CONT.) MANUFACTURING LOCATION MODULE PART NUMBER (ASCII) IDENTIFICATION CODE IDENTIFICATION CODE (CONT.) YEAR MANUFACTURE WEEK MANUFACTURE MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) SYSTEM FREQUENCY (-13E/-133/-10E) SDRAM COMPONENT CLOCK DETAIL
65-71 73-90 95-98 99-125
NOTE:
+3.3V ±0.3V. "1"/"0": Serial Data, "driven HIGH"/"driven LOW." value tRAS used -13E modules calculated from tRP. Actual device spec. value 37ns.
16Meg SDRAM SODIMMs SD4C4_8_16X64HG_B.fm 8/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
32MB 64MB 128MB (x64) 144-PIN SDRAM SODIMMs
144-PIN SODIMM
FRONT VIEW
2.666 (67.72) 2.656 (67.45) .079 (2.00) (2X)
.150 (3.80)
.071 (1.80) (2X)
1.005 (25.53) 0.995 (25.27) .787 (20.00)
.236 (6.00) .100 (2.55)
.157 (4.00)
.079 (2.00) .83.82 (3.30)
.043 (1.10) .035 (0.90)
.059 (1.50) .024 (.60)
.0315 (.80)
2.504 (63.60)
BACK VIEW
2.386 (60.60)
NOTE: dimensions inches (millimeters)
typical where noted.
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16Meg SDRAM SODIMMs SD4C4_8_16X64HG_B.fm 8/02
©2002, Micron Technology Inc.

SMALL-OUTLINE SDRAM MODULE JEDEC-standard PC100 PC133 compliant 1

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