SYNCHRONOUS DRAM MODULE PC100- PC133-compliant JEDEC-standard, 16
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
SYNCHRONOUS DRAM MODULE
PC100- PC133-compliant JEDEC-standard, 168-pin, dual inline memory module (DIMM) Unbuffered 32MB 64), 64MB 64), 128MB Single +3.3V ±0.3V power supply Fully synchronous; signals registered positive edge system clock Internal pipelined operation; column address changed every clock cycle Internal SDRAM banks hiding access/precharge Programmable burst lengths: full page Auto Precharge, includes CONCURRENT AUTO PRECHARGE Auto Refresh Modes Self Refresh Mode 32MB 64MB: 64ms, 4,096-cycle refresh; 128MB: 64ms, 8,192-cycle refresh LVTTL-compatible inputs outputs Serial Presence-Detect (SPD)
latest data sheet, please refer site: www.micron.com/moduleds
MT4LSDT464A 32MB MT4LSDT864A(I) 64MB MT4LSDT1664A(I) 128MB
Figure 168-Pin DIMM MO-161
Table
MODULE MARKING -13E -133 -10E
Timing Parameters
PC100 tRCD tRP) 2-2-2 2-2-2 2-2-2 PC133 tRCD tRP) 2-2-2 3-3-3
OPTIONS
Package 168-pin DIMM (gold) Operating Temperature Range Commercial (0°C +70°C) Industrial (-40°C +85°C)1 Frequency Latency 7.5ns (133 MHz) 7.5ns (133 MHz) (100 MHz)
NOTE:
MARKING
None -13E -133 -10E
Table
PARTNUMBER
Part Numbers
CONFIGURATION SYSTEM SPEED
Consult Micron availability; Industrial Temperature option available -133 speed only.
MT4LSDT464AG-13E_ MT4LSDT464AG-133_ MT4LSDT464AG-10E_ MT4LSDT864AG-13E_ MT4LSDT864A(I)G-133_ MT4LSDT864AG-10E_ MT4LSDT1664AG-13E_ MT4LSDT1664A(I)G-133_ MT4LSDT1664AG-10E_
NOTE:
Table
Address Table
32MB MODULE 64MB MODULE (BA0, BA1) (A0-A11) (A0-A8) (S0, 128MB MODULE (BA0, BA1) (A0-A12) (A0-A8) (S0,
designators component revision last characters each part number. Consult factory current revision codes. Example: MT4LSDT1664AG-133B1.
Refresh Count (BA0, BA1) Device Banks Device Conf. Addressing (A0-A11) (A0-A7) Column Addr. (S0, Module Banks
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Table Assignment (168-Pin DIMM Front)
SYMBOL DQM0 DQM1 SYMBOL DQM2 DQM3 DQ16 DQ17 DQ18 DQ19 DQ20 CKE1 SYMBOL DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Table
Assignment (168-Pin DIMM Back)
CAS# DQM4 DQM5 RAS# NC/A12* CKE0 DQM6 DQM7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SYMBOL
NOTE:
SYMBOL SYMBOL SYMBOL SYMBOL DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
32MB 64MB modules, 128MB module.
Figure Locations (168-Pin DIMM)
Front View
Back View Components This Side Module
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Table Descriptions
SYMBOL RAS#, CAS#, WE#, CK0, TYPE Input Input DESCRIPTION Command Inputs: RAS#, CAS#, (along with define command being entered. Clock: driven system clock. SDRAM input signals sampled positive edge also increments internal burst counter controls output registers. Clock Enable: activates (HIGH) deactivates (LOW) signal. Deactivating clock provides PRECHARGE POWER-DOWN SELF REFRESH operation (all device banks idle) CLOCK SUSPEND OPERATION (burst access progress). synchronous except after device enters power-down self refresh modes, where becomes asynchronous until after exiting same mode. input buffers, including disabled during power-down self refresh modes, providing standby power. Chip Select: enables (registered LOW) disables (registered HIGH) command decoder. commands masked when registered HIGH. considered part command code. Input/Output Mask: DQMB input mask signal write accesses output enable signal read accesses. Input data masked when DQMB sampled HIGH during WRITE cycle. output buffers placed High-Z state (twoclock latency) when DQMB sampled HIGH during READ cycle. Bank Address: define which device bank ACTIVE, READ, WRITE, PRECHARGE command being applied. Address Inputs: Provide address ACTIVE commands, column address auto prcharge (A10) READ/WRITE commands, select location memory arrary respective device bank. sampled during PRECHARGE command determines whether PRECHARGE applies device bank (A10 LOW, device bank selected BA0, BA1) device banks (A10 HIGH). address inputs also provide op-code during MODE REGISTER command. Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module Presence-Detect Address Inputs: These pins used configure presence-detect device. Serial Presence-Detect Data: bidirectional used transfer addresses data into presencedetect portion module. Data I/Os: Data bus. Pins listed module pinout order necessarily correlate with symbols. NUMBERS 111,
CKE0
Input
S0#,
Input
112, 113, 130,
DQMB0DQMB7
Input
BA0,
Input
33-38, 117-121, 123, (128MB)*
A0-A11 (32MB/64MB) A0-A12 (128MB)
Input
165-167
SA0-SA2
Input Input Input/Output
2-5, 7-11, 13-17, 19-20, 55-58, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156, 158-161
DQ0-DQ63
Input/Output
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Table Descriptions
SYMBOL
Pins listed module pinout order necessarily correlate with symbols. NUMBERS 102, 110, 124, 133, 143, 157, 107, 116, 127, 138, 148, 152, 105, 106, 114, 125, 129, 132, 108, 109, (32MB/64MB), 134, 135, 145-147, TYPE Supply DESCRIPTION Power Supply: +3.3V ±0.3V.
Supply
Ground.
Use: These pins used these modules, assigned pins other modules this product family. Connected: These pins connected these modules.
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Figure Functional Block Diagram
DQM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM0 DQM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM2 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 RAS# CAS# CKE0 A0-A11(32MB/64MB) A0-A12(128MB) BA0-1 DQML DQMH RAS#: SDRAMs CAS#: SDRAMs CKE: SDRAMs WE#: SDRAMs A0-A11: SDRAMs A0-A12: SDRAMs BA0-1: SDRAMs SDRAMs SDRAMs
U1-U5 MT48LC4M16A2TG SDRAMs 32MB Comm. Temp. U1-U5 MT48LC8M16A2TG SDRAMs 64MB Comm. Temp. U1-U5 MT48LC16M16A2TG SDRAMs 128MB Comm. Temp. U1-U5 MT48LC8M16A2TG-75 SDRAMs 64MB Ind. Temp. U1-U5 MT48LC16M16A2TG-75 SDRAMs 128MB Ind. Temp.
DQM5 DQML DQMH DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM1 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQML DQMH
DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQM3 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQML DQMH
11.2pF
13.6pF
CK1,
10pF
Note: resistor values unless otherwise specified. industry standard, Micron modules various component speed grades referenced module part numbering guide www.micron.com/numberguide.
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
General Description
Micron MT4LSDT464A, MT4LSDT864A(I), MT4LSDT1664A(I) high-speed CMOS, dynamic random access, 32MB, 64MB, 128MB memory modules organized configuration. These modules SDRAM devices which internally configured quad-bank DRAMs with synchronous interface (all signals registered positive edge clock signals CK0, CK2). four banks configured devices used these modules configured 4,096 bit-rows bit-columns, input/output bits 32MB module; 4,096 bit-rows bit-columns input/output bits 64MB; module 8,192 bit-rows bit-columns input/output bits 128MB module. Read write accesses SDRAM module burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed (BA0, select device bank, A0-A11 32MB/64MB; A0-A12 128MB select device row). address bits registered coincident with READ WRITE command(A0-A7 32MB; A0-A8 64MB/ 128MB) used select starting device column location burst access. These modules provide programmable READ WRITE burst lengths locations, full page, with burst terminate option. auto precharge function enabled provide self-timed precharge that initiated burst sequence. These modules internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows column address changed every clock cycle achieve highspeed, fully random access. Precharging device bank while accessing other three device banks will hide PRECHARGE cycles provide seamless, high-speed, random access operation. These modules designed operate 3.3V, lowpower memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs, outputs, clocks LVTTL-compatible. SDRAM modules offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with automatic column-address generation, ability interleave between internal banks order hide precharge time, capability randomly change
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
column addresses each clock cycle during burst access. more information regarding SDRAM operation, refer 64Mb, 128Mb, 256Mb SDRAM component data sheets.
Serial Presence-Detect Operation
These modules incorporate serial presence-detect (SPD). function implemented using 2,048-bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters. remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. Once power applied VDDQ (simultaneously) clock stable (stable clock defined signal cycling within timing constraints specified clock pin), SDRAM requires 100µs delay prior issuing command other than COMMAND INHIBIT Starting some point during this 100µs period continuing least through this period, COMMAND INHIBIT commands should applied. Once 100µs delay been satisfied with least COMMAND INHIBIT command having been applied, PRECHARGE command should applied. device banks must then precharged, thereby placing device banks idle state. Once idle state, AUTO REFRESH cycles must performed. After AUTO REFRESH cycles complete, SDRAM ready mode register programming. Because mode register will power unknown state, should loaded prior applying operational command.
Mode Register Definition
mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode, write burst mode, shown Figure Mode Register Definition Diagram, page mode register programmed
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
LOAD MODE REGISTER command will retain stored information until programmed again device loses power. Mode register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), M4-M6 specify latency, specify operating mode, specifies write burst mode, reserved future use. 128MB module, address (M12) undefined should driven during loading mode register. mode register must loaded when device banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation. ordering accesses within burst determined burst length, burst type starting column address, shown Table Burst Definition Table, page
Figure Mode Register Definition Diagram
32MB 64MB Modules
Address
Mode Register (Mx)
Reserved* *Should program ensure compatibility with future devices.
Mode
Latency
Burst Length
128MB Module
Address
Burst Length
Read write accesses SDRAM burst oriented, with burst length being programmable, shown Mode Register Definition Diagram. burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. full-page burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached, shown Burst Definition Table. block uniquely selected (32MB) A1-A8 (64MB/128MB) when burst length two; A2-A7 A2-A8 when burst length four; A3-A7 A3-A8 when burst length eight. remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached, shown Table Burst Definition Table, page
Mode Register (Mx) Reserved* Mode Latency Burst Length
*Should program M12, M11, ensure compatibility with future devices.
Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved Reserved
M6-M0 Defined
Operating Mode Standard Operation other states reserved
Write Burst Mode Programmed Burst Length Single Location Access
Burst Type
Accesses within given burst programmed either sequential interleaved; this referred burst type selected
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Table Burst Definition Table
STARTING COLUMN ADDRESS ORDER ACCESSES WTHIN BURST TYPE SEQUENTIAL 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 TYPE INTERLEAVED 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 supported
BURST LENGTH
Full A0-Ai* Page (location 0-y)
READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, READ command registered latency programmed clocks, will start driving after data will valid shown Latency Diagram. Latency Table indicates operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result.
Figure Latency Diagram
COMMAND
READ
DOUT
Latency
32MB module 64MB 128MB modules
NOTE: full-page accesses: (32MB); (64MB/ 128MB). burst length two, A1-Ai select block-of-two burst; selects starting column within block. burst length four, A2-Ai select block-of-four burst; A0-A1 select starting column within block. burst length eight, A3-Ai select block-of-eight burst; A0-A2 select starting column within block. full-page burst, full selected A0-Ai select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-Ai select unique column accessed, mode register ignored.
COMMAND
READ
DOUT
Latency
DON'T CARE UNDEFINED
Latency latency delay, clock cycles, between registration READ command availability first piece output data. latency three clocks.
Operating Mode normal operating mode selected setting zero; other combinations values reserved future and/or test modes. programmed burst length applies both READ WRITE bursts. Test modes reserved states should used because unknown operation incompatibility with future versions result.
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Write Burst Mode When burst length programmed applies both READ WRITE bursts; when programmed burst length applies READ bursts, write accesses single-location (nonburst) accesses.
Table
Latency Table
ALLOWABLE OPERATING CLOCK FREQUENCY (MHz)
SPEED -13E -133 -10E
LATENCY
LATENCY
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Commands
This Truth Table provides general reference available commands. more detailed description commands operations, refer 64Mb, 128Mb, 256Mb SDRAM component data sheet.
Table
Note:
Truth Table Commands DQMB Operation
RAS# CAS# DQMB L/H8 L/H8 ADDR Bank/Row Bank/Col Bank/Col Code Op-Code Valid Active Active High-Z NOTES
NAME (FUNCTION) COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output enable Write Inhibit/Output High-Z
NOTE:
HIGH commands shown except SELF REFRESH. A0-A11 define op-code written mode register, 128MB module, should driven LOW. A0-A11 (32MB/64MB) A0-A12 (128MB) provide device address, BA0, determine which device bank made active. A0-A7 (32MB) A0-A8 (64MB/128MB) provide device column address; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge feature; BA0, determine which device bank being read from written LOW: BA0, determine device bank being precharged. HIGH: device banks precharged BA0, "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls device addressing; inputs I/Os "Don't Care" except CKE. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Absolute Maximum Ratings
Stresses greater than those listed cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operaVoltage VDD, VDDQ Supply Relative +4.6V Voltage Inputs, Pins Relative +4.6V Operating Temperature (Commercial) .0°C +70°C (Industrial). .-40°C +85°C tional sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Storage Temperature (plastic) -55°C +150°C Power Dissipation
Table Electrical Characteristics Operating Conditions
Notes: notes appear following parameter tables; VDD, VDDQ +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs Command/ INPUT LEAKAGE CURRENT: input Address, CKE0 (All other pins under CK0, test OUTPUT LEAKAGE CURRENT: disabled; VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA) SYMBOL VDD, VDDQ -0.3 UNITS NOTES
Table Specifications Conditions 32MB Module
Notes: notes appear following parameter tables; VDD, VDDQ +3.3V ±0.3V; DRAM components only PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT tRFC (MIN) HIGH; HIGH 15.62µs SELF REFRESH CURRENT: 0.2V SYMBOL IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 -13E -133 -10E UNITS NOTES
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Table Specifications Conditions 64MB Module
Notes: notes appear following parameter tables; VDD, VDDQ +3.3V ±0.3V; DRAM components only PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT tRFC (MIN) HIGH; HIGH 15.62µs SELF REFRESH CURRENT: 0.2V SYMBOL IDD1 IDD2 IDD3 -13E -133 -10E UNITS NOTES
IDD4 IDD5 IDD6 IDD7
1,320 1,240 1,080
Table Specifications Conditions 128MB Module
Notes: notes appear following parameter tables; VDD, VDDQ +3.3V ±0.3V; DRAM components only PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT tRFC (MIN) HIGH; HIGH 7.81µs SELF REFRESH CURRENT: 0.2V SYMBOL IDD1 IDD2 IDD3 -13E -133 -10E UNITS NOTES
IDD4 IDD5 IDD6 IDD7
1,140 1,080 1,080
Table Capacitance
Notes notes appear following parameter table PARAMETER Input Capacitance: A0-A12, BA0, BA1, RAS, CAS, CKE0 Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitnace: DQMB0-DQMB7 Inuput/Output Capacitnance: DQ0-DQ63 SYMBOL CI3a CI3b 16.2 18.6 15.2 18.2 20.6 UNITS
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Table Electrical Characteristics Recommended Operating Conditions
Notes: notes appear following parameter tables; VDD, VDDQ +3.3V ±0.3V CHARACTERISTICS PARAMETER Access time from (positive edge) Address hold time Address setup time high-level width low-level width Clock cycle time hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time load) ACTIVE PRECHARGE command ACTIVE ACTIVE command period ACTIVE READ WRITE delay Refresh period (8,192 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank ACTIVE bank command Transition time WRITE recovery time
-13E SYMBOL
-133 120,000 7.5ns
-10E UNITS NOTES 120,000
AC(3) AC(2)
CK(3) CK(2)
HZ(3) HZ(2)
120,000
Exit SELF REFRESH ACTIVE command
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Table Functional Characteristics
Notes: notes appear following parameter tables. PARAMETER READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVE command Data-in PRECHARGE command Last data-in burst STOP command Last data-in READ/WRITE command Last data-in PRECHARGE command LOAD MODE REGISTER command ACTIVEor REFRESH command Data-out high-impedance from PRECHARGE command
SYMBOL
-13E
-133
-10E
UNITS NOTES
CKED
ROH(3) ROH(2)
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Notes
voltages referenced VSS. This parameter sampled. VDD, VDDQ +3.3V; MHz; 25°C; under test biased 1.4V. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range ensured (0°C +70°C Commercial, -40°C +85°C Industrial). initial pause 100µs required after powerup, followed AUTO REFRESH commands, before proper device operation ensured. (VDD VDDQ must powered simultaneously. VSSQ must same potential.) AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load:
50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have with timing referenced 1.5V crossover point. input transition time longer than 1ns, then timing referenced (MAX) (MIN) longer crossover point. Other input signals allowed transition more than once every clocks otherwise valid levels. specifications tested after device properly initialized. Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate.
Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate. Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will increase decrease proportionally according amount frequency alteration test condition. Address transitions average transition every clocks. must toggled minimum times during this period. Based 10ns -10E; 7.5ns -133 -13E. overshoot: (MAX) VDDQ pulse width 3ns, pulse width cannot greater than one-third cycle rate. undershoot: (MIN) pulse width 3ns. clock frequency must remain constant (stable clock defined signal cycling within timing constraints specified clock pin) during access precharge states (READ, WRITE, including PRECHARGE commands). used reduce data rate. Auto precharge mode only. precharge timing budget (tRP) begins -13E; 7.5ns -133; -10E after first clock delay, after last WRITE executed. exceed limit precharge mode. Precharge mode only. JEDEC PC100 specify three clocks. ttAC -133/-13E with load 4.6ns guaranteed design. Parameter guaranteed design. -13E, 7.5ns; -133, 7.5ns; -10E, 10ns. HIGH during refresh command period (MIN,) else LOW. IDD6 limit actually nominal value does result fail value. Refer device data sheet timing waveforms. value tRAS used -13E speed grade mod. ules calculated from Leakage number reflects worst-case leakage possible through module pin, what each memory device contributes.
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
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32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Clock Data Conventions
Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions, indicated Figures Figure Data Validity ,and Figure Definition Start Stop.
Acknowledge
Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data indicated Figure Figure Acknowledge Response from Receiver. device will always respond with acknowledge after recognition start condition slave address. both device WRITE operation have been selected, device will respond with acknowledge after receipt each subsequent eight-bit word. read mode, device will transmit eight bits data, release line, monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
Start Condition
commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met.
Stop Condition
communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode.
Figure Data Validity
Figure Definition Start Stop
DATA STABLE DATA CHANGE DATA STABLE
START
STOP
Figure Acknowledge Response from Receiver
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Table EEPROM Device Select Code
most significant (b7) sent first DEVICE TYPE IDENTIFIER Memory Area Select Code (two arrays) Protection Register Select Code CHIP ENABLE
Table EEPROM Operating Modes
MODE Current Address Read Random Address Read Sequential Read Byte Write Page Write BYTES INITIAL SEQUENCE START, Device Select, START, Device Select, `0', Address reSTART, Device Select, Similar Current Random Address Read START, Device Select, START, Device Select,
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUTL INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs 3.3V ±10% POWER SUPPLY CURRENT: clock frequency SYMBOL UNITS
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Figure EEPROM Timing Diagram
HIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
UNDEFINED
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; +3.3V ±0.3V PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time
NOTE: Timing actually specified tWR.
SYMBOL
UNITS
NOTES
HD:DAT HD:STA
HIGH
SU:DAT SU:STA
SU:STO
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Table Serial Presence-Detect Matrix
"1"/"0": Serial Data, "driven HIGH"/"driven LOW." BYTE DESCRIPTION NUMBER BYTES USED MICRON TOTAL NUMBER MEMORY BYTES MEMORY TYPE NUMBER ADDRESSES NUMBER COLUMN ADDRESSES NUMBER BANKS MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS SDRAM CYCLE TIME, (CAS LATENCY SDRAM ACCESS FROM CLOCK, (CAS LATENCY MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM WIDTH (PRIMARY SDRAM) ERROR-CHECKING SDRAM DATA WIDTH MINIMUM CLOCK DELAY, tCCD BURST LENGTHS SUPPORTED NUMBER INTERNAL BANKS SDRAM DEVICE LATENCIES SUPPORTED LATENCY LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME, (CAS LATENCY SDRAM ACCESS FROM (CAS LATENCY SDRAM CYCLE TIME, (CAS LATENCY SDRAM ACCESS FROM (CAS LATENCY MINIMUM PRECHARGE TIME, MINIMUM ACTIVE ACTIVE, MINIMUM RAS# CAS# DELAY, tRCD MINIMUM RAS# PULSE WIDTH, tRAS (Note MODULE BANK DENSITY ENTRY (VERSION) SDRAM LVTTL (-13E) 7.5ns (-133) (-10E) 5.4ns (-13E/-133) (-10E) None (80) 15.6µs/SELF (82) 7.81µs/SELF None PAGE UNBUFFERED 7.5ns (-13E) 10ns (-133/-10E) 5.4ns (-13E) (-133/-10E) 15ns (-13E) 20ns (-133/-10E) 14ns (-13E) 15ns (-133) 20ns (-10E) 15ns (-13E) 20ns (-133/-10E) 45ns (-13E) 44ns (-133) 50ns (-10E) 32MB, 64MB, 128MB MT4LSDT464A MT4LSDT864A(I) MT4LSDT1664A(I)
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Table Serial Presence-Detect Matrix
"1"/"0": Serial Data, "driven HIGH"/"driven LOW." BYTE 36-61 DESCRIPTION COMMAND ADDRESS SETUP TIME COMMAND ADDRESS HOLD TIME DATA SIGNAL INPUT SETUP TIME DATA SIGNAL INPUT HOLD TIME RESERVED REVISION CHECKSUM BYTES 0-62 ENTRY (VERSION) 1.5ns (-13E/-133) (-10E) 0.8ns (-13E/-133) (-10E) 1.5ns (-13E/-133) (-10E) 0.8ns (-13E/-133) (-10E) -13E -133 -10E MICRON 1-11 MT4LSDT464A MT4LSDT864A(I) MT4LSDT1664A(I) 01-0B Variable Data 01-09 Variable Data Variable Data Variable Data Variable Data 01-0B Variable Data 01-09 Variable Data Variable Data Variable Data Variable Data 01-0B Variable Data 01-09 Variable Data Variable Data Variable Data Variable Data
65-71 73-90 95-98 99-125
NOTE:
MANUFACTURER'S JEDEC CODE MANUFACTURER'S JEDEC CODE (cont'd.) MANUFACTURING LOCATION MODULE PART NUMBER (ASCII) IDENTIFICATION CODE IDENTIFICATION CODE (continued) YEAR MANUFACTURE WEEK MANUFACTURE MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) SYSTEM FREQUENCY SDRAM COMPONENT CLOCK DETAIL
100/133
value tRAS used -13E part calculated from tRP. Actual device specification value 37ns.
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology Inc.
32MB 64MB 128MB (x64) 168-PIN SDRAM DIMMs
Figure 168-Pin DIMM
FRONT VIEW
5.256 (133.50) 5.244 (133.20) .125 (3.18)
.079 (2.00) (2X) .118 (3.00) (2X) .118 (3.00) .250 (6.35) .118 (3.00) 1.661 (42.18) 2.625 (66.68) .039 (1.00)R (2X) .039 (1.00) .050 (1.27) .128 (3.25) (2X) .118 (3.00) .054 (1.37) .046 (1.17) 1.005 (25.53) .700 (17.78) 0.995 (25.27)
(PIN BACKSIDE)
4.550 (115.57)
(PIN BACKSIDE)
NOTE: dimensions inches (millimeters)
typical where noted.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron logo registered trademarks Micron logo trademark Micron Technology, Inc.
128MB SDRAM DIMM SD4C4_8_16X64AG_B.fm Rev. 12/02
©2002, Micron Technology Inc.
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