SYNCHRONOUS DRAM MODULE JEDEC-standard, 168-pin, dual in-line mem
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1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
SYNCHRONOUS DRAM MODULE
JEDEC-standard, 168-pin, dual in-line memory module (DIMM) PC100 PC133 compliant Stacked TSOP SDRAM components Registered inputs with one-clock delay Phase-lock loop (PLL) clock driver reduce loading Utilizes SDRAM components ECC-optimized pinout Single +3.3V ±0.3V power supply Fully synchronous; signals registered positive edge clock Internal pipelined operation; column address changed every clock cycle Internal SDRAM banks hiding access/ precharge Programmable burst lengths: full page Auto Precharge Auto Refresh Modes Self Refresh Mode: 64ms, 8,192 cycle refresh LVTTL-compatible inputs outputs Serial presence-detect (SPD) Gold edge contacts
OPTIONS MARKING
MT36LSDT12872 MT36LSDT25672
latest data sheet, please refer site: www.micron.com/datasheets
Figure 168-Pin DIMM (MO-161)
Standard
1.70in. (43.18mm)
Low-Profile
1.20in. (30.48mm)
Table
Device Timing
PC100 tRCD 2-2-2 2-2-2 2-2-2 PC133 tRCD 2-2-2 3-3-3
MODULE MARKINGS -13E -133 -10E
Package 168-pin DIMM (Standard) 168-pin DIMM (Lead-free) Standard Low-Profile Frequency/CAS Latency1 MHz/CL MHz/CL MHz/CL
NOTE:
note page -13E -133 -10E
Table
Address Table
(READ) Latency. Registered mode adds clock cycle
Refresh Count (BA0, BA1) (BA0, BA1) Device Banks Device Configuration (A0-A12) (A0-A12) Addressing Column Addressing (A0-A9, A11) (A0-A9, A11, A12) (S0, (S0, Module Ranks
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
©2003 Micron Technology, Inc.
PRODUCTS SPECIFICATIONS DISCUSSED HEREIN SUBJECT CHANGE MICRON WITHOUT NOTICE.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Part Numbers
MODULE DENSITY CONFIGURATION SYSTEM SPEED
PART NUMBER MT36LSDT12872G-13E_ MT36LSDT12872Y-13E_ MT36LSDT12872G-133_ MT36LSDT12872Y-133_ MT36LSDT12872G-10E_ MT36LSDT12872Y-10E_ MT36LSDT25672G-13E_ MT36LSDT25672Y-13E_ MT36LSDT25672G-133_ MT36LSDT25672Y-133_ MT36LSDT25672G-10E_ MT36LSDT25672Y-10E_
NOTE:
designators component revision last characters each part number. Consult factory current revision codes. Example: MT36LSDT12872G-133B1.
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Assignment (168-Pin DIMM Front)
DQMB0 DQMB1 DQMB2 DQMB3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Table
Assignment (168-Pin DIMM Back)
CKE0 DQMB6 DQMB7 CAS# DQMB4 DQMB5 RAS# DQ48 DQ49 DQ50 DQ51 DQ52 REGE DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SYMBOL SYMBOL SYMBOL SYMBOL DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
SYMBOL SYMBOL SYMBOL SYMBOL DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
Figure 168-Pin DIMM Assignment
Standard
Front View Front View
Profile
Back View Back View
PIN125
PIN125
Indicates VDDQ
Indicates
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Descriptions
SYMBOL RAS#, CAS#, CK0-CK3 CKE0 TYPE Input Input Input DESCRIPTION Command Inputs: RAS#, CAS#, (along with define command being entered. Clock: distributed through on-board devices. CK1-CK3 terminated. Clock Enable: activates (HIGH) deactivates (LOW) signal. Deactivating clock provides POWERDOWN SELF REFRESH operation (all device banks idle) CLOCK SUSPEND operation (burst access progress). synchronous except after device enters power-down self refresh modes, where becomes asynchronous until after exiting same mode. input buffers, including disabled during power-down self refresh modes, providing standby power. Chip Select: enable (registered LOW) disable (registered HIGH) command decoder. commands masked when registered HIGH. considered part command code. Input/Output Mask: DQMB input mask signal write accesses output enable signal read accesses. Input data masked when DQMB sampled HIGH during WRITE cycle. output buffers placed High-Z state (twoclock latency) when DQMB sampled HIGH during READ cycle. Bank Address: define which device bank ACTIVE, READ, WRITE, PRECHARGE command being applied. Address Inputs: Provide address ACTIVE commands, column address auto prcharge (A10) READ/WRITE commands, select location memory arrary respective device bank. sampled during PRECHARGE command determines whether PRECHARGE applies device bank (A10 LOW, device bank selected BA0, BA1) device banks (A10 HIGH). address inputs also provide op-code during MODE REGISTER command. Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module. Presence-Detect Address Inputs: These pins used configure presence-detect device. Register Enable: REGE permits DIMM operate "buffered" mode (LOW) "registered" mode (HIGH). Data I/Os: Data bus. numbers correlate with symbol order. Refer Assignment tables page fore more information NUMBERS 111, 125,
114,
S0#-S3#
Input
112, 113, 130,
DQMB0-DQMB7
Input
BA0,
Input
33-38, 117-121, 123,
A0-A12
Input
165-167 2-5, 7-11, 13-17, 19-20, 55-58, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103-104, 139142, 144, 149-151, 153-156, 158-161 105, 106, 136,
SA0-SA2 REGE DQ0-DQ63
Input Input Input Input/ Output
CB0-CB7
Input/ Check Bits. Output Input/ Serial Presence-Detect Data: bidirectional used Output transfer addresses data into data presence-detect portion module.
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
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1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Descriptions (Continued)
SYMBOL TYPE Supply DESCRIPTION Power Supply: +3.3V ±0.3V. numbers correlate with symbol order. Refer Assignment tables page fore more information NUMBERS 102, 110, 124, 133, 143, 157, 107, 116, 127, 138, 148, 152, 61-63, 108, 109, 132, 134, 135, 145, 146,
Supply
Ground.
Connected: Listed pins connected these modules.
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Figure Functional Block Diagram
RS0# RS1# RDQMB0 RDQMB4 DQ32 DQ33 DQ34 DQ35 U23t U22t U23b U22b
RDQMB1 DQ10 DQ11
DQ36 DQ37 DQ38 DQ39 RDQMB5
DQ40 DQ41 DQ42 DQ43
U21t U20t U19t
U21b U20b
DQ12 DQ13 DQ14 DQ15
DQ44 DQ45 DQ46 DQ47
RS2# RS3# RDQMB2 DQ16 DQ17 DQ18 DQ19
U19b
RDQMB6 DQ48 DQ49 DQ50 DQ51 U18t U17t U18b U17b
DQ20 DQ21 DQ22 DQ23 RDQMB3 DQ24 DQ25 DQ26 DQ27
DQ52 DQ53 DQ54 DQ55 RDQMB7
DQ56 DQ57 DQ58 DQ59
U16t U15t
U16b U15b
DQ28 DQ29 DQ30 DQ31 U10, U11, RAS# CAS# CKE0 A0-A12 S0#, S1#, DQMB0 DQMB7 REGE
DQ60 DQ61 DQ62 DQ63
RRAS#: SDRAMs RCAS#: SDRAMs RWE#: SDRAMs RCKE: SDRAMs RA0-RA12: SDRAMs RBA0: SDRAMs RBA1: SDRAMs RS0#, RS2#: Module Rank0 RS1#, RS3#: Module Rank1
CK1-CK3
12pF
12pF
SDRAMs SDRAMs
SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM REGISTER
RDQMB0 RDQMB7: SDRAMs
NOTE:
resistor values unless otherwise specified. indicates portion stacked SDRAM. indicates bottom portion stacked SDRAM. industry standard, Micron modules utilize various component speed grades, referenced module part number guide www.micron.com/numberguide.
Modules MT48LC64M4A2TG SDRAMs Modules MT48LC128M4A2TG SDRAMs
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
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1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
General Description
MT36LSDT12872 MT36LSDT25672 high-speed CMOS, dynamic random-access, memory modules organized (ECC) configurations. SDRAM modules internally configured quad-bank SDRAM devices with synchronous interface (all signals registered positive edge clock signal CK). Read write accesses SDRAM modules burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed (BA0, select device bank; A0-A12, select device row). address bits registered coincident with READ WRITE command used select starting column location burst access. SDRAM modules provide programmable read write burst lengths locations, full page, with burst terminate option. auto precharge function enabled provide self-timed precharge that initiated burst sequence. SDRAM modules internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows column address changed every clock cycle achieve highspeed, fully random access. Precharging device bank while accessing other three device banks will hide PRECHARGE cycles provide seamless, high-speed, random-access operation. SDRAM modules designed operate 3.3V, low-power memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs outputs LVTTL-compatible. SDRAM modules offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with automatic column-address generation, ability interleave between device banks order hide precharge time, capability randomly change column addresses each clock cycle during burst access. more information regarding SDRAM operation, refer 256Mb 512Mb SDRAM component data sheets. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions device operation.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. Once power applied VDDQ (simultaneously) clock stable (stable clock defined signal cycling within timing constraints specified clock pin), SDRAM requires 100µs delay prior issuing command other than COMMAND INHIBIT Starting some point during this 100µs period continuing least through this period, Command Inhibit commands should applied. Once 100µs delay been satisfied with least Command Inhibit command having been applied, PRECHARGE command should applied. device banks must then precharged, thereby placing device device banks idle state. Once idle state, auto refresh cycles must performed. After auto refresh cycles complete, SDRAM ready mode register programming. Because mode register will power unknown state, should loaded prior applying operational command.
Register Operation
These modules operated either registered mode (REGE HIGH), where control/address input signals latched register rising clock edge sent SDRAM devices following rising clock edge (data access delayed clock), buffered mode (REGE LOW) where input signals pass through register/buffer SDRAM devices same clock. phase-lock loop (PLL) modules used redrive clock SDRAM devices minimize system clock loading. (CK0 connected PLL, CK1, CK2, terminated.)
Serial Presence-Detect Operation
These modules incorporate serial presence-detect (SPD). function implemented using 2,048-bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters.
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals, together with (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) tied ground module, permanently disabling hardware write protect block boundary reached, shown Burst Definition Table block uniquely selected (1GB), A1-A9, A11, (2GB) when burst length two; A2-A9, (1GB), A2-A9, A11, (2GB) when burst length four; A3-A9, (1GB) A3-A9, A11, (2GB) when burst length eight. remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached, shown Table Burst Definition Table, page
Mode Register Definition
mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode write burst mode, shown Figure Mode Register Definition Diagram. mode register programmed LOAD MODE REGISTER command will retain stored information until programmed again device loses power. Mode register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), M4-M6 specify latency, specify operating mode, specifies write burst mode, reserved future use. Address (M12) undefined should driven during loading mode register. mode register must loaded when device banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation.
Figure Mode Register Definition Diagram
Address
Mode Register (Mx)
Reserved*
Mode
Latency
Burst Length
*Should program M12, M11, ensure compatibility with future devices.
Burst Length Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Full Page
Burst Type Sequential Interleaved
Burst Length
Read write accesses SDRAM burst oriented, with burst length being programmable, shown Figure Mode Register Definition Diagram. burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. full-page burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within
Latency Reserved Reserved Reserved Reserved Reserved Reserved
M6-M0 Defined
Operating Mode Standard Operation other states reserved
Write Burst Mode Programmed Burst Length Single Location Access
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
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1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table
BURST LENGTH
Burst Definition Table
STARTING COLUMN ADDRESS ORDER ACCESSES WITHIN BURST TYPE SEQUENTIAL 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn+1, Cn+2, Cn+3, Cn+4., .Cn-1, TYPE INTERLEAVED 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 supported
Figure Latency Diagram
COMMAND
READ
DOUT
Latency
COMMAND
(location
READ
DOUT
Latency DON'T CARE UNDEFINED
Full Page
Table
Latency Table
ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) LATENCY LATENCY
Input register adds clock registered mode SPEED
NOTE:
full-page accesses: 2,048 (1GB); 4,096 (2GB). burst length two, will select block burst; selects starting column within block. burst length four, will select block four burst; A0-A1 select starting column within block. burst length eight, will select block eight burst; A0-A2 select starting column within block. full-page burst, full selected will select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, will select unique column accessed, Mode Register ignored. A0-A9, 1GB; A0-A9, A11, 2GB.
-13E -133 -10E
Burst Type
Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Table Burst Definition Table.
Latency
latency delay, clock cycles, between registration READ command availability first piece output data. latency three clocks.
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, read command registered latency programmed clocks, will start driving after data will valid shown Figure Latency Diagram, page Table Latency Table, page indicates operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result.
Operating Mode
normal operating mode selected setting zero; other combinations values reserved future and/or test modes. programmed burst length applies both read write bursts. Test modes reserved states should used because unknown operation incompatibility with future versions result.
Write Burst Mode
When burst length programmed M0-M2 applies both read write bursts; when programmed burst length applies read bursts, write accesses single-location (nonburst) accesses.
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Commands
Truth Table provides quick reference available commands. This followed written description each command. more detailed description commands operations refer 256Mb 512Mb SDRAM component datasheets.
Table
SDRAM Command DQMB Operation Truth Table
NAME (FUNCTION) RAS# CAS# DQMB L/H7 L/H7 ADDR Bank/Row Bank/Col Bank/Col NOTES Valid
HIGH commands shown except Self Refresh
COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z
Active Code Op-Code Active HighZ
NOTE:
A0-A12 provide device address. BA0, determine which device bank made active. A0-A9, (1GB) 0-A9, A11, A12(2GB) provide device column address; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge feature; BA0, determine which device bank being read from written LOW: BA0, determine which device bank being precharged. HIGH: both device banks precharged BA0, "Don't Care." This command Auto Refresh HIGH, Self Refresh LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. A0-A12 define op-code written Mode Register, should driven low. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Absolute Maximum Ratings
Stresses greater than those listed cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operaVoltage Supply Relative +4.6V Voltage Inputs, Pins Relative +4.6V tional sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Operating Temperature (ambient) .0°C +70°C Storage Temperature (plastic) -55°C +150°C Power Dissipation
Table Electrical Characteristics Operating Conditions
Notes: notes appear page VDDQ +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input: A0-A11, A12, (All other pins under test BA0, BA1, RAS#, CAS#, INPUT LEAKAGE CURRENT: input: DQMB, (All other pins under test INPUT LEAKAGE CURRENT: input: (All other pins under test inputs: OUTPUT LEAKAGE CURRENT: disabled; OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA) SYMBOL VDD, VDDQ -0.3 UNITS NOTES
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Specifications Conditions
SDRAM components only; Notes: notes appear page VDDQ +3.3V ±0.3V PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT tRFC (MIN)
-13E IDD1a IDD2b IDD3a IDD4a IDD5b IDD6b IDD7b 2,466 2,466 10,260
-133 2,286 2,466 9,720 -10E 2,286 2,466 9,720
UNITS NOTES
HIGH; HIGH SELF REFRESH CURRENT: 0.2V
NOTE:
7.8125µs
Value calculated module rank this operating condition, other module ranks power-down mode. Value calculated reflects module ranks this operating condition.
Table Specifications Conditions
SDRAM components only; Notes: notes appear page VDDQ +3.3V ±0.3V PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT tRFC (MIN) HIGH; HIGH SELF REFRESH CURRENT: 0.2V
NOTE:
-13E IDD1a IDD2b IDD3a IDD4a IDD5b IDD6
-133 3,636 1,476 3,276 -10E 3,636 1,476 3,276
UNITS NOTES
3,906 1,476 3,276
14,400 13,320 13,320
7.8125µs
IDD7b
Value calculated module rank this operating condition, other module ranks power-down mode. Value calculated reflects module ranks this operating condition.
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Capacitance
Note: notes appear page PARAMETER Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: Input/Output Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, CKE0 CK1-CK3 DQMB REGE SCL, SA0-SA2 SYMBOL CI1A UNITS
Table SDRAM Component Electrical Characteristics Recommended Operating Conditions
Notes: notes appear page CHARACTERISTICS PARAMETER Access time from (pos. edge) Address hold time Address setup time high-level width low-level width Clock cycle time hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setupt Data-in hold time Data-ins etup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time load) ACTIVE PRECHARGE command ACTIVE ACTIVE command period ACTIVE READ WRITE delay Refresh period AUTO REFRESH period
-13E 120,000
-133 120,000
-10E
UNITS NOTES
AC(3) AC(2)
CK(3) CK(2)
HZ(3) HZ(2)
120,000
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1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table SDRAM Component Electrical Characteristics Recommended Operating Conditions (Continued)
Notes: notes appear page CHARACTERISTICS PARAMETER PRECHARGE command period ACTIVE bank ACTIVE bank command Transition time WRITE recovery time
-13E
-133 7.5ns
-10E
UNITS NOTES
Exit SELF REFRESH ACTIVE command
Table Functional Characteristics
Notes: notes appear page PARAMETER READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVE command Data-in PRECHARGE command Last data-in burst STOP command Last data-in READ/WRITE command Last data-in PRECHARGE command LOAD MODE REGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command CL=3
SYMBOL
-13E
-133
-10E
UNITS
NOTES
CKED
ROH(3) ROH(2)
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Notes
voltages referenced VSS. This parameter sampled. VDDQ +3.3V ±0.3V; MHz, 25°C; under test biased 1.4V. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range ensured; (0°C +70°C). initial pause 100µs required after powerup, followed AUTO REFRESH commands, before proper device operation ensured. (VDD VDDQ must powered simultaneously. VSSQ must same potential.) AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load:
50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have using measurement reference level 1.5V. input transition time longer than 1ns, then timing measured from (MAX) (MIN) longer 1.5V midpoint. should always referenced crossover. Refer Micron Technical Note TN-48-09. Other input signals allowed transition more than once every clocks otherwise valid levels. specifications tested after device properly initialized. Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate.
Timing actually specified tRP; clock(s) specified reference only minimum cycle rate. Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will increase decrease proportionally according amount frequency alteration test condition. Address transitions average transition every clocks. must toggled minimum times during this period. Based 10ns -10E, 7.5ns -13E. overshoot: (MAX) VDDQ pulse width 3ns, pulse width cannot greater than third cycle rate. undershoot: (MIN) pulse width 3ns. clock frequency must remain constant (stable clock defined signal cycling within timing constraints specified clock pin) during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. precharge timing budget (tRP) begins -13E; 7.5ns -133 -10E after first clock delay, after last WRITE executed. Precharge mode only. JEDEC PC100 specify three clocks. -133/-13E with load 4.6ns guaranteed design. Parameter guaranteed design. value tRAS used -13E speed grade mod. ules calculated from -10E, 10ns; -133, 7.5ns; -13E, 7.5ns. HIGH during refresh command period (MIN) else LOW. IDD6 limit actually nominal value does result fail value. This timing function will show extra clock cycle when registered mode. Leakage number reflects worst case leakage possible through module pin, what each memory device contributes. operating frequencies MHz, tCKS 3.0ns.
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Register Timing Requirements Switching Characteristics
+3.3V ±0.3V REGISTER SYMBOL fclock tpd1 SSTL pattern JESD82-2 tpd2 PARAMETER Clock Frequency Propagation Delay, Single Rank Output) Propagation Delay, DualRank Output) Pulse Duration Setup Time Hold Time 50pF Ohms 30pF HIGH Data Before HIGH Data After HIGH CONDITION UNITS
Table Clock Driver Timing Requirements Switching Characteristics
+3.3V ±0.3V PARAMETER Operating Clock Frequency Inupt Duty Cycle Cycle Cycle Jitter Static Phase Offeset Induced Skew Output Output Skew
NOTE:
SYMBOL
-150
UNITS
NOTES
JITCC
Spread Spectrum Clock. synthesizers system motherboard will reduce EMI. Skew defined total clock skew between outputs therefore specified maximum only.
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Figure Component Case Temperature Airflow
Ambient Temperature
Tmax- memory stress software
Degrees Celsius
Tave- memory stress software
Minimum Flow
Tave- gaming software
NOTE:
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc. recommends minimum flow meter/second (~197 LFM) across MT36LSDT12872G MT36LSDT25672G modules when installed system. component case temperature measurements shown above obtained experimentally. system used experimental purposes dual-processor work station, fully loaded with four MT36LSDT12872G modules. Case temperatures charted represent worst-case component locations modules installed internal slots system. Temperature versus speed data obtained performing experiments with system motherboard removed from case mounted Eiffel-type speed wind tunnel. Peripheral devices installed system motherboard testing processor(s) video card, other peripheral devices mounted outside wind tunnel test chamber. memory diagnostic software used determining worst-case component temperatures memory diagnostic software application developed internal Micron Technology, Inc.
Flow (meters/sec)
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Clock Data Conventions
Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions shown Figure Data Validity, Figure Definition Start Stop).
Acknowledge
Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data shown Figure Acknowledge Response From Receiver). device will always respond with acknowledge after recognition start condition slave address. both device WRITE operation have been selected, device will respond with acknowledge after receipt each subsequent eight word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
Start Condition
commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met.
Stop Condition
communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode.
Figure Data Validity
Figure Definition Start Stop
DATA STABLE DATA CHANGE DATA STABLE
START
STOP
Figure Acknowledge Response From Receiver
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table EEPROM Device Select Code
most significant (b7) sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code DEVICE TYPE IDENTIFIER CHIP ENABLE
Table EEPROM Operating Modes
MODE Current Address Read RandomAddressRead Sequential Read Byte Write Page Write
BYTES
INITIAL SEQUENCE Start, Device Select, Start, Device Select, Address RESTART, Device Select, Similar Current Random Address Read START, Device Select, START, Device Select,
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs POWER SUPPLY CURRENT: clock frequency SYMBOL ICCS Write Read UNITS
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Figure EEPROM Timing Diagram
HIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
UNDEFINED
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; +3.3V ±0.3V PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time
NOTE:
SYMBOL HD:DAT HD:STA HIGH SU:DAT SU:STA SU:STO
UNITS
NOTES
aviod spurious START STOP conditions, minimum delay placed between SCL=1 falling rising edge SDA. This parameter sampled. reSTART condition, following WRITE cycle. EEPROM WRITE cycle time (tWRC) time from valid stop condition write sequence EEPROM internal erase/program cycle. During WRITE cycle, EEPROM interface circuit disabled, remains HIGH pull-up resistor, EEPROM does respond slave address.
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Serial Presence-Detect Matrix
"1"/"0": Serial data, "driven HIGH"/"driven LOW"; +3.3V ±0.3V BYTE DESCRIPTION Number Bytes Used Micron Total Number Memory Bytes Memory Type Number Addresses Number Column Addresses Number Module Ranks Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, (CAS Latency ENTRY (VERSION) SDRAM LVTTL (-13E) 7.5ns (-133) (-10E) 5.4ns (-13E/-133) (-10E) 7.81µs/SELF PAGE -13E/-133/-10E 7.5ns (-13E) 10ns (-133/-10E) 5.4ns (-13E) (-10E) 15ns (-13E) 20ns (-133/-10E) 14ns (-13E) 15ns (-133) 20ns (-10E) 15ns (-13E) 20ns (-133/-10E) 45ns (-13E) 44ns (-133) 50ns (-10E) MT36LSDT12872 MT36LSDT25672
SDRAM Access from CLK, (CAS Latency Module Configuration Type Refresh Rate/Type SDRAM Width (Primary SDRAM) Error-checking SDRAM Data Width Minimum Clock Delay from Back-to-Back Random Column Addresses,tCCD Burst Lengths Supported Number Banks SDRAM Device Latencies Supported Latency Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, (CAS Latency (-133/-10E) SDRAM Access from CLK, (CAS Latency SDRAM Cycle Time, (CAS Latency SDRAM Access from CLK, (CAS Latency Minimum Precharge Time, Minimum Active Active, tRRD
Minimum RAS# CAS# Delay, tRCD Minimum RAS# Pulse Width, tRAS (See note
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Serial Presence-Detect Matrix (Continued)
"1"/"0": Serial data, "driven HIGH"/"driven LOW"; +3.3V ±0.3V BYTE 36-61 DESCRIPTION Module Rank Density Command Address Setup Time, tAS, tCMS Command Address Hold Time, tAH, tCMH Data Signal Input Setup Time, Data Signal Input Hold Time, Reserved Revision Checksum Bytes 0-62 ENTRY (VERSION) 512MB 1.5ns (-13E/-133) (-10E) 0.8ns (-13E/-133) (-10E) 1.5ns (-13E/-133) (-10E) 0.8ns (-13E/-133) (-10E) REV. -13E -133 -10E MICRON 1-11 MT36LSDT12872 01-09 Variable Data 01-0B Variable Data Variable Data Variable Data MT36LSDT25672 01-09 Variable Data 01-0B Variable Data Variable Data Variable Data
65-71 73-90 95-98 99-125
NOTE:
Manufacturer's JEDEC Code Manufacturer's JEDEC Code (Cont.) Manufacturing Location Module Part Number (ASCII) Identification Code Identification Code (Cont.) Year Manufacture Week Manufacture Module Serial Number Manufacturer-specific Data (RSVD) System Frequency SDRAM Component Clock Detail
100/133
value tRAS used -13E module calculated from tRP. Actual device spec. value 37ns.
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Figure Standard 168-Pin DIMM Dimensions
FRONT VIEW
5.256 (133.50) 5.244 (133.20) 0.320 (8.13)
0.079 (2.00) (2X)
1.705 (43.31) 1.695 (43.05)
0.118 (3.00) (2X) 0.118 (3.00) TYP.
0.700 (17.78) TYP.
0.250 (6.35) TYP. 0.118 (3.00) TYP.
0.054 (1.37) 0.046 (1.17) 0.039 (1.00) R(2X) 0.040 (1.02) TYP. 0.050 (1.27) TYP.
4.550 (115.57)
BACK VIEW
0.128 (3.25) (2X) 0.118 (3.00) 1.661 (42.18) 2.625 (66.68)
NOTE:
dimensions inches (millimeters)
typical where noted.
09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
1GB, (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Figure Low-Profile 168-Pin DIMM Dimensions
FRONT VIEW
5.256 (133.50) 5.244 (133.20) 0.320 (8.13)
0.079 (2.00) (2X)
1.206 (30.63) 1.194 (30.33) 0.700 (17.78)
0.118 (3.00) (2X) 0.118 (3.00) 0.250 (6.35) 0.118 (3.00)
0.039 (1.00) R(2X)
0.040 (1.02)
0.050 (1.27)
0.054 (1.37) 0.046 (1.17)
4.550 (115.57)
BACK VIEW
0.128 (3.25) (2X) 0.118 (3.00) 1.661 (42.18)
2.625 (66.68)
NOTE:
dimensions inches (millimeters)
typical where noted.
Data Sheet Designation
Released Mark): This data sheet contains minimum maximum limits specified over complete power supply temperature range production devices. Although considered final, these specifications subject change, further product development data characterization sometimes occur.
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09005aef80b18348 SD36C128_256x72G_C.fm Rev. 5/03 Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology,
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