SYNCHRONOUS DRAM MODULE JEDEC-standard, 100-pin, dual in-line mem

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

SYNCHRONOUS DRAM MODULE JEDEC-standard, 100-pin, dual in-line mem

Datasheet Thumbnail

Top Searches for this datasheet

16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
SYNCHRONOUS DRAM MODULE
JEDEC-standard, 100-pin, dual in-line memory module (DIMM) 16MB 32), 32MB 32), 64MB 32), 128MB Utilizes SDRAM components Single +3.3V power supply Fully synchronous; signals registered positive edge system clock Internal pipelined operation; column address changed every clock cycle Internal banks hiding access/precharge Programmable burst lengths: full page Auto Precharge Auto Refresh Modes 64ms, 4,096-cycle (16MB, 32MB, 64MB)and 8,192-cycle (128MB) refresh LVTTL-compatible inputs outputs Serial presence-detect (SPD)
MT2LSDT432U 16MB, MT4LSDT832UD 32MB, MT4LSDT1632UD 64MB, MT4LSDT3232UD 128MB
latest data sheet, please refer site: www.micron.com/moduleds
Figure 100-Pin DIMM (MO-161)
Table
Timing Parameters
HOLD TIME 0.8ns
(READ) Latency ACCESS TIME SPEED CLOCK SETUP GRADE FREQUENCY TIME 5.4ns 5.4ns 7.5ns 1.5ns
OPTIONS
Package 100-pin DIMM (Gold) 100-pin DIMM (Lead-Free) Timing (Cycle Timing) 7.5ns (133 MHz) (125 MHz) 10ns (100 MHz)
MARKING
Table
Address Table
16MB
(BA0-BA1)
MODULE DENSITY Refresh Count Device Banks Device Configuration Device Addressing Device Column Addressing Module Ranks
32MB
(BA0-BA1)
64MB
(BA0-BA1)
128MB
(BA0-BA1)
(A0-A11)
(A0-A11)
(A0-A11)
(A0-A12))
(A0-A7)
(S0#, S2#)
(A0-A7)
(A0-A8)
(A0-A8)
(S0#, S2#, S1#, S3#) (S0#, S2#, S1#, S3#) (S0#, S2#, S1#, S3#)
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Table Part Numbers
CONFIGURATION DEVICE PACKAGE TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP TSOP
Table
Assignment (100-Pin DIMM Front)
SYMBOL SYMBOL SYMBOL CKE0 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
PART NUMBER MT2LSDT432UG-75_ MT2LSDT432UY-75_ MT2LSDT432UG-8_ MT2LSDT432UY-8_ MT2LSDT432UG-10_ MT2LSDT432UY-10_ MT4LSDT832UDG-75_ MT4LSDT832UDY-75_ MT4LSDT832UDG-8_ MT4LSDT832UDY-8_ MT4LSDT832UDG-10_ MT4LSDT832UDY-10_ MT4LSDT1632UDG-75_ MT4LSDT1632UDY-75_ MT4LSDT1632UDG-8_ MT4LSDT1632UDY-8_ MT4LSDT1632UDG-10_ MT4LSDT1632UDY-10_ MT4LSDT3232UDG-75_ MT4LSDT3232UDY-75_ MT4LSDT3232UDG-8_ MT4LSDT3232UDY-8_ MT4LSDT3232UDG-10_ MT4LSDT3232UDY-10_
NOTE:
SYMBOL DQMB0
Table
Assignment (100-Pin DIMM Back)
SYMBOL RAS# CAS# SYMBOL CKE1 DQMB3 SYMBOL DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
SYMBOL DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB1
part numbers with two-place code (not shown), designating component revisions. Consult factory current revision codes. Example: MT2LSDT432UG-8B1.
Figure Module Layout
Front View
Back View
(Not populated module)
PIN100
Indicates
Indicates
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Table Descriptions
SYMBOL RAS#, CAS#, CK0, TYPE Input Input DESCRIPTION Command Inputs: RAS#, CAS# (along with define command being entered. Clock: driven system clock. SDRAM input signals sampled positive edge also increments internal burst counter controls output registers. Clock Enable: activates (HIGH) deactivates (LOW) signal. Deactivating clock provides POWER-DOWN SELF REFRESH operation (all banks idle), CLOCK SUSPEND operation (burst access progress). synchronous except after device enters power-down self refresh modes, where becomes asynchronous until after exiting same mode. input buffers, including disabled during power-down self refresh modes, providing standby power. Chip Select: enables (registered LOW) disablse (registered HIGH) command decoder. commands masked when registered HIGH. considered part command code. Input/Output Mask: DQMB input mask signal write accesses output enable signal read accesses. Input data masked when DQMB sampled HIGH during WRITE cycle. output buffers placed High-Z state (after two-clock latency) when DQMB sampled HIGH during READ cycle. Bank Address: define which bank ACTIVE, READ, WRITE PRECHARGE command being applied. Address Inputs: A0-A12 sampled during ACTIVE command (row-address A0-A12) READ/WRITE command (column-address A0-A8, with defining AUTO PRECHARGE) select location memory array respective bank. sampled during PRE-CHARGE command determine both banks precharged (A10 HIGH). address inputs also provide op-code during LOAD MODE REGISTER command. Data I/Os: Data bus.
NUMBERS
CKE0, CKE1
Input
S0#-S3#
Input
DQMB0-DQMB3
Input
13-18, 63-67, 69-70
BA0, A0-A12
Input Input
2-5, 7-10, 38-41, 43-46, 52-55, 57-60, 88-91, 93-96
DQ0-DQ31
Input/ Output Supply Supply Input/ Output Input Input
Power Supply: +3.3V ±0.3V. Ground. Serial Presence-Detect Data: bidirectional used transfer addresses data into data presencedetect portion module. Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module. Presence-Detect Address Inputs: These pins used configure presence-detect device. Reserved Future Use: These pins should left unconnected. Use: These pins connected this module assigned pins compatible DRAM version. connected.
98-100 32-35, 82-85
SA0-SA2
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Figure Functional Block Diagram (16MB)
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQML DQMH
DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 RAS# CAS# CKE0 A0-A11 RAS#: SDRAMs CAS#: SDRAMs CKE: SDRAMs WE#: SDRAMs A0-A11: SDRAMs BA0: SDRAMs BA1: SDRAMs SDRAMs SDRAMs 10pF DQML DQMH 6.8pF
NOTE:
resistor values 10W. industry standard, Micron utilizes various component speed grades referenced Module Part Numbering Guide www.micron.com/numberguide.
SDRAM MT48LC4M16A2TG 16MB module
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Figure Functional Block Diagram (32MB, 64MB, 128MB)
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 RAS# CAS# CKE0 CKE1 A0-A11 (32MB, 64MB) A0-A12 (128MB) DQML DQMH RAS#: SDRAMs CAS#: SDRAMs CKE: SDRAMs U1-U2 CKE: SDRAMs U3-U4 WE#: SDRAMs A0-A11: SDRAMs A0-A12: SDRAMs BA0: SDRAMs BA1: SDRAMs SDRAMs SDRAMs
SDRAMs MT48LC4M16A2TG 32MB module SDRAMs MT48LC8M16A2TG 64MB module SDRAMs MT48LC16M16A2TG 128MB module
DQML DQMH
DQML
DQMH
DQML DQMH 6.8pF
6.8pF
NOTE:
resistor values 10W. industry standard, Micron utilizes various component speed grades referenced Module Part Numbering Guide www.micron.com/numberguide.
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
General Description
MT2LSDT432U, MT4LSDT832UD, MT4LSDT1632UD, MT4LSDT3232UD high-speed CMOS, dynamic random-access, 16MB, 32MB, 64MB, 128MB memory modules organized configuration. These modules SDRAM devices which internally configured quad-bank DRAMs with synchronous interface (all signals registered positive edge clock signal CK). Read write accesses SDRAM module burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed. BA0, select device bank; A0-A11 (16MB, 32MB, 64MB) A0-A12 (128MB). address bits registered coincident with READ WRITE command (A0-A7 16MB 32MB; A0-A8 64MB 128MB) used select starting device column location burst access. These modules provide programmable READ WRITE burst lengths locations, full page, with burst terminate option. auto precharge function enabled provide self-timed precharge that initiated burst sequence. These modules internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows column address changed every clock cycle achieve highspeed, fully random access. Precharging device bank while accessing other three device banks will hide PRECHARGE cycles provide seamless, high-speed, random access operation. These modules designed operate 3.3V, lowpower memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs, outputs, clocks LVTTL-compatible. SDRAM modules offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with automatic column-address generation, ability interleave between internal device banks order hide precharge time, capability randomly change column addresses each clock cycle during burst access. more information regarding SDRAM operation, refer 64Mb, 128Mb, 256Mb SDRAM component data sheets.
Serial Presence-Detect Operation
These modules incorporate serial presence-detect (SPD). function implemented using 2,048-bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters. remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals. Write protect (WP) tied ground module, permanently disabling hardware write protect.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. Once power applied clock stable (stable clock defined signal cycling within timing constraints specified clock pin), SDRAM requires 100µs delay prior issuing command other than COMMAND INHIBIT Starting some point during this 100µs period continuing least through this period, COMMAND INHIBIT commands should applied. Once 100µs delay been satisfied with least COMMAND INHIBIT command having been applied, PRECHARGE command should applied. device banks must then precharged, thereby placing device banks idle state. Once idle state, AUTO REFRESH cycles must performed. After AUTO REFRESH cycles complete, SDRAM ready mode register programming. Because mode register will power unknown state, should loaded prior applying operational command.
Mode Register Definition
mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode write burst mode, shown Figure Mode Register Definition Diagram, page mode register programmed LOAD MODE REGISTER command will retain stored information until programmed again device loses power.
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Mode register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), M4-M6 specify latency, specify operating mode, specifies write burst mode, reserved future use. 128MB module, address (M12) undefined should driven during loading mode register. mode register must loaded when device banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation. latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, READ command registered latency programmed clocks, will start driving after data will valid shown Figure Latency Diagram, page
Burst Length
Read write accesses SDRAM burst oriented, with burst length being programmable, shown Figure Mode Register Definition Diagram. burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. full-page burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached, shown Table Burst Definition, page block uniquely selected A1-A8 (16MB 32MB) A1-A9 (64MB 128MB) when burst length two; A2-A9 when burst length four; A3-A8 A3-A9 when burst length eight. remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached, shown Table Burst Definition, page
Figure Mode Register Definition Diagram
128MB Module
Address
Mode Register (Mx)
Reserved* Reserved*
Mode
Latency
Burst Length
*Should program M12, M11, ensure compatibility with future devices.
16MB, 32MB, 64MB Modules
Address
Mode Register (Mx)
Reserved*
Mode
Latency
Burst Length
*Should program M11, ensure compatibility with future devices.
Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Burst Type Sequential Interleaved Latency Reserved Reserved Reserved Reserved Reserved Reserved
Latency
latency delay, clock cycles, between registration READ command availability first piece output data. latency three clocks. READ command registered clock edge
M6-M0 Defined
Operating Mode Standard Operation other states reserved
Write Burst Mode Programmed Burst Length Single Location Access
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Table Burst Definition
STARTING COLUMN ADDRESS ORDER ACCESSES WITHIN BURST TYPE SEQUENTIAL 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn+1, Cn+2, Cn+3, Cn+4., .Cn-1, TYPE INTERLEAVED 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Supported
Figure Latency Diagram
COMMAND
BURST LENGTH
READ
DOUT
Full Page A0-A8 (512) (location 0-y)
Latency
COMMAND
READ
DOUT
Latency
DON'T CARE UNDEFINED
NOTE:
Table Latency Table, page indicates operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result.
burst length two, A1-A8 select block-of-two burst; selects starting column within block. burst length four, A2-A8 select block-of-four burst; A0-A1 select starting column within block. burst length eight, A3-A8 select block-ofeight burst; A0-A2 select starting column within block. full-page burst, full selected, A0-A8 select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-A8 select unique column accessed, Mode Register ignored.
Operating Mode
normal operating mode selected setting zero; other combinations values reserved future and/or test modes. programmed burst length applies both READ WRITE bursts.
Write Burst Mode
When burst length programmed applies both READ WRITE bursts; when programmed burst length applies READ bursts, write accesses single-location (nonburst) accesses. Test modes reserved states should used because unknown operation incompatibility with future versions result.
Table
Latency Table
ALLOWABLE OPERATING CLOCK FREQUENCY (MHz)
SPEED
LATENCY
LATENCY
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Commands
Truth Table provides general reference available commands. more detailed description commands operations, refer 64Mb, 128Mb, 256Mb SDRAM component data sheet.
Table
Truth Table Commands DQMB Operation
NAME (FUNCTION) RAS# CAS# DQMB L/H7 L/H7 ADDR Bank/Row Bank/Col Bank/Col Code Valid Active NOTES
HIGH commands shown except SELF REFRESH
COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z
NOTE:
Op-Code Active High-Z
A0-A11(32MB) A0-A12 (64MB, 128MB, 128MB) provide address determine which bank made active. A0-A8 provide column address; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge feature; determine which bank being read from written LOW: determine which bank being precharged. HIGH: both banks precharged "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. A0-A11 define op-code written Mode Register. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Absolute Maximum Ratings
Stresses greater than those listed cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operaVoltage Supply Relative +4.6V Voltage Inputs, Pins Relative +4.6V Operating Temperature (ambient) .0°C +70°C tional sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Storage Temperature (plastic) -55°C +125°C Power Dissipation Single-Rank Module Dual-Rank Module
Table Electrical Characteristics Operating Conditions (16MB)
Notes: +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input (All other pins under test -0.3 UNITS NOTES
OUTPUT LEAKAGE CURRENT: disabled; VOUT OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA)
WE#, RAS#, CAS#, A0-A11, BA0, DQMB
Table Electrical Characteristics Operating Conditions (32MB, 64MB, 128MB)
Notes: notes appear page +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input (All other pins under test -0.3 UNITS NOTES
OUTPUT LEAKAGE CURRENT: disabled; VOUT OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA)
WE#, RAS#, CAS#, A0-A11/12, BA0, DQMB
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Table Specifications Conditions (16MB)
Notes: notes appear page +3.3V ±0.3V PARAMETER/CONDITION
IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7
UNITS
NOTES
OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN); latency STANDBY CURRENT: Power-Down Mode; LOW; banks idle STANDBY CURRENT: Active Mode; HIGH; HIGH; banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; banks active; latency AUTO REFRESH CURRENT: (MIN); HIGH; HIGH 15.625µs; SELF REFRESH CURRENT: 0.2V
Table Specifications Conditions (32MB)
Notes: notes appear page +3.3V ±0.3V PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN); latency STANDBY CURRENT: Power-Down Mode; LOW; banks idle STANDBY CURRENT: Active Mode; HIGH; HIGH; banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; banks active; latency AUTO REFRESH CURRENT: (MIN); HIGH; HIGH 15.625µs; SELF REFRESH CURRENT: 0.2V IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 1,240 UNITS NOTES
Table Specifications Conditions (64MB)
Notes: notes appear page +3.3V ±0.3V PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN); latency STANDBY CURRENT: Power-Down Mode; LOW; banks idle STANDBY CURRENT: Active Mode; HIGH; HIGH; banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; banks active; latency AUTO REFRESH CURRENT: (MIN); HIGH; HIGH 15.625µs; SELF REFRESH CURRENT: 0.2V
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7
1,240
UNITS
NOTES
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Table Specifications Conditions (128MB)
Notes: notes appear page +3.3V ±0.3V PARAMETER/CONDITION
IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7
1,080
1,080
1,080
UNITS
NOTES
OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN); latency STANDBY CURRENT: Power-Down Mode; LOW; banks idle STANDBY CURRENT: Active Mode; HIGH; HIGH; banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; banks active; latency AUTO REFRESH CURRENT: (MIN); HIGH; HIGH 7.8125µs; SELF REFRESH CURRENT: 0.2V
Table Capacitance (16MB)
Note: notes appear page PARAMETER Input Capacitance: A0-A11, BA0, BA1, RAS#, CAS#, Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: DQMB Input Capacitance: SCL, SA0-SA2, Input/Output Capacitance: SYMBOL 11.8 13.8 UNITS
Table Capacitance (32MB, 64MB, 128MB)
Note: notes appear page PARAMETER Input Capacitance: A0-A11, BA0, BA1, RAS#, CAS#, Input Capacitance: Input Capacitance: Input Capacitance: Input Capacitance: DQMB Input Capacitance: SCL, SA0-SA2, Input/Output Capacitance: SYMBOL 11.8 15.2 13.8 15.2 UNITS
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Table SDRAM Component Electrical Characteristics
Notes: notes appear page CHARACTERISTICS PARAMETER Access time from (positive edge) Address hold time Address setup time high-level width low-level width Clock cycle time hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time load) ACTIVE PRECHARGE command period ACTIVEto ACTIVE command period AUTO REFRESH period ACTIVE READ WRITE delay Refresh period (8,192 cycles) PRECHARGE command period ACTIVE bank ACTIVE bank command period Transition time WRITE recovery time
SYMBOL 120,000
120,000
UNITS NOTES 120,000
CL=3
RCAR
Exit SELF REFRESH ACTIVE command
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Table Functional Characteristics
Notes: notes appear page PARAMETER READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVATE command Data-in precharge Last data-in BURST STOP command Last data-in READ/WRITE command Lastdata-intoPRECHARGEcommand LOAD MODE REGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command CL=2 SYMBOL
UNITS
NOTES
CKED
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Notes
voltages referenced VSS. This parameter sampled. +3.3V; MHz. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range (0°C 70°C) ensured. initial pause 100µs required after powerup, followed Auto Refresh commands, before proper device operation ensured. Auto Refresh command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between Vih) monotonic manner. Outputs measured 1.5V with equivalent load:
50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have with timing referenced 1.5V crossover point. Other input signals allowed transition more than once every clocks otherwise valid levels. specifications tested after device properly initialized. Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate.
Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate. Timing actually specified tWR. Clocks required specified JEDEC functionality dependent timing parameter. current will decrease latency reduced. This fact that maximum cycle rate slower latency reduced. Address transitions average transition every clocks. must toggled minimum times during this period. Based -75, andtCK -10. overshoot: (MAX) pulse width 10ns, pulse width cannot greater than third cycle rate. undershoot: (MIN) pulse width 10ns, pulse width cannot greater than third cycle rate. clock frequency must remain constant (stable clock defined signal cycling within timing constraints specified clock pin) during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. precharge timing budget (tRP) begins after first clock delay, after last WRITE executed. Precharge mode only. JEDEC specifies three clocks. 7.5ns -75, 10ns 15ns -10. HIGH during refresh command period RFC(MIN), else LOW. IDD6 limit actually nominal value does result fail value. Refer device data sheet timing waveforms. Leakage number reflects worst case leakage possible through module pin, what each memory device contributes.
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Clock Data Conventions
Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions shown Figure Data Validity, Figure Definition Start Stop).
Acknowledge
Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data shown Figure Acknowledge Response from Receiver). device will always respond with acknowledge after recognition start condition slave address. both device write operation have been selected, device will respond with acknowledge after receipt each subsequent eight-bit word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
Start Condition
commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met.
Stop Condition
communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode.
Figure Data Validity
Figure Definition Start Stop
DATA STABLE DATA CHANGE DATA STABLE
START
STOP
Figure Acknowledge Response from Receiver
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Table EEPROM Device Select Code
Most significant (b7) sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code DEVICE TYPE IDENTIFIER CHIP ENABLE
Table EEPROM Operating Modes
MODE Current Address Read RandomAddressRead Sequential Read Byte Write Page Write BYTES INITIAL SEQUENCE Start, Device Select, Start, Device Select, Address RESTART, Device Select, Similar Current Random Address Read START, Device Select, START, Device Select,
Figure EEPROM
HIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
UNDEFINED
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs POWER SUPPLY CURRENT: clock frequency SYMBOL UNITS
Table Serial Presence-Detect EEPROM Electrical Characteristics
voltages referenced VSS; +3.3V ±0.3V PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time ClockHIGHperiod Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time
NOTE:
SYMBOL
UNITS
NOTES
HD:DAT HD:STA
HIGH
SU:DAT SU:STA
SU:STO
EEPROM write cycle time (tWRC) time from valid stop condition write sequence EEPROM internal erase/program cycle. During write cycle, EEPROM interface circuit disabled, remains HIGH pull-up resistor, EEPROM does respond slave address.
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Table Serial Presence-Detect Matrix (16MB, 32MB)
"1"/"0": Serial Data, "driven HIGH"/"driven LOW"
BYTE
DESCRIPTION Number Bytes Used Micron Total Number Memory Bytes Memory Type Number Addresses Number Column Addresses Number Module Ranks Module Data Width Module Data Width (continued) Module Voltage Interface Levels SDRAM Cycle Time, (CAS Latency
ENTRY (VERSION) SDRAM LVTTL 7.5ns (-75) (-8) 10ns (-10) 5.4ns (-75 (-8) 7.5ns (-10) None 15.625µs/Self
MT2LSDT432U
MT4LSDT832UD
SDRAM Access From Clock, (CAS Latency
Module Configuration Type Refresh Rate/Type SDRAM Width (Primary SDRAM) Error-Checking SDRAM Data Width Minimum Clock Delay, tCCD Burst Lengths Supported Number Banks SDRAM Device Latencies Supported Latency Latency SDRAM Module Attributes SDRAM Device Attributes: General
Page Unbuffered Attributes 10ns (-75/-8) SDRAM Cycle Time, (CAS Latency 15ns (-10) (-75/-8) SDRAM Access From Clock, tAC, (CAS Latency (-10) SDRAM Cycle Time, (CAS Latency Supported SDRAM Access From Clock, tAC, (CAS Latency Supported 20ns (-75/-8) Minimum Precharge Time, 30ns (-10) 15ns (-75) Minimum Active Active, tRRD 20ns (-8/-10) 20ns (-75/-8) Minimum RAS# CAS# Delay, tRCD 30ns (-10) 44ns (-75) Minimum RAS# Pulse Width, 50ns (-8) 60ns (-10) 16MB Module Rank Density 1.5ns (-75) Command Address Setup, (-8/-10) 0.8ns (-75) Command Address Hold, (-8/-10)
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Table Serial Presence-Detect Matrix (16MB, 32MB) (Continued)
"1"/"0": Serial Data, "driven HIGH"/"driven LOW"
BYTE 36-61
DESCRIPTION Data Signal Input Setup, Data Signal Input Hold, Reserved Bytes Revision Checksum Bytes 0-62
ENTRY (VERSION) 1.5ns (-75) (-8/-10) 0.8ns (-75) (-8/-10) REV. (-75) (-8) (-10) MICRON 1-11
MT2LSDT432U 01-0B Variable Data 01-09 Variable Data Variable Data Variable Data
MT4LSDT832UD 01-0B Variable Data 01-09 Variable Data Variable Data Variable Data
65-71 73-90 95-98 99-127
Manufacturer's JEDEC Code Manufacturer's JEDEC Code (Cont.) Manufacturing Location Module Part Number (ASCII) Identification Code Identification Code (Continuted) Year Manufacture Week Manufacture Module Serial Number Manufacturer-Specific Data (RSVD)
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Table Serial Presence-Detect Matrix (64MB, 128MB)
"1"/"0": Serial Data, "driven HIGH"/"driven LOW"
BYTE
DESCRIPTION Number Bytes Used Micron Total Number Memory Bytes Memory Type Number Addresses Number Column Addresses Number Module Ranks Module Data Width Module Data Width (continued) Module Voltage Interface Levels SDRAM Cycle Time, (CAS Latency
ENTRY (VERSION) SDRAM LVTTL 7.5ns(-75) (-8) 10ns(-10) 5.4(-75) (-8) 7.5ns (-10) None 15.625µs, 7.81µs/ Self Page Unbuffered Attributes 10ns (-75/-8) 15ns (-10) (-75/-8) (-10) Supported Supported 20ns (-75/-8) 30ns (-10) 15ns (-75) 20ns (-10/-8) 20ns (-75/-8) 30ns (-10) 44ns (-75) 50ns (-8) 60ns (-10) 32MB 64MB 1.5ns (-75) (-8/-10) 0.8ns (-75) (-8/-10)
MT4LSDT1632UD
MT4LSDT3232UD
SDRAM Access From Clock, (CAS Latency
Module Configuration Type Refresh Rate/Type SDRAM Width (Primary SDRAM) Error-Checking SDRAM Data Width Minimum Clock Delay, tCCD Burst Lengths Supported Number Banks SDRAM Device Latencies Supported Latency Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, (CAS Latency SDRAM Access From Clock, tAC, (CAS Latency SDRAM Cycle Time, (CAS Latency SDRAM Access From Clock, tAC, (CAS Latency Minimum Precharge Time, Minimum Active Active, tRRD Minimum RAS# CAS# Delay, tRCD Minimum RAS# Pulse Width, tRAS
Module Rank Density Command Address Setup, Command Address Hold,
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Table Serial Presence-Detect Matrix (64MB, 128MB) (Continued)
"1"/"0": Serial Data, "driven HIGH"/"driven LOW"
BYTE 36-61
DESCRIPTION Data Signal Input Setup, Data Signal Input Hold, Reserved Bytes Revision Checksum Bytes 0-62
ENTRY (VERSION) 1.5ns (-75) (-8/-10) 0.8ns (-75) (-8/-10) REV. (-75) (-8) (-10) MICRON 1-11
MT4LSDT1632UD 01-0B Variable Data 01-09 Variable Data Variable Data Variable Data
MT4LSDT3232UD 01-0B Variable Data 01-09 Variable Data Variable Data Variable Data
65-71 73-90 95-98 99-127
Manufacturer's JEDEC Code Manufacturer's JEDEC Code (Cont.) Manufacturing Location Module Part Number (ASCII) Identification Code Identification Code (Continuted) Year Manufacture Week Manufacture Module Serial Number Manufacturer-Specific Data (Rsvd)
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Figure 100-Pin DIMM Dimensions (16MB)
Front View
3.557 (90.34) 3.545 (90.04) 0.079 (2.00) (2X)
0.125 (3.18)
1.005 (25.53) 0.995 (25.27) 0.700 (17.78)
0.118 (3.00) (2X) 0.118 (3.00)
0.118 (3.00)
0.250 (6.35) 0.039 (1.00) R(2X)
0.128 (3.25) (2X) 0.118 (3.00) 0.039 (1.00) 0.050 (1.27)
0.054 (1.37) 0.046 (1.17)
2.850 (72.39)
Back View
Components This Side Module
NOTE:
dimensions inches (millimeters)
typical where noted.
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32) 100-PIN SDRAM DIMM
Figure 100-Pin DIMM Dimensions (16MB)
Front View
3.557 (90.34) 3.545 (90.04) 0.157 (4.00)
0.079 (2.00) (2X)
1.005 (25.53) 0.995 (25.27) 0.700 (17.78)
0.118 (3.00) (2X) 0.118 (3.00)
0.118 (3.00)
0.250 (6.35) 0.039 (1.00) R(2X)
0.128 (3.25) (2X) 0.118 (3.00) 0.039 (1.00) 0.050 (1.27)
0.054 (1.37) 0.046 (1.17)
2.850 (72.39)
Back View
NOTE:
dimensions inches (millimeters)
typical where noted.
Data Sheet Designation
Released Mark): This data sheet contains minimum maximum limits specified over complete power supply temperature range production devices. Although considered final, these specifications subject change, further product development data characterization sometimes occur.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, logo, Micron logo trademarks and/or service marks Micron Technology, Inc.
09005aef80948ad4 SD2_4C4_8_16_32x32UDG_A.fm Rev. 2/03
©2003, Micron Technology Inc.

SYNCHRONOUS DRAM MODULE JEDEC-standard, 100-pin, dual in-line mem

Top Searches for this datasheet

Other recent searches