SYNCHRONOUS DRAM MODULE JEDEC-standard 168-pin, dual in-line memo
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128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
SYNCHRONOUS DRAM MODULE
JEDEC-standard 168-pin, dual in-line memory module (DIMM) PC133- PC100-compliant Registered inputs with one-clock delay Phase-lock loop (PLL) clock driver reduce loading Utilizes SDRAM components ECC-optimized pinout Single +3.3V power supply Fully synchronous; signals registered positive edge clock Internal pipelined operation; column address changed every clock cycle Internal SDRAM banks hiding access/precharge Programmable burst lengths: full page Auto Precharge Auto Refresh Modes Self Refresh Mode 128MB 256MB: 64ms, 4,096-cycle refresh; 512MB: 64ms, 8,192-cycle refresh LVTTL-compatible inputs outputs Serial Presence-Detect (SPD)
OPTIONS MARKING
latest data sheet, please refer site: www.micron.com/moduleds
MT18LSDT1672G 128MB, MT18LSDT3272G 256MB, MT18LSDT6472G 512MB
Figure 168-Pin DIMM (MO-168)
Standard
Profile
Table
Timing Parameters
SETUP TIME HOLD TIME
ACCESS TIME MODULE CLOCK MARKING FREQUENCY -13E -133 -10E 5.4ns 5.4ns 7.5ns
Package 168-pin DIMM (gold) Frequency/CAS Latency MHz/CL MHz/CL MHz/CL
NOTE:
-13E -133 -10E
Table
Part Numbers
CONFIG SYSTEM SPEED
PART NUMBER MT18LSDT1672G-13E_ MT18LSDT1672G-133_ MT18LSDT1672G-10E_ MT18LSDT3272G-133_ MT18LSDT3272G-13E_ MT18LSDT3272G-10E_ MT18LSDT6472G-133_ MT18LSDT6472G-13E_ MT18LSDT6472G-10E_
NOTE:
Registered mode adds clock cycle
Table
PARAMETER
Address Table
128MB 256MB 512MB
Refresh Count Device Config. (BA0, BA1) (BA0, BA1) (BA0, BA1) Device Banks Addressing 4K(A0-A11) (A0-A11) (A0-A12) (A0-A9) (A0-A9,A11) (A0-A9,A11) Column Addr. (S0,S2) (S0,S2) (S0,S2) Module Ranks
designators component revision last characters each part number. Consult factory current revision codes. Example: MT18LSDT1672G-133B1
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Assignment (168-Pin DIMM Front)
DQMB0 DQMB1 DQMB2 DQMB3 DQ16 DQ17 DQ18 DQ19 DQ20 CKE1 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Table
Assignment (168-Pin DIMM Back)
CKE0 DQMB6 DQMB7 CAS# DQMB4 DQMB5 RAS# DQ48 DQ49 DQ50 DQ51 DQ52 NC/A12 REGE DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SYMBOL SYMBOL SYMBOL SYMBOL
NOTE:
SYMBOL SYMBOL SYMBOL SYMBOL DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
128MB 256MB modules, 512MB module.
Figure Locations (168-Pin DIMM)
Front View
Front ViewFront View
Back View Back View
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Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Descriptions
SYMBOL WE#, CAS#, RAS# CK0-CK3 CKE0 TYPE Input Input Input DESCRIPTION Command Inputs: WE#, CAS#, RAS# (along with S0#, S2#) define command being entered. Clock: distributed through on-board devices. CK1-CK3 terminated. Clock Enable: CKE0 activates (HIGH) deactivates (LOW) signal. Deactivating clock provides POWERDOWN SELF REFRESH operation (all device banks idle) CLOCK SUSPEND operation (burst access progress). CKE0 synchronous except after device enters power-down self refresh modes, where CKE0 becomes asynchronous until after exiting same mode. input buffers, including CK0, disabled during power-down self refresh modes, providing standby power. Chip Select: S0#, enable (registered LOW) disable (registered HIGH) command decoder. commands masked when S0#, registered HIGH. S0#, considered part command code. Input/Output Mask: DQMB input mask signal write accesses output enable signal read accesses. Input data masked when DQMB sampled HIGH during WRITE cycle. output buffers placed High-Z state (twoclock latency) when DQMB sampled HIGH during READ cycle. Bank Address: define which device bank ACTIVE, READ, WRITE PRECHARGE command being applied. Address Inputs: A0-A11 (128MB/256MB) A0-A12 (512MB) sampled during ACTIVE command (device rowaddress A0-A11/12) READ/WRITE command (device column-address A0-A9 (128MB) A9/A11 (256MB/ 512MB), with defining auto precharge) select location memory array respective device bank. sampled during PRECHARGE command determine both device banks precharged (A10 HIGH). address inputs also provide op-code during LOAD MODE REGISTER command. Write Protect: Serial presence-detect hardware write protect. Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module. Presence-Detect Address Inputs: These pins used configure presence-detect device. Register Enable. Data I/Os: Data bus.
numbers listed module pinout order; assignment tables page more information NUMBERS 111, 125,
S0#,
Input
28-29, 46-47, 112-113, 130131
DQMB0- DQMB7
Input
BA0,
Input
33-38, 117-121, 123, (512MB)
A0-A11 (128MB/ 256MB) A0-A12 (512MB)
Input
165-167 2-5, 7-11, 13-17, 19-20, 5558, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103104, 139-142, 144, 149-151, 153-156, 158-161 21-22, 52-53, 105-106, 136-137
SA0-SA2 REGE DQ0-DQ63
Input Input Input Input Input/ Output
CB0-CB7
Input/ Output
Check Bits.
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
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128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Descriptions (Continued)
SYMBOL TYPE Input/ Output\ Supply DESCRIPTION Serial Presence-Detect Data: bidirectional used transfer addresses data into data presence-detect portion module. Power Supply: +3.3V ±0.3V. numbers listed module pinout order; assignment tables page more information NUMBERS
40-41, 102, 110, 124, 133, 143, 157, 107, 116, 127, 138, 148, 152, 108, 109, 114, (128/256MB),129, 132, 134, 135, 145, 146,
Supply
Ground.
Connected: These pins connected these modules.
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
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128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Figure Functional Block Diagram
RS0# RDQMB0 RDQMB4 DQ32 DQ33 DQ34 DQ35
RDQMB1 DQ10 DQ11
DQ36 DQ37 DQ38 DQ39 RDQMB5
DQ40 DQ41 DQ41 DQ43
DQ12 DQ13 DQ14 DQ15
DQ44 DQ45 DQ46 DQ47
RS2# RDQMB2 DQ16 DQ17 DQ18 DQ19
RDQMB6 DQ48 DQ49 DQ50 DQ51
DQ20 DQ21 DQ22 DQ23 RDQMB3 DQ24 DQ25 DQ26 DQ27
DQ52 DQ53 DQ54 DQ55 RDQMB7
DQ56 DQ57 DQ58 DQ59
DQ28 DQ29 DQ30 DQ31
DQ60 DQ61 DQ62 DQ63
U10, U11, RAS# CAS# CKE0 (128MB/256MB) A0-A11 (512MB) A0-A12 S0#, DQMB0 DQMB7 REGE
RRAS#: SDRAMs RCAS#: SDRAMs RCKE0: SDRAMs RWE#: SDRAMs RA0-RA11: SDRAMs RA0-RA12: SDRAMs RBA0: SDRAMs RBA1: SDRAMs RS0#, RS2# RDQMB0 RDQMB7 SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM REGISTER
12pF
SDRAMs SDRAMs
CK1-CK3
12pF
NOTE:
resistor values ohms unless otherwise specified. industry standard, Micron uses various component speed grades referenced Module Part Numbering Guide www.micron.com/numberguide.
SDRAMS MT48LC16M4A2TG 128MB SDRAMS MT48LC32M4A2TG 256MB SDRAMS MT48LC64M4A2TG 512MB
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128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
General Description
MT18LSDT1672G, MT18LSDT3272G, MT18LSDT6472G high-speed CMOS, dynamic random-access, 128MB, 256MB, 512MB memory modules organized (ECC) configuration. These modules internally configured quad-bank SDRAM devices, with synchronous interface (all signals registered positive edge clock signal CK0). Read write accesses SDRAM modules burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed (BA0, select device bank, A0-A11 select device 128MB 256MB modules; A0-A12 select device 512MB module). address bits registered coincident with READ WRITE command used select starting device column location burst access. These modules provide programmable read write burst lengths locations, full page, with burst terminate option. auto precharge function enabled provide self-timed device precharge that initiated burst sequence. These modules internal pipelined architecture. Precharging device bank while accessing other three device banks will hide PRECHARGE cycles provide seamless, high-speed, random-access operation. These modules designed operate 3.3V, lowpower memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs outputs LVTTL-compatible. SDRAM modules offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with automatic device column-address generation, ability interleave between device banks order hide precharge time, capability randomly change device column addresses each clock cycle during burst access. more information regarding SDRAM operation, refer 64Mb, 128Mb, 256Mb SDRAM data sheets. clock edge sent SDRAM devices following rising clock edge (data access delayed clock), buffered mode (REGE LOW) where input signals pass through register/buffer SDRAM devices same clock. phase-lock loop (PLL) modules used redrive clock signals SDRAM devices minimize system clock loading (CK0 connected PLL, CK1, CK2, terminated).
Serial Presence-Detect Operation
These modules incorporate serial presence-detect (SPD). function implemented using 2,048-bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters. remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals, together with (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) tied ground module, permanently disabling hardware write protect.
SDRAM Component Description
general, 64Mb, 128Mb, 256Mb SDRAM memory devices used these modules quadbank DRAMs, that operate 3.3V include synchronous interface (all signals registered positive edge clock signal, CK). four banks 64Mb device each configured 4,096 bitrows, 1,024 bit-columns, input/output bits. four banks 128Mb device each configured 4,096 bit-rows, 2,048 bit-columns, input/ output bits. four banks 256MB device configured 8,192 bit-rows, 2,048 columns, input/output bits.
Module Functional Description
Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed select device bank, A0-A11 (for 128MB 256MB module), A0-A12 (for 512MB
Register Operation
These modules operated either registered mode (REGE HIGH), where control/address input signals latched register rising
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
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128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
module), select device row. address bits A0-A9 (for 64MB) A0-A9, (for 256MB 512MB module), registered coincident with READ WRITE command used select starting device column location burst access. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions device operation. burst mode, reserved future use. 512MB module, address (M12) undefined should driven during loading mode register. mode register must loaded when device banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. Once power applied VddQ (simultaneously) clock stable (stable clock defined signal cycling within timing constraints specified clock pin), SDRAM requires 100µs delay prior issuing command other than COMMAND INHIBIT Starting some point during this 100µs period continuing least through this period, Command Inhibit commands should applied. Once 100µs delay been satisfied with least Command Inhibit command having been applied, PRECHARGE command should applied. device banks must then precharged, thereby placing device device banks idle state. Once idle state, AUTO refresh cycles must performed. After AUTO refresh cycles complete, SDRAM ready mode register programming. Because mode register will power unknown state, should loaded prior applying operational command.
Figure Mode Register Definition Diagram
128MB 256MB Modules
Address
Mode Register (Mx)
Reserved*
*Should program M11, ensure compatibility with future devices.
Mode
Latency
Burst Length
512MB Module
Address
Mode Register (Mx)
Reserved* Reserved*
Mode
Latency
Burst Length
*Should program M12, M11, ensure compatibility with future devices.
Burst Length Reserved Reserved Reserved Full Page Burst Type Sequential Interleaved Reserved Reserved Reserved Reserved
Mode Register Definition
mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode write burst mode, shown Mode Register Definition Diagram. mode register programmed LOAD MODE REGISTER command will retain stored information until programmed again device loses power. Mode register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), M4-M6 specify latency, specify operating mode, specifies write
Latency Reserved Reserved Reserved Reserved Reserved
M6-M0 Defined
Operating Mode Standard Operation other states reserved
Write Burst Mode Programmed Burst Length Single Location Access
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
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128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Burst Length
Read write accesses SDRAM burst oriented, with burst length being programmable, shown Mode Register Definition Diagram. burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. full-page burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached, shown Burst Definition Table. block uniquely selected A1A9 (64MB) A1-A9, (128MB/256MB) when burst length two; A2-A9 A2-A9, when burst length four; A3-A9 A3-A9, when burst length eight. remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached, shown Burst Definition Table.
Table
Burst Definition Table
STARTING COLUMN ADDRESS ORDER ACCESSES WITHIN BURST TYPE SEQUENTIAL 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn+1, Cn+2, Cn+3, Cn+4., .Cn-1, TYPE INTERLEAVED 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Notsupported
BURST LENGTH
Full Page
NOTE:
A0-A9, =A0-A9/A11 (location 0-y)
Burst Type
Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Burst Definition Table.
Latency
latency delay, clock cycles, between registration READ command availability first piece output data. latency three clocks.
full-page accesses: 1,024 (128MB); 2,048 (256MB and512MB). burst length two, A1-A9 (128MB) A9/A11(256MB and512MB) select block burst; selects starting column within block. burst length four, A2-A9 A2-A9/A11 select block four burst; A0-A1 select starting column within block. burst length eight, A3-A9 A3-A9/A11 select block eight burst; A0-A2 select starting column within block. full-page burst, full selected A0-A9 A0-A9/A11 select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-A9 A0-A9/A11 select unique column accessed, Mode Register ignored.
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
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128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, read command registered latency programmed clocks, will start driving after data will valid shown Latency Diagram. Latency Table indicate operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result.
Figure Latency Diagram
COMMAND
READ
DOUT
Latency
COMMAND
READ
DOUT
Operating Mode
normal operating mode selected setting zero; other combinations values reserved future and/or test modes. programmed burst length applies both read write bursts. Test modes reserved states should used because unknown operation incompatibility with future versions result.
Latency DON'T CARE UNDEFINED
Table
Latency Table
Registered mode will clock cycle Latency (CL) listed ALLOWABLE OPERATING FREQUENCY (MHZ) SPEED -13E -133 -10E
Write Burst Mode
When burst length programmed M0-M2 applies both read write bursts; when programmed burst length applies read bursts, write accesses single-location (nonburst) accesses.
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
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128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Commands
Truth Table provides quick reference available commands. This followed written description each command. more detailed description commands operations refer 64Mb, 128Mb, 256Mb SDRAM component datasheets.
Table
Truth Table SDRAM Commands DQMB Operation
NAME (FUNCTION) RAS# CAS# DQMB L/H8 L/H8 ADDR Bank/Row Bank/Col Bank/Col Code Valid Active NOTES
Note: notes appear below table)
COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z
NOTE:
Op-Code Active High-Z
HIGH commands shown except Self Refresh. A0-A11 (128MB 256MB), A0-A12 (512MB) define op-code written Mode Register, should driven low. A0-A11 (128MB 256MB), A0-A12 (512MB) provide device address. BA0, determine which device bank made active. A0-A9 provide device column address 128MB module; A0-A9/A11 256MB 512MB modules; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge feature; BA0, determine which device bank being read from written LOW: BA0, determine which device bank being precharged. HIGH: both device banks precharged BA0, "Don't Care." This command Auto Refresh HIGH, Self Refresh LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
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128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Absolute Maximum Ratings
Stresses greater than those listed cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operaVoltage Supply Relative +4.6V Voltage Inputs, Pins Relative +4.6V Operating Temperature (ambient) .0°C +70°C
Notes: notes appear page +70°C PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input (All other pins under test inputs: A0-A12, BA0, BA1, RAS#, CAS#,WE#, CKE0 INPUT LEAKAGE CURRENT: input (All other pins under test inputs: DQMB OUTPUT LEAKAGE CURRENT: disabled; VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA) SYMBOL VDD, VDDQ -0.3
tional sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Storage Temperature (plastic) -55°C +150°C Power Dissipation
Table Electrical Characteristics Operating Conditions
UNITS NOTES
Table Specifications Conditions (128MB)
SDRAM components only Notes: notes appear page +70°C; VDDQ +3.3V ±0.3V PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT HIGH; tRFC (MIN) HIGH 15.6 SELF REFRESH CURRENT: 0.2V
SYMBOL IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7
-13E 1,250 2,700 4,140
-133 2,070 2,520 3,780
-10E 1,710 2,160 3,420
UNITS
NOTES
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128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Specifications Conditions (256MB)
SDRAM components only Notes: notes appear page +70°C; VDDQ +3.3V ±0.3V PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT HIGH; tRFC (MIN) HIGH 15.6 SELF REFRESH CURRENT: 0.2V SYMBOL IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 -13E 2,880 2,970 5,940 -133 2,700 2,700 5,580 -10E 2,520 2,520 4,860 UNITS NOTES
Table Specifications Conditions (512MB)
SDRAM components only Notes: notes appear page +70°C; VDDQ +3.3V ±0.3V PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT HIGH; tRFC (MIN) HIGH 15.6 SELF REFRESH CURRENT: 0.2V
SYMBOL IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7
-13E 2,430 2,430 5,130
-133 2,250 2,430 4,860
-10E 2,250 2,430 4,860
UNITS
NOTES
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128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table CAPACITANCE (128MB, 256MB, 512MB)
Note: notes appear page PARAMETER Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, WE#, CKE0 Input Capacitance: S0#, S2#, DQMB0-DQMB7 Input Capacitance: Input Capacitance: SCL, SA0-SA2, Input Capacitance: CK1-CK3 Input Capacitance: REGE Input/Output Capacitance: DQ0-DQ63, CB0-CB3, CB4-CB7 SYMBOL UNITS
Table SDRAM Component Electrical Characteristics Recommended Operating Conditions
Notes: notes appear page CHARACTERISTICS PARAMETER Access time from CLK(pos.edge) Address hold time Address setup time high-level width low-level width Clock cycle time hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time load) ACTIVE CHARGE command ACTIVE ACTIVE command period ACTIVE READ WRITE delay Refresh period (8,192 rows) AUTO REFRESH period CHARGE command period
-13E SYMBOL CL=3 CL=2
-133 120,000
-10E UNITS 120,000 NOTES
AC(3) AC(2)
120,000
CL=3
CK(3) CK(2)
HZ(3) HZ(2)
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
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128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table SDRAM Component Electrical Characteristics Recommended Operating Conditions (Continued)
Notes: notes appear page CHARACTERISTICS PARAMETER ACTIV bank ACTIVE bank command Transition time WRITE recovery time
-13E SYMBOL
-133 7.5ns
-10E UNITS NOTES
Exit SELF REFRESH ACTIVE command
Table Functional Characteristics
Notes: notes appear page PARAMETER READ/WRITEc ommand READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVEcommand Data-in CHARGEcommand Last data-in burst STOP command Last data-in READ/WRITE command Last data-in PRECHARGEcommand LOAD MODE REGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command CL=3
SYMBOL -13E -133
-10E
UNITS
NOTES
CKED
ROH(3) ROH(2)
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
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128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Notes
voltages referenced VSS. This parameter sampled. VDD, VVDDQ +3.3V; MHz, 25°C; under test biased 1.4V. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range ensured; (0°C +70°C). initial pause 100µs required after powerup, followed AUTO Refresh commands, before proper device operation ensured. (VDD VDDQ must powered simultaneously. VSSQ must same potential.) AUTO Refresh command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load:
50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have with timing referenced 1.5V crossover point. input transition time longer than then timing referenced (MAX) (MIN) longer 1.5V crossover point. Other input signals allowed transition more than once every clocks otherwise valid levels. specifications tested after device properly initialized. Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate. Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate.
Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will increase decrease proportionally according amount frequency alteration test condition. Address transitions average transition every clocks. must toggled minimum times during this period. Based 10ns -10E, 7.5ns -13E. overshoot: (MAX) VDDQ pulse width 3ns, pulse width cannot greater than third cycle rate. undershoot: (MIN) pulse width 3ns. clock frequency must remain constant (stable clock defined signal cycling within timing constraints specified clock pin) during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. precharge timing budget (tRP) begins -13E; 7.5ns -133 -10E after first clock delay, after last WRITE executed. exceed limit precharge mode. Precharge mode only. JEDEC PC100 specify three clocks. -133/-13E with load 4.6ns guaranteed design. Parameter guaranteed design. value tRAS. -13E speed grade module SPDs calculated from 45ns. -10E, 10ns; -133, 7.5ns; -13E, 7.5ns. HIGH during refresh command period (MIN) else LOW. IDD6 limit actually nominal value does result fail value. This timing function will show extra clock cycle when registered mode. Leakage number reflects worst case leakage possible through module pin, what each memory device contributes.
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Clock Data Conventions
Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions shown Figure Data Validity, Figure Definition Start Stop).
Acknowledge
Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data shwon Figure Acknowledge Response from Receiver). device will always respond with acknowledge after recognition start condition slave address. both device write operation have been selected, device will respond with acknowledge after receipt each subsequent eight-bit word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
Start Condition
commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met.
Stop Condition
communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode.
Figure Data Validity
Figure Definition Start Stop
DATA STABLE DATA CHANGE DATA STABLE
START
STOP
Figure Acknowledge Response from Receiver
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table EEPROM Device Select Code
Most significant (b7) sent first) SELECT CODE Memory Area Select Code (Two Arrays) Protection Register Select Code DEVICE TYPE IDENTIFIER CHIP ENABLE
Table EEPROM Operating Modes
MODE Current Address Read Random Ddress Read Sequential Read Byte Write Page Write BYTES INITIAL SEQUENCE Start, Device Select, Start, Device Select, Address Restart, Device Select, Similar Current Random Address Read Start, Device Select, Start, Device Select,
Figure EEPROM Timing Diagram
HIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
UNDEFINED
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs POWER SUPPLY CURRENT: clock frequency SYMBOL UNITS
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; +3.3V ±0.3V PARAMETER/CONDITION data-out valid Time must free before transition cans tart Data-out hold time fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITEcycle time
NOTE:
SYMBOL
UNITS
NOTES
HD:DAT HD:STA
HIGH
SU:DAT SU:STA
SU:STO
EEPROM WRITE cycle time (tWRC) time from valid stop condition write sequence EEPROM internal erase/program cycle. During WRITE cycle, EEPROM interface circuit disabled, remains HIGH pull-up resistor, EEPROM does respond slave address.
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Serial Presence- Detect Matrix
"1"/"0": Serial Data, "driven HIGH"/"driven LOW" BYTE DESCRIPTION Number Bytes Used Micron Total Number Memory Bytes Memory Type Number Addresses Number Column Addresses Number Module Ranks Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, (CAS Latency SDRAM Access From Clock, (CAS Latency Module Configuration Type Refresh Rate/type SDRAM Width (Primary SDRAM) Error-Checking SDRAM Data Width Minimum Clock Delay, tCCD Burst Lengths Supported Number Banks SDRAM Device Latencies Supported Latency Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, (CAS Latency SDRAM Access From Clock, tAC, (CAS Latency SDRAM Cycle Time, (CAS Latency SDRAM Access From Clock, (CAS Latency Minimum Precharge Time, Minimum Active Active, Minimum RAS# CAS# Delay, tRCD Minimum RAS# Pulse Width, tRAS (See note Module Rank Density
ENTRY (VERSION) SDRAM 12or13 10or11 LVTTL (-13E) (-133) (-10E) (-13E/-133) (-10E) 7.8/15.6µs/SELF PAGE -133 (-13E) (-133/-10E) (-13E) (-133/-10E) (-13E) (-133/-10E) 14(-13E) (-133) (-10E) (-13E) (-133/-10E) (-13E) (-133) (-10E) 128MB/ 256MB/512MB
MT18LSDT1672G MT18LSDT3272G MT18LSDT6472G
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Serial Presence- Detect Matrix (Continued)
"1"/"0": Serial Data, "driven HIGH"/"driven LOW" BYTE 36-61 DESCRIPTION Command Address Setup, Command Address Hold, Data Signal Input Setup, Data Signal Input Hold, Reserved Bytes Revision Checksum Bytes 0-62
ENTRY (VERSION) (-13E/-133) (-10E) (-13E/133) (-10E) (-13E/-133) (-10E) (-13E/-133) (-10E) REV. -13E -133 -10E MICRON
MT18LSDT1672G MT18LSDT3272G MT18LSDT6472G 01-11 Variable Data 01-09 Variable Data Variable Data Variable Data 01-0B Variable Data 01-09 Variable Data Variable Data Variable Data 01-0B Variable Data 01-09 Variable Data Variable Data Variable Data
65-71 73-90 95-98 99-125
NOTE:
Manufacturer's JEDEC Code Manufacturer's JEDEC Code (Cont.) Manufacturing Location Module Part Number (ASCII) Identification Code Identification Code (Continuted) Year Manufacture Week Manufacture Module Serial Number Manufacturer-Specific Data (Rsvd) Identification Code (Continuted) Year Manufacture
100/133
value tRAS used -13E module calculated from tRP. Actual device spec. value
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Figure 168-Pin DIMM Dimensions (Standard PCB)
FRONT VIEW
5.256 (133.50) 5.244 (133.20) .157 (4.00)
(2.00) (2X)
1.705 (43.31) 1.695 (43.05)
.118 (3.00) (2X) .118 (3.00) TYP.
.700 (17.78) TYP.
.250 (6.35) TYP. .118 (3.00) TYP.
.054 (1.37) .046 (1.17) .039 (1.00) R(2X) .040 (1.02) TYP. .050 (1.27) TYP.
4.550 (115.57)
BACK VIEW
.128 (3.25) (2X) .118 (3.00) 1.661 (42.18) 2.625 (66.68)
NOTE:
dimensions inches (millimeters)
typical where noted.
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Figure 168-Pin DIMM Dimensions (Low-Profile PCB)
FRONT VIEW
5.256 (133.50) 5.244 (133.20)
.320 (8.13)
1.206 (30.63) 1.194 (30.33) .700 (17.78)
(3.00) .250 (6.35) .118 (3.00)
4.550 (115.57)
.039 (1.00) R(2X)
.040 (1.02)
.050 (1.27)
.054 (1.37) .046 (1.17)
BACK VIEW
.128 (3.25) (2X) .118 (3.00) 1.661 (42.18)
2.625 (66.68)
NOTE:
dimensions inches (millimeters)
typical where noted.
Data Sheet Designation
Released Mark): This data sheet contains minimum maximum limits specified over complete power supply temperature range production devices. Although considered final, these specifications subject change, further product development data characterization sometimes occur.
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003, Micron Technology Inc.
128MB, 256MB, 512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, logo, Micron logo trademarks and/or service marks Micron Technology, Inc.
16,32,Meg SDRAM DIMMs (Footer Desc variable) SD18C16_32_64x72G_B.fm Rev. 1/03
©2003, Micron Technology Inc.
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