SYNCHRONOUS DRAM MODULE 168-pin, dual in-line memory module (DIMM
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512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
SYNCHRONOUS DRAM MODULE
168-pin, dual in-line memory module (DIMM) PC133- PC100-compliant Registered inputs with one-clock delay Utilizes SDRAM devices Phase-lock loop (PLL) clock driver reduce loading ECC-optimized pinout 512MB Single +3.3V ±0.3V power supply Fully synchronous; signals registered positive edge clock Internal pipelined operation; column address changed every clock cycle Internal SDRAM banks hiding access/ precharge Programmable burst lengths: full page Auto Precharge Auto Refresh Modes Self Refresh Mode 64ms refresh: 8,192 cycles LVTTL-compatible inputs outputs Serial Presence-Detect (SPD) Gold edge contacts
MARKING
MT18LSDF6472G 512MB
latest data sheet, please refer site: www.micron.com/datasheets
Figure 168-Pin DIMM (MO-161)
Standard 1.05in. (26.67mm)
Low-Profile 0.90in. (22.86mm)
Table
Address Table
512MB (BA0, BA1) (A0-A12) (A0-A9, A11) (S0#, S2#)
OPTIONS
Refresh Count Device Banks Device Configuration Addressing Column Addressing Module Ranks
Package 168-pin DIMM (Standard) 168-pin DIMM (Lead-free) Frequency/CAS Latency1 MHz/CL MHz/CL MHz/CL
NOTE:
-13E -133 -10E
Table
Part Numbers
CONFIGURATION SYSTEM SPEED
PART NUMBER MT18LSDF6472G-13E_ MT18LSDF6472G-133_ MT18LSDF6472G-10E_
NOTE:
Module latency; registered mode adds clock cycle
Table
Device Timing
PC100 tRCD 2-2-2 2-2-2 2-2-2 PC133 tRCD 2-2-2 3-3-3
MODULE MARKINGS -13E -133 -10E
designators component revision last characters each part number. Consult factory current revision codes. Example: MT18LSDF6472G-133B1.
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
©2003 Micron Technology, Inc.
PRODUCTS SPECIFICATIONS DISCUSSED HEREIN SUBJECT CHANGE MICRON WITHOUT NOTICE.
512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Assignment (168-Pin DIMM Front
DQMB0 DQMB1 DQMB2 DQMB3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Table
Assignment (168-Pin DIMM Back)
CKE0 DQMB6 DQMB7 CAS# DQMB4 DQMB5 RAS# DQ48 DQ49 DQ50 DQ51 DQ52 REGE DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SYMBOL SYMBOL SYMBOL SYMBOL DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
SYMBOL SYMBOL SYMBOL SYMBOL DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
Figure 168-Pin DIMM Layout
Standard 1.05in. (26.67mm)
Low-Profile 0.90in. (22.86mm)
PIN125
PIN125
Indicates VDDQ
Indicates
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512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table
PINS 111,
Descriptions
SYMBOL WE#, CAS#, RAS# CKE0 TYPE Input Input Input DESCRIPTION Command Inputs: WE#, CAS#, RAS# (along with define command being entered. Clock: distributed through on-board devices. Clock Enable: activates (HIGH) deactivates (LOW) signal. Deactivating clock provides POWER-DOWN SELF REFRESH operation (all device banks idle) CLOCK SUSPEND operation (burst access progress). synchronous except after device enters power-down self refresh modes, where becomes asynchronous until after exiting same mode. input buffers, including CKE, disabled during power-down self refresh modes, providing standby power. Chip Select: enables (registered LOW) disables (registered HIGH) command decoder. commands masked when registered HIGH. considered part command code. Input/Output Mask: DQMB input mask signal write accesses output enable signal read accesses. Input data masked when DQMB sampled HIGH during WRITE cycle. output buffers placed High-Z state (two-clock latency) when DQMB sampled HIGH during READ cycle. Bank Address: define which device bank ACTIVE, READ, WRITE, PRECHARGE command being applied. Address Inputs: Provide address ACTIVE commands, column address auto precharge (A10) READ/WRITE commands, select location memory array respective device bank. sampled during PRECHARGE command determines whether PRECHARGE applies device bank (A10 LOW, device bank selected BA0, BA1) device banks (A10 HIGH). address inputs also provide op-code during MODE REGISTER command. define which mode register (mode register extended mode register) loaded during LOAD MODE REGISTER command. Write Protect: Serial presence-detect hardware write protect. Serial Clock Presence-Detect: used synchronize presencedetect data transfer from module. Presence-Detect Address Inputs: These pins used configure presence-detect device. Register Enable. Data I/Os: Data
numbers listed correct order; more information, Assignment tables page
S0#,
Input
112, 113, 130,
DQMB0- DQMB7
Input
33-38, 117-121, 123,
BA0, A0-A12
Input Input
166, 167, 2-5, 7-11, 13-17, 55-58, 65-67, 69-82, 74-77, 86-89, 91-95, 97-101, 103, 104, 139-142, 144, 149-151, 153-156, 158-161 105, 106, 136,
SA0-SA2 REGE DQ0-DQ63
Input Input Input Input Input/ Output
CB0-CB7
Input/ Output Input/ Output
Check Bits. Serial Presence-Detect Data: bidirectional used transfer addresses data into data presence-detect portion module.
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
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512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table
PINS 102, 110, 124, 133, 143, 157, 107, 116, 127, 138, 148, 152, 108, 109, 114, 125, 129, 132, 134, 135, 145, 146, 163,
Descriptions
SYMBOL TYPE Supply DESCRIPTION Power Supply: +3.3V ±0.3V.
numbers listed correct order; more information, Assignment tables page
Supply
Ground.
Connected: These pins connected this module.
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Figure Functional Block Diagram
RS0# RDQMB0 RDQMB4 DQ32 DQ33 DQ34 DQ35
RDQMB1 DQ10 DQ11
DQ36 DQ37 DQ38 DQ39 RDQMB5
DQ40 DQ41 DQ41 DQ43
DQ12 DQ13 DQ14 DQ15
DQ44 DQ45 DQ46 DQ47
RS2# RDQMB2 DQ16 DQ17 DQ18 DQ19
RDQMB6 DQ48 DQ49 DQ50 DQ51
DQ20 DQ21 DQ22 DQ23 RDQMB3 DQ24 DQ25 DQ26 DQ27
DQ52 DQ53 DQ54 DQ55 RDQMB7
DQ56 DQ57 DQ58 DQ59
DQ28 DQ29 DQ30 DQ31
DQ60 DQ61 DQ62 DQ63
RAS# CAS# CKE0 A0-A12 S0#, DQMB0 DQMB7
RRAS#: SDRAMs RCAS#: SDRAMs RCKE0: SDRAMs RWE#: SDRAMs RA0-RA12: SDRAMs RBA0: SDRAMs RBA1: SDRAMs RS0#, RS2# RDQMB0 RDQMB7 CK1-CK3
12pF
SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM REGISTER
SDRAMs SDRAMs
12pF
NOTE: resistor values unless otherwise specified.
SDRAM MT48LC64M4A2FB
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
General Description
MT18LSDF6472G high-speed CMOS, dynamic random-access, 512MB memory module organized (ECC) configuration. This module uses internally configured quad-bank SDRAMs with synchronous interface (all signals registered positive edge clock signal). Read write accesses SDRAM modules burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed (BA0, select device bank; A0-A12 select device row). address bits registered coincident with READ WRITE command used select starting device column location burst access. SDRAM modules provide programmable read write burst lengths locations, full page, with burst terminate option. auto precharge function enabled provide self-timed precharge that initiated burst sequence. SDRAM modules internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows device column address changed every clock cycle achieve high-speed, fully random access. Precharging device bank while accessing other three device banks will hide PRECHARGE cycles provide seamless, high-speed, random-access operation. SDRAM modules designed operate +3.3V ±0.3V, low-power memory systems. auto refresh mode provided, along with power-saving, powerdown mode. inputs outputs LVTTL-compatible. SDRAM modules offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with automatic column-address generation, ability interleave between device banks order hide precharge time, capability randomly change device column addresses each clock cycle during burst access. more information regarding SDRAM operation, refer 256Mb SDRAM component data sheet.
Register Operation
This module operated either registered mode (REGE HIGH), where control/address input signals latched register rising clock edge sent SDRAM devices following rising clock edge (data access delayed clock), buffered mode (REGE LOW) where input signals pass through register/buffer SDRAM devices same clock. phase-lock loop (PLL) modules used redrive clock signals SDRAM devices minimize system clock loading (CK0 connected PLL, CK1, CK2, terminated).
Serial Presence-Detect Operation
This module incorporates serial presence-detect (SPD). function implemented using 2,048-bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters. remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals, together with (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) tied ground module, permanently disabling hardware write protect.
Device Description
general, 256Mb SDRAM component device used this modules quad-bank DRAM, that operate 3.3V include synchronous interface (all signals registered positive edge clock signal, CK0). four banks 256Mb device each configured 8,192 bit-rows, 2,048 bit-columns, input/output bits.
Module Functional Description
Module read write accesses burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed. select device bank, A0-A12, select device row.
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
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512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
address bits A0-A9, registered coincident with READ WRITE command, used select starting device column location burst access. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions device operation. fied time before initiating subsequent operation. Violating either these requirements will result unspecified operation.
Burst Length
Read write accesses SDRAM burst oriented, with burst length being programmable, shown Figure Mode Register Definition Diagram. burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. full-page burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. Once power applied VDDQ (simultaneously) clock stable (stable clock defined signal cycling within timing constraints specified clock pin), SDRAM requires 100µs delay prior issuing command other than COMMAND INHIBIT Starting some point during this 100µs period continuing least through this period, Command Inhibit commands should applied. Once 100µs delay been satisfied with least Command Inhibit command having been applied, PRECHARGE command should applied. device banks must then precharged, thereby placing device banks idle state. Once idle state, AUTO refresh cycles must performed. After AUTO refresh cycles complete, SDRAM ready mode register programming. Because mode register will power unknown state, should loaded prior applying operational command.
Figure Mode Register Definition Diagram
Address
Mode Register (Mx)
Reserved* Reserved*
Mode
Latency
Burst Length
*Should program M12, M11, ensure compatibility with future devices. Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Mode Register Definition
mode register used define specific mode operation SDRAM device. This definition includes selection burst length, burst type, latency, operating mode write burst mode, shown Mode Register Definition Diagram. mode register programmed LOAD MODE REGISTER command will retain stored information until programmed again device loses power. Mode register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), M4-M6 specify latency, specify operating mode, specifies write burst mode, reserved future use. (M12) undefined, should driven during loading mode register. mode register must loaded when device banks idle, controller must wait speci09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved
M6-M0 Defined
Operating Mode Standard Operation other states reserved
Write Burst Mode Programmed Burst Length Single Location Access
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512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Burst Definition Table
STARTING COLUMN ADDRESS ORDER ACCESSES WITHIN BURST TYPE SEQUENTIAL 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn+1, Cn+2 Cn+3, Cn+4. .Cn-1, TYPE INTERLEAVED 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Supported
BURST LENGTH
Full Page A0-A9 (location 0-y)
NOTE:
Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached, shown Figure Burst Definition Table. block uniquely selected A1-A9, when burst length two; when burst length four; when burst length eight. remaining (least significant) address bit(s) (are) used select starting location within block. Fullpage bursts wrap within page boundary reached, shown Figure Burst Definition Table.
Burst Type
Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Figure Burst Definition Table.
Latency
latency delay, clock cycles, between registration READ command availability first piece output data. latency three clocks. READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, read command registered latency programmed clocks, will start driving after data will valid shown Figure Latency Diagram. Table Latency Table, indicates operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result.
full-page accesses: 2,048. burst length two, A1-A9, select blockof-two burst; selects starting column within block. burst length four,A2-A9, select blockof-four burst; A0-A1 select starting column within block. burst length eight, A3-A9, select blockof-eight burst; A0-A2 select starting column within block. full-page burst, full selected A0-A9, select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-A9, select unique column accessed, mode register ignored.
Operating Mode
normal operating mode selected setting zero; other combinations values reserved future and/or test
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
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512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
modes. programmed burst length applies both read write bursts. Test modes reserved states should used because unknown operation incompatibility with future versions result.
Figure Latency Diagram
COMMAND
READ
DOUT
Write Burst Mode
When burst length programmed applies both read write bursts; when programmed burst length applies read bursts, write accesses single-location (nonburst) accesses.
Latency
Table
Latency Table
COMMAND READ DOUT Latency DON'T CARE UNDEFINED
Registered mode adds clock cycle ALLOWABLE OPERATING CLOCK FREQUENCY (MHz) SPEED -13E -133 -10E LATENCY LATENCY
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
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512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Commands
Table SDRAM Commands DQMB Operation Truth Table, provides quick reference available commands. This followed written description each command. more detailed description commands operations, refer 256Mb SDRAM component data sheet.
Table
SDRAM Commands DQMB Operation Truth Table
RAS# CAS# DQMB ADDR Bank/ Bank/Col Bank/Col Code Op-code Valid Active Active High-Z NOTES
HIGH commands shown except SELF REFRESH NAME (FUNCTION) COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z
NOTE:
A0-A12 provide address; BA0-BA1 determine which device bank made active. A0-A9, provide column address; HIGH enables auto-precharge feature (nonpersistent), while disables auto-precharge feature; BA0-BA1 determine which device bank being read from written LOW: BA0-BA1 determine which device bank being precharged. HIGH: device banks precharged BA0, "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. A0-A11 define op-code written mode register should driven LOW. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Absolute Maximum Ratings
Stresses greater than those listed cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operaVoltage VDD, VDDQ Supply Relative +4.6V Voltage Inputs Pins Relative +4.6V Operating Temperature (Commercial) +55°C tional sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Storage Temperature (plastic) -55°C +150°C Power Dissipation
Table Electrical Characteristics Operating Conditions
Notes: notes appear page VDD, VDDQ +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input (All other pins under test SYMBOL VDD, VDDQ -0.3 UNITS NOTES
Command Address Inputs, DQMB OUTPUT LEAKAGE CURRENT: pins disabled; VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA)
Table Specifications Conditions
Notes: notes appear page VDD, VDDQ +3.3V ±0.3V; SDRAM component values only PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device device banks idle; STANDBY CURRENT: Active Mode;CKE HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active AUTO REFRESH CURRENT tRFC (MIN) HIGH; HIGH SELF REFRESH CURRENT: 0.2V
SYMBOL
IDD1
-13E
-133
-10E
UNITS
NOTES
2,430 2,250 2,250
IDD2 IDD3 IDD4 IDD5 IDD6 IDD7
2,430 2,430 2,430 5,130 4,860 4,860
7.8125µs
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
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512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Capacitance
Note notes appear page PARAMETER Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, WE#, Input Capacitance: DQMB Input Capacitance: Input Capacitance: SCL, Input Capacitance: Input Capacitance: REGE Input/Output Capacitance: SYMBOL UNITS
Table Electrical Characteristics Recommended Operating Conditions
Notes: notes appear page Module timing parameters comply with PC100 PC133 Design Specs, based component parameters ACCHARACTERISTICS PARAMETER Access timefrom (pos.edge) Address hold time Address setup time high-level width low-level width Clock cycle time holdt setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time (noload) ACTIVE PRECHARGE command ACTIVE ACTIVE command period ACTIVE READ WRITE delay Refresh period (8,192 rows) AUTOREFRESH period PRECHARGE command period
-13E SYMBOL
-133 120,000
-10E UNITS 120,000 NOTES
AC(3) AC(2)
120,000
CK(3) CK(2)
HZ(3) HZ(2)
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512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Electrical Characteristics Recommended Operating Conditions (Continued)
Notes: notes appear page ACCHARACTERISTICS PARAMETER ACTIVE bank ACTIVE bank command Transition time WRITE recovery time SYMBOL
-13E
-133
-10E UNITS NOTES
7.5ns
Exit SELFREFRESH ACTIVE command
Table Functional Characteristics
Notes: notes appear page PARAMETER READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVE command Data-in PRECHARGE command Last data-in burst STOP command Last data-in READ/WRITE command Last data-in PRECHARGE command LOAD MODE REGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command
SYMBOL
-13E
-133
-10E
UNITS
NOTES
CKED
ROH(3) ROH(2)
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
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512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Notes
voltages referenced VSS. This parameter sampled. VDD, VDDQ +3.3V; MHz; 25°C; under test biased 1.4V. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range ensured (0°C +55°C). initial pause 100µs required after powerup, followed AUTO REFRESH commands, before proper device operation ensured. (VDD VDDQ must powered simultaneously. VSSQ must same potential.) AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load:
50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have with timing referenced 1.5V crossover point. input transition time longer than 1ns, then timing referenced (MAX) (MIN) longer crossover point. Other input signals allowed transition more than once every clocks otherwise valid levels. specifications tested after device properly initialized. Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate. Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate.
Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will increase decrease proportionally according amount frequency alteration test condition. Address transitions average transition every clocks. must toggled minimum times during this period. Based 10ns -10E; 7.5ns -133 -13E. overshoot: (MAX) VDDQ pulse width 3ns, pulse width cannot greater than third cycle rate. undershoot: (MIN) pulse width 3ns. clock frequency must remain constant (stable clock defined signal cycling within timing constraints specified clock pin) during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. precharge timing budget (tRP) begins -13E; 7.5ns -133; -10E after first clock delay, after last WRITE executed. exceed limit precharge mode. Precharge mode only. JEDEC PC100 specify three clocks. -133/-13E with load 4.6ns guaranteed design. Parameter guaranteed design. -13E, 7.5ns; -133, 7.5ns; -10E, 10ns HIGH during refresh command period (MIN) else LOW. IDD6 limit actually nominal value does result fail value. Refer device data sheet timing waveforms. value tRAS used -13E speed grade modules calculated from Leakage number reflects worst case leakage possible through module pin, what each memory device contributes.
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
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512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Clock Data Conventions
Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions shown Figure Data Validity, Figure Definition Start Stop).
Acknowledge
Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data shown Figure Acknowledge Response From Receiver). device will always respond with acknowledge after recognition start condition slave address. both device WRITE operation have been selected, device will respond with acknowledge after receipt each subsequent eight word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
Start Condition
commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met.
Stop Condition
communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode.
Figure Data Validity
Figure Definition Start Stop
DATA STABLE DATA CHANGE DATA STABLE
START
STOP
Figure Acknowledge Response From Receiver
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
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512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table EEPROM Device Select Code
most significant (b7) sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code DEVICE TYPE IDENTIFIER CHIP ENABLE
Table EEPROM Operating Modes
MODE Current Address Read Random Address Read Sequential Read Byte Write Page Write BYTES INITIAL SEQUENCE Start, Device Select, Start, Device Select, Address RESTART, Device Select, Similar Current Random Address Read START, Device Select, START, Device Select,
Figure EEPROM Timing Diagram
HIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
UNDEFINED
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
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512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Serial Presence-Detect EEPROM Operating Conditions
+3.3V ±0.3V; voltages referenced PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs POWER SUPPLY CURRENT: SYMBOL ICCS Write Read UNITS
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; VDDSPD +3.3V ±0.3V PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time
NOTE:
SYMBOL HD:DAT HD:STA HIGH SU:DAT SU:STA SU:STO
UNITS
NOTES
avoid spurious START STOP conditions, minimum delay placed between falling rising edge SDA. This parameter sampled. reSTART condition, following WRITE cycle. EEPROM WRITE cycle time (tWRC) time from valid stop condition write sequence EEPROM internal erase/program cycle. During WRITE cycle, EEPROM interface circuit disabled, remains HIGH pull-up resistor, EEPROM does respond slave address.
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Serial Presence-Detect Matrix
"1"/"0": Serial data, "driven HIGH"/"driven LOW"; +3.3V ±0.3V BYTE DESCRIPTION Number Bytes Used Micron Total Number Memory Bytes Memory Type Number Addresses Number Column Addresses Number Module Ranks Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, (CAS Latency ENTRY (VERSION) SDRAM LVTTL (-13E) (-133) (-10E) (-13E/-133) (-10E) 7.81µs/SELF PAGE -10E, -133, -13E (-13E) (-133/-10E) (-13E) (-133/-10E) (-13E) (-133/-10E) (-13E) (-133) (-10E) (-13E) (-133/-10E) (-13E) (-133) (-10E) 512MB (-13E/-133) (-10E) MT18LSDF6472G
SDRAM Access from CLK, (CAS Latency Module Configuration Type Refresh Rate/Type SDRAM Width (Primary SDRAM) Error-checking SDRAM Data Width Minimum Clock Delay from Back-to-Back Random Column Addresses,tCCD Burst Lengths Supported Number Banks SDRAM Device Latencies Supported Latency Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, (CAS Latency SDRAM Access from CLK, (CAS Latency SDRAM Cycle Time, (CAS Latency SDRAM Access from CLK, (CAS Latency Minimum Precharge Time, Minimum Active Active, tRRD
Minimum RAS# CAS# Delay, tRCD Minimum RAS# Pulse Width, tRAS (See note
Module Rank Density Command Address Setup Time, tAS, tCMS
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Table Serial Presence-Detect Matrix (Continued)
"1"/"0": Serial data, "driven HIGH"/"driven LOW"; +3.3V ±0.3V BYTE 36-61 DESCRIPTION Command Address Hold Time, tAH, tCMH Data Signal Input Setup Time, Data Signal Input Hold Time, Reserved Revision Checksum Bytes 0-62 ENTRY (VERSION) (-13E/-133) (-10E) (-13E/-133) (-10E) (-13E/-133) (-10E) REV. -13E -133 -10E MICRON MT18LSDF6472G Variable Data 01-09 Variable Data Variable Data Variable Data
65-71 73-90 95-98 99-125
NOTE:
Manufacturer's JEDEC Code Manufacturer's JEDEC Code (Cont.) Manufacturing Location Module Part Number (ASCII) Identification Code Identification Code (Cont.) Year Manufacture Week Manufacture Module Serial Number Manufacturer-Specific Data (RSVD) System Frequency SDRAM Component Clock Detail
(-13E/ -133/-10E)
value tRAS used -13E modules calculated from tRP. Actual device specification value 37ns.
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Figure Standard 168-Pin DIMM Dimensions
FRONT VIEW
5.256 (133.50) 5.244 (133.20) 0.157 (3.99)
0.079 (2.00) (2X)
1.056 (26.82) 1.044 (26.52) 0.118 (3.00) (2X) 0.18 (3.00) 0.250 (6.35) 0.118 (3.00)
0.700 (17.78)
4.550 (115.57)
0.039 (1.00) R(2X)
0.040 (1.02)
0.050 (1.27)
0.054 (1.37) 0.046 (1.17)
BACK VIEW
0.128 (3.25) (2X) 0.118 (3.00) 1.661 (42.18)
2.625 (66.68)
NOTE:
dimensions inches (millimeters); typical where noted.
09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03
Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology, Inc.
512MB (x72, ECC) 168-PIN REGISTERED SDRAM DIMM
Figure Low-Profile 168-Pin DIMM Dimensions
FRONT VIEW
5.256 (133.50) 5.244 (133.20) 0.079 (2.00) (2X)
0.157 (3.99)
0.118 (3.00) (2X) 0.118 (3.00) 0.250 (6.35) 0.118 (3.00)
0.700 (17.78)
0.906 (23.01) 0.894(22.71)
4.550 (115.57)
0.039 (1.00) R(2X)
0.040 (1.02)
0.050 (1.27)
0.054 (1.37) 0.046 (1.17)
BACK VIEW
0.128 (3.25) (2X) 0.118 (3.00) 1.661 (42.18)
2.625 (66.68)
NOTE:
dimensions inches (millimeters); typical where noted.
Data Sheet Designation
Released Mark): This data sheet contains minimum maximum limits specified over complete power supply temperature range production devices. Although considered final, these specifications subject change, further product development data characterization sometimes occur.
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09005aef80d04a5a SDF18C64x72G_C.fm Rev. 8/03 Micron Technology, Inc., reserves right change products specifications without notice. ©2003 Micron Technology,
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