'03.07.15 wire interface Real-Time Clock with Battery Backup swit

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OUTLINE
'03.07.15
wire interface Real-Time Clock with Battery Backup switch-over Function
R2061 Series
R2061 CMOS real-time clock connected three signal lines, SCLK, SIO, configured perform serial transmission time calendar data CPU. Further, battery backup switchover circuit voltage detector. periodic interrupt circuit configured generate interrupt signals with selectable interrupts ranging from seconds month. alarm interrupt circuits generate interrupt signals preset times. oscillation circuit driven under constant voltage, fluctuation oscillator frequency supply voltage small, time keeping current small (TYP. 0.4µA 3V). oscillation halt sensing circuit used judge validity internal data such events power-on; supply voltage monitoring circuit configured record drop supply voltage below selectable supply voltage monitoring threshold settings. oscillation adjustment circuit intended adjust time counts with high precision correcting deviations oscillation frequency crystal oscillator. Battery backup switchover function automatic switchover circuit between main power supply backup battery primary secondary battery. Switchover executed monitoring voltage main power supply, therefore voltage backup battery voltage relevant. This model comes ultra-compact FFP12 (Height 1.00mm,
FEATURES
Minimum Timekeeping supply voltage Typ. 0.75V (Max. 1.00V); power consumption 0.4µA (1.0µA MAX.) VDD=3V Built-in Backup switchover circuit (can used primary battery, secondary battery, electric double layer capacitor) Three signal lines (CE, SCLK, SIO) required connection CPU. (Maximum clock frequency 1MHz (with Time counters (counting hours, minutes, seconds) calendar counters (counting years, months, days, weeks) format) Interrupt circuit configured generate interrupt signals (with interrupts ranging from seconds month) provided with interrupt flag interrupt halt alarm interrupt circuits (Alarm_W week, hour, minute alarm settings Alarm_D hour minute alarm settings) Built-in voltage detector with delay With Power-on flag prove that power supply starts from Supply voltage monitoring circuit with supply voltage monitoring threshold settings Automatic identification leap years year 2099 Selectable 12-hour 24-hour mode settings Built-in oscillation stabilization capacitors High precision oscillation adjustment circuit CMOS process Ultra-compact FFP12
CONFIGURATION
R2061K(FFP12)
OSCOUT
OSCIN
/INTR
VIEW
/VDCC
SCLK
Rev.1.03
R2061 Series BLOCK DIAGRAM
POWER SUPPLY BATTERY VOLTAGE MONITOR VOLTAGE DETECTOR /VDCC DELAY OSCIN REAL TIME CLOCK
SCLK /INTR
LEVEL SHIFTER
OSCOUT
VOLTAGE REFERENCE
SELECTION GUIDE
R2061xxx Series, output voltage options designated. Part Number designated follows: R2061K01-E2 Part Number R2061abb-cc Code Description Designation package. FFP12 SSOP16 Serial number Voltage detector setting etc. Designation taping type. Only available.
Rev.1.03
R2061 Series DESCRIPTION
Symbol Item Chip enable Input Description used interfacing with CPU. Should held high allow access CPU. Incorporates pull-down resistor. Should held open when powered off. Allows maximum input voltage volts regardless supply voltage. SCLK used input clock pulses synchronizing input output data from pin. Allows maximum input voltage volts regardless supply voltage. used input output data intended writing reading synchronization with SCLK pin. /INTR used output alarm interrupt (Alarm_W) alarm interrupt (Alarm_D) output periodic interrupt signals signals. Disabled power-on from Nch. open drain output. Supply power Connect primary battery backup. Normally, power supplied from level equal less than -VDET1, power supplied from this pin. OSCIN OSCOUT pins used connect 32.768-kHz crystal oscillator (with other oscillation circuit components built into R2061K series). connected power supply. Connect capacitor much 0.1µF between VSS. case using secondary battery, connecting secondary battery this possible. While monitoring Power supply, voltage equal lower than -VDET1, this output level "L". When /VDCC becomes "L", turns turns result, power supplied from internal real time clock. When equal +VDET1 more, turns turns off. After DELAY passed, /VDCC output becomes off, "H". Open-drain output. stabilize internal reference, connect capacitor much 0.1uF between this VSS. grounded.
SCLK
Serial Clock Input Serial Input Output Interrupt Output Main Battery input Power Supply Input Backup Battery Oscillation Circuit Input Output Positive Power Supply Input
/INTR
OSCIN OSCOUT
/VDCC
Power Supply Monitoring Result Output
Noise Bypass Negative Power Supply Input
Rev.1.03
R2061 Series ABSOLUTE MAXIMUM RATINGS
(VSS=0V) Symbol Item Name Supply Voltage Supply Voltage Supply Voltage Input Voltage SCLK Input Voltage Input Voltage Output Voltage /INTR, /VDCC Output Voltage IOUT Maximum Output Current Power Dissipation Topt 25°C Topt Operating Temperature Tstg Storage Temperature Description -0.3 +6.5 -0.3 +6.5 -0.3 +6.5 -0.3 +6.5 -0.3 VCC+0.3 -0.3 VDD+0.3 -0.3 +6.5 -0.3 VCC+0.3 +125 Unit
RECOMMENDED OPERATING CONDITIONS
Symbol Vaccess Item Supply Voltage Name power supply voltage interfacing with (VSS=0V, Topt=-40 +85°C) Min, Typ. Max. Unit -VDET1
VCLK
Minimum Timekeeping 0.75 1.00 Voltage CGout,CDout=0pF *2), Oscillation Frequency 32.768 VPUP Pull-up Voltage /INTR, /VDCC -VDET1 Vaccess specification guaranteed design. CGout connected between OSCIN VSS, CDout connected between OSCOUT VSS. R2061 series incorporates capacitors between OSCIN VSS, between OSCOUT VSS. Then normally, CGout CDout necessary. Crystal oscillator: CL=6-8pF, R1=30K
Rev.1.03
R2061 Series ELECTRICAL CHARACTERISTICS (PRELIMINARY)
R2061K01 (Unless otherwise specified: VSS=0V,VSB=3.0V, VCC=2.0V, 0.1uF between VSS, VSS, Topt=-40 +85°C) Symbol Item Name Conditions Min. Typ. Max. Unit VIH1 Input Voltage SCLK 0.8x VIH2 Input Voltage 0.8x VCC+ Input Voltage SCLK -0.3 0.2x Output VOH=VCC-0.5V -0.5 Current VOL=0.4V IOL1 Output Current IOL2 Output Current /INTR IOL3 Output Current /VDCC VDD,VSB,VCC=1.4V VOL=0.4V Input Leakage SCLK VI=5.5V -1.0 Current RDNCE Pull-down Input register IOZ1 Output Off-state VO=5.5V -1.0 Current IOZ2 Output Off-state /INTR, VO=5.5V -1.0 Current /VDCC Time Keeping Current VCC=0V, VSB=3.0V, Backup mode VDD, Output=OPEN ISBL Leakage Current VCC=3.0V, -1.0 Backup VSB=5.5V VCC_on VDD, Output=OPEN 1.90 2.10 2.30 VDETH Supply Voltage Topt=25°C Monitoring Voltage 1.20 1.35 1.50 VDETL Supply Voltage Topt=25°C Monitoring Voltage 1.657 1.700 1.743 -VDET1 Detector Threshold Topt=25°C Voltage (falling edge VCC) 1.731 1.785 1.839 +VDET1 Detector Released Topt=25°C Voltage (rising edge VCC) Detector Threshold VCC, VDET ±100 Topt=-40 85°C Released Voltage Topt Temperature coefficient VCCV Output Topt=25°C, VCC=2.0V, VCC0.12 0.04 OUT1 Voltage Iout=0.5mA VSBV Output Topt=25°C, VCC=1.4V, VSB0.08 0.02 OUT2 Voltage VSB=3.0V, Iout=0.1mA Internal Oscillation OSCIN Capacitance Internal Oscillation OSCOUT Capacitance
Guaranteed design.
Rev.1.03
R2061 Series ELECTRICAL CHARACTERISTICS
Unless otherwise specified: VSS=0V,Topt=-40 +85°C Input Output Conditions: CondiUnit Item VDD1.7V Tions Min. Typ. Max. -bol tCES Set-up Time tCEH Hold Time Recovery Time fSCLK SCLK Clock Frequency tCKH SCLK Clock Time tCKL SCLK Clock Time tCKS SCLK Set-up Time Data Output Delay Time Data Output Floating Time tCEZ Data Output Delay Time After Falling Input Data Set-up Time Input Data Hold Time Time tDELAY Output Delay Time Keeping Voltage Detector voltage interfacing with defined Vaccess (P.4 sRECOMMENDED OPERATING CONDITIONS) reading/writing timing, "P.24 sInterfacing with qConsiderations Reading Writing Time Data under special condition".
tCKH
tCKL tCEH
tCES
SCLK SIO(IN) SIO(OUT)
tCEZ
+VDET1 tDELAY
/VDCC
Rev.1.03
R2061 Series PACKAGE DIMENSIONS
R2061Kxx
1PIN INDEX
0.05
2PIN INDEX 0.35 0.35 0.25 1.0Max
0.103
0.3±0.15
0.2±0.15
(BOTTOM VIEW) 0.17±0.1 0.27±0.15 2.0±0.1
TAPING SPECIFICATION R2061 Series have designated taping direction. product designation taping components "R2061S/Kxx-E2".
2.0±0.1
Rev.1.03
R2061 Series GENERAL DESCRIPTION
Battery Backup Switchover Function R2061 Series have power supply input, VSB. With monitoring input voltage, which voltage between supplied internal power supply decided. Refer next table state backup battery internal power supply's state each condition. VCCVDET1 VCC<VDET1 VCCRTC, VSBRTC, /VDCC=OFF(H) /VDCC=L backup battery, only primary battery such CR2025, LR44, secondary battery such ML614, TC616, also electric double layered capacitor aluminum capacitor used. Switchover point judged with voltage main power (VCC), therefore, backup voltage higher than main supply voltage, switchover realized without extra load backup power supply. case back-up primary battery
case back-up capacitor secondary battery (Charging voltage equal power supply voltage)
case back-up capacitor secondary battery (Charging voltage equal power supply voltage)
Power Supply
power supply
power supply (3V)
0.1µF
Double layer capacitor etc.
CR2025 etc.
ML614 etc.
Interface with R2061 connected three signal lines (Chip Enable), SCLK (Serial Clock), (Serial Input Output), through which reads writes data from CPU. accessed when held high. Access clock pulses have maximum frequency MHz, allowing high-speed data transfer CPU. falls down under -VDET1, R2061 stops accessing with CPU. Clock Calendar Function R2061 reads writes time data from units ranging from seconds last digits calendar year. calendar year will automatically identified leap year when last digits multiple Consequently, leap years year 2099 automatically identified such. year 2000 leap year while year 2100 leap year.
Rev.1.03
R2061 Series
Alarm Function R2061 incorporates alarm interrupt circuit configured generate interrupt signals preset times. alarm interrupt circuit allows types alarm settings specified Alarm_W registers Alarm_D registers. Alarm_W registers allow week, hour, minute alarm settings including combinations multiple day-of-week settings such "Monday, Wednesday, Friday" "Saturday Sunday". Alarm_D registers allow hour minute alarm settings. Alarm_W outputs from /INTR pin, Alarm_D outputs also from /INTR pin. Each alarm function checked from using polling function. High-precision Oscillation Adjustment Function R2061 built-in oscillation stabilization capacitors CD), that connected external crystal oscillator configure oscillation circuit. kinds accuracy this function alternatives. correct deviations oscillator frequency crystal, oscillation adjustment circuit configured allow correction time count gain loss ±1.5ppm ±0.5ppm 25°C) from CPU. maximum range approximately ±189ppm ±63ppm) increments approximately 3ppm 1ppm). Such oscillation frequency adjustment each system following advantages: Allows timekeeping with much higher precision than conventional RTCs while using crystal oscillator with wide range precision variations. Corrects seasonal frequency deviations through seasonal oscillation adjustment. Allows timekeeping with higher precision particularly with temperature sensing function RTC, through oscillation adjustment tune with temperature fluctuations. Power-on Reset, Oscillation Halt Sensing Function Supply Voltage Monitoring Function R2061 power supply pins (VCC, VSB, VDD), among them, have monitoring function supply voltage. power supply monitoring circuit makes /VDCC when power supply becomes equal lower than -VDET1. power-on VDD, this circuit makes /VDCC turn off, after delay time, tDELAY from when power supply becomes equal more than +VDET1. R2061 incorporates oscillation halt sensing circuit equipped with internal registers configured record past oscillation halt, oscillation halt sensing circuit, monitoring flag, power-on reset flag useful judging validity time data. Power reset function reset control resisters when system powered from same time, fact memorized resister flag, thereby identifying whether they powered from battery backed-up. R2061 also incorporates supply voltage monitoring circuit equipped with internal registers configured record drop supply voltage below certain threshold value. Supply voltage monitoring threshold settings selected between 2.1V 1.35V through internal register settings. sampling rate normally oscillation halt sensing circuit configured confirm established invalidation time data contrast supply voltage monitoring circuit intended confirm potential invalidation time data. Further, supply voltage monitoring circuit applied battery supply voltage monitoring.
Periodic Interrupt Function R2061 incorporates periodic interrupt circuit configured generate periodic interrupt signals aside from interrupt signals generated periodic interrupt circuit output from /INTR pin. Periodic interrupt signals have five selectable frequency settings (once seconds), (once second), 1/60 (once minute), 1/3600 (once hour), monthly (the first every month). Further, periodic interrupt signals also have selectable waveforms, normal pulse form (with frequency special form adapted interruption from level mode (with second, minute, hour, month interrupts). condition periodic interrupt signals monitored with using polling function.
Rev.1.03
R2061 Series Address Mapping
Address A3A2A1A0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Register Name Second Counter Minute Counter Hour Counter Day-of-week Counter Day-of-month Counter Month Counter Century Year Counter Oscillation Adjustment Register Alarm_W (Minute Register) Alarm_W (Hour Register) Alarm_W (Day-of-week Register) Alarm_D (Minute Register) Alarm_D (Hour Register) Control Register Control Register /1920 Data MO10 WM40 WM20 WH20 WM10
1011 1100 1101 1110 1111
WALE VDSL
DM40 DALE VDET
DM20 DH20 DP/A /1224 /XST
DM10 DH10 SCRA TCH2
TEST
SCRA TCH1
CTFG WAFG
Notes: data listed above accept both reading writing. data marked with invalid writing reset reading. When Control Register bits reset Oscillation Adjustment Register, Control Register Control Register excluding /XST bit. When DEV=0, oscillation adjustment circuit configured allow correction time count gain loss ±1.5ppm. When DEV=1, oscillation adjustment circuit configured allow correction time count gain loss ±0.5ppm. power-on-reset flag.
Rev.1.03
R2061 Series Register Settings
Control Register (ADDRESS WALE DALE SCRA TEST (For Writing) /1224 TCH2 WALE DALE SCRA TEST (For Reading) /1224 TCH2 Default Settings Default settings: Default value means read written values when power-on from volts. WALE, DALE Alarm_W Enable Bit, Alarm_D Enable WALE,DALE Description Disabling alarm interrupt circuit (under control settings Alarm_W registers Alarm_D registers). Enabling alarm interrupt circuit (under control settings Alarm_W registers Alarm_D registers)
(Default)
/12-24-hour Mode Selection /1224 Description /1224 Selecting 12-hour mode with a.m. p.m. indications. (Default) Selecting 24-hour mode Setting /1224 specifies 12-hour mode 24-hour mode, respectively. 24-hour mode 12-hour mode 24-hour mode (AM12) (AM10) (AM11) Setting /1224 should precede writing time data 12-hour mode (PM12) (PM10) (PM11)
SCRATCH2 Scratch SCRATCH2 Description (Default) SCRATCH2 intended scratching accepts reading writing SCRATCH2 will when Control Register TEST Test TEST Description Normal operation mode. Test mode. TEST used only testing factory should normally
(Default)
Rev.1.03
R2061 Series
CT2,CT1, Periodic Interrupt Selection Bits Description Wave form Interrupt Cycle Falling Timing mode OFF(H) Fixed Pulse Mode 2Hz(Duty50%) Pulse Mode 1Hz(Duty50%) Level Mode Once second (Synchronized with second counter increment) Level Mode Once minute seconds every minute) Level Mode Once hour minutes seconds every hour) Level Mode Once month hours, minutes, seconds first every month)
(Default)
Pulse Mode: 2-Hz 1-Hz clock pulses output synchronization with increment second counter illustrated timing chart below.
CTFG /INTR Approx. 92µs (Increment second counter) Rewriting second counter
pulse mode, increment second counter delayed approximately from falling edge clock pulses. Consequently, time readings immediately after falling edge clock pulses appear behind time counts real-time clocks approximately second. Rewriting second counter will reset other time counters less than second, driving /INTR low. Level Mode: Periodic interrupt signals output with selectable interrupt cycle settings second, minute, hour, month. increment second counter synchronized with falling edge periodic interrupt signals. example, periodic interrupt signals with interrupt cycle setting second output synchronization with increment second counter illustrated timing chart below.
CTFG /INTR Setting CTFG (Increment second counter) (Increment second counter) Setting CTFG (Increment second counter)
*1), When oscillation adjustment circuit used, interrupt cycle will fluctuate once 20sec. 60sec. follows: Pulse Mode: period output pulses will increment decrement maximum ±3.784 example, 1-Hz clock pulses will have duty cycle ±0.3784%. Level Mode: periodic interrupt cycle second will increment decrement maximum ±3.784
Rev.1.03
R2061 Series
SCRA CTFG WAFG DAFG (For Writing) TCH1 VDSL VDET /XST SCRA CTFG WAFG DAFG (For Reading) TCH1 Indefinite Default Settings Default settings: Default value means read written values when power-on from volts. VDSL VDSL Supply Voltage Monitoring Threshold Selection Description Selecting supply voltage monitoring threshold setting 2.1v. Selecting supply voltage monitoring threshold setting 1.35v. VDSL intended select supply voltage monitoring threshold settings.
Control Register (Address VDSL VDET /XST
(Default)
VDET VDET
Supply Voltage Monitoring Result Indication Description Indicating supply voltage above supply voltage monitoring (Default) threshold settings. Indicating supply voltage below supply voltage monitoring threshold settings. Once VDET supply voltage monitoring circuit will disabled while VDET will hold setting VDET accepts only writing which restarts supply voltage monitoring circuit. Conversely, setting VDET causes event.
/XST Oscillation Halt Sensing Monitor /XST Description Sensing halt oscillation Sensing normal condition oscillation /XST accepts reading writing /XST will when oscillation halt sensing. /XST will hold even after restart oscillation. Power-on-reset Flag Description Normal condition Detecting power-on -reset sensing power-on reset condition.
(Default)
will when power-on from volts. will hold setting even after power-on. When bits will reset Oscillation Adjustment Register, Control Register Control Register except /XST PON. result, /INTR stops outputting. accepts only writing Conversely, setting causes event.
SCRATCH1 Scratch SCRATCH1 Description (Default) SCRATCH1 intended scratching accepts reading writing SCRATCH1 will when Control Register
Rev.1.03
R2061 Series
CTFG Periodic Interrupt Flag CTFG Description Periodic interrupt output (Default) Periodic interrupt output CTFG when periodic interrupt signals output from /INTR ("L"). CTFG accepts only writing level mode, which disables ("H") /INTR until enabled ("L") again next interrupt cycle. Conversely, setting CTFG causes event. WAFG,DAFG Alarm_W Flag Alarm_D Flag WAFG,DAFG Description Indicating mismatch between current time preset alarm time (Default) Indicating match between current time preset alarm time WAFG DAFG bits valid only when WALE DALE have setting which caused approximately 61µs after match between current time preset alarm time specified Alarm_W registers Alarm_D registers. WAFG (DAFG) accepts only writing /INTR outputs ("H") when this /INTR outputs again next preset alarm time. Conversely, setting WAFG DAFG bits causes event. WAFG DAFG bits will have reading when alarm interrupt circuit disabled with WALE DALE bits settings WAFG DAFG bits synchronized with output /INTR shown timing chart below.
Approx. 61µs WAFG(DAFG) /INTR Writing WAFG(DAFG) (Match between current time preset alarm (Match between current time preset alarm Writing WAFG(DAFG) (Match between current time preset alarm Approx. 61µs
Rev.1.03
R2061 Series
Time Counter (Address 0-2h) Second Counter (Address Indefinite Indefinite Minute Counter (Address Indefinite Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
(For Writing) (For Reading) Default Settings
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
(For Writing) (For Reading) Default Settings
Hour Counter (Address (For Writing) (For Reading) Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings Default settings: Default value means read written values when power-on from volts. Time digit display (BCD format) follows: second digits range from carried minute digit transition from minute digits range from carried hour digits transition from hour digits range shown "P11 Control Register (ADDRESS /1224: /12-24-hour Mode Selection Bit" carried day-of-month day-of-week digits transition from PM11 AM12 from writing second counter resets divider units less than second. carry from lower digits with writing non-existent time cause time counters malfunction. Therefore, such incorrect writing should replaced with writing existent time data.
Day-of-week Counter (Address Default settings: (For Writing) (For Reading) Indefinite Indefinite Indefinite Default Settings Default value means read written values when power-on from volts.
day-of-week counter incremented when day-of-week digits carried day-of-month digits. Day-of-week display (incremented septimal notation): (W4, 1).(1, Correspondences between days week day-of-week digits user-definable (e.g. Sunday writing (W4, prohibited except when days week unused.
Rev.1.03
R2061 Series
Calendar Counter (Address 4-6h) Day-of-month Counter (Address Indefinite Indefinite Month Counter Century (Address MO10 /1920 MO10 /1920 Indefinite Indefinite Year Counter (Address
Indefinite
Indefinite
Indefinite
Indefinite
(For Writing) (For Reading) Default Settings
Indefinite
Indefinite
Indefinite
Indefinite
(For Writing) (For Reading) Default Settings
(For Writing) (For Reading) Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings Default settings: Default value means read written values when power-on from volts. calendar counters configured display calendar digits format using automatic calendar function follows: day-of-month digits (D20 range from January, March, May, July, August, October, December; from April, June, September, November; from February leap years; from February ordinary years. day-of-month digits carried month digits reversion from last month month digits (MO10 MO1) range from carried year digits reversion from year digits (Y80 range from (00, leap years) carried /1920 digits reversion from /1920 digits cycle between reversion from year digits. carry from lower digits with writing non-existent calendar data cause calendar counters malfunction. Therefore, such incorrect writing should replaced with writing existent calendar data.
Oscillation Adjustment Register (Address (For Writing) (For Reading) Default Settings Default settings: Default value means read written values when power-on from volts. When Oscillation Adjustment Circuit operates seconds. When Oscillation Adjustment Circuit operates seconds. bits Oscillation Adjustment Circuit configured change time counts second basis settings Oscillation Adjustment Register timing DEV.
Rev.1.03
R2061 Series
Oscillation Adjustment Circuit will operate with same timing (00, seconds) timing writing Oscillation Adjustment Register. setting causes increment time counts ((F5, setting causes decrement time counts ((/F5, /F4, /F3, /F2, /F1, /F0) settings ("*" representing either "1") bits cause neither increment decrement time counts.
Example: (DEV, when second digits read increment current time counts 32768 32780 current time count loss). (DEV, when second digits read neither increment decrement current time counts 32768. (DEV, when second digits read decrement current time counts 32768 32764 current time count gain). increase clock pulses once seconds causes time count loss approximately (32768 3.051 ppm). Conversely, decrease clock pulses once seconds causes time count gain ppm. Consequently, when "0", deviations time counts corrected with precision ±1.5 ppm. same way, when "1", deviations time counts corrected with precision ±0.5 ppm. Note that oscillation adjustment circuit configured correct deviations time counts oscillation frequency 32.768-kHz clock pulses. further details, "P29 Configuration Oscillation Circuit Correction Time Count Deviations Oscillation Adjustment Circuit".
Rev.1.03
R2061 Series
Alarm_W Registers (Address 8-Ah) Alarm_W Minute Register (Address WM40 WM20 WM10 WM40 WM20 WM10
Indefinite Indefinite Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
(For Writing) (For Reading) Default Settings
Alarm_W Hour Register (Address WH10 WH20 WP/A WH10 WH20 WP/A Indefinite Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
(For Writing) (For Reading) Default Settings
Alarm_W Day-of-week Register (Address (For Writing) (For Reading) Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings Default settings: Default value means read written values when power-on from volts. Alarm_W Hour Register represents WP/A when 12-hour mode selected a.m. p.m.) WH20 when 24-hour mode selected (tens hour digits). Alarm_W Registers should have non-existent alarm time settings. (Note that mismatch between current time preset alarm time specified Alarm_W registers disable alarm interrupt circuit.) When 12-hour mode selected, hour digits read a.m. p.m., respectively. (See "P11 qControl Register (ADDRESS /1224: 12-/24-hour Mode Selection Bit") correspond day-of-week counter with settings ranging from with respective settings disable outputs Alarm_W Registers.
Rev.1.03
R2061 Series
Example Alarm Time Setting
Alarm Preset alarm time Day-of-week Sun. Mon. Tue. Wed. Fri. Sat. 12-hour mode min. min. 24-hour mode min. min.
00:00 a.m. days 01:30 a.m. days 11:59 a.m. days 00:00 p.m. Mon. Fri. 01:30 p.m. Sun. 11:59 p.m. Mon. ,Wed., Fri.
Note that correspondence between days week shown above table only example mandatory.
Alarm_D Register (Address B-Ch) Alarm_D Minute Register (Address DM40 DM20 DM10 DM40 DM20 DM10 Indefinite Indefinite Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
(For Writing) (For Reading) Default Settings
Alarm_D Hour Register (Address DH10 (For Writing) DH20 DP/A DH10 (For Reading) DH20 DP/A Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings Default settings: Default value means read written values when power-on from volts.
represents DP/A when 12-hour mode selected a.m. p.m.) DH20 when 24-hour mode selected (tens hour digits). Alarm_D registers should have non-existent alarm time settings. (Note that mismatch between current time preset alarm time specified Alarm_D registers disable alarm interrupt circuit.) When 12-hour mode selected, hour digits read 0a.m. 0p.m., respectively. (See "P11 qControl Register (ADDRESS /1224: 12-/24-hour Mode Selection Bit")
Rev.1.03
R2061 Series Interfacing with
DATA TRANSFER FORMATS Timing Between Transition Data Input Output R2061 adopts 3-wire serial interface which they (Chip Enable), SCLK (Serial Clock), (Serial Input/Output) pins receive send data from CPU. 3-wire serial interface provides types input/output timings with which output input synchronized with rising falling edges SCLK input, respectively, vice versa. R2061 configured select either different input/output timings depending level SCLK high transition pin. Namely, when SCLK held high transition pin, models will select timing with which output synchronized with rising edge SCLK input, input synchronized with falling edge SCLK input, illustrated timing chart below.
SCLK (for writing)
tCES
(for reading)
Conversely, when SCLK held high high transition pin, models will select timing with which output synchronized with falling edge SCLK input, input synchronized with rising edge SCLK input, illustrated timing chart below.
SCLK (for writing)
tCES
(for reading)
Data Transfer Formats Data transfer commenced high transition input completed high transition. Data transfer conducted serially multiple units byte bits). former bits used specify Address Pointer head address with which data transfer commenced from host. latter bits used select either reading data transfer writing data transfer, Transfer Format Register specify appropriate data transfer format. data transfer formats designed transfer most significant (MSB) first.
SCLK
Setting Address Pointer
Setting Transfer Format Register
Writing Reading data transfer
types data transfer formats available reading data transfer writing data transfer each.
Rev.1.03
R2061 Series
Writing Data Transfer Formats 1-byte Writing Data Transfer Format first type writing data transfer format designed transfer 1-byte data time selected specifying address pointer head address with which writing data transfer commenced then writing setting transfer format register. This 1-byte writing data transfer completed driving continued specifying head address address pointer setting data transfer format.
Example 1-byte Writing Data Transfer (For Writing Data Addresses
Specifying FhSetting Address Pointer Transfer Format Register
Data
Writing data address
Data
Specifying Setting Writing data Address Pointer Transfer Format Register address
Data transfer from host
Data transfer from RTCs
Burst Writing Data Transfer Format second type writing data transfer format designed transfer sequence data serially selected specifying address pointer head address with which writing data transfer commenced then writing setting transfer format register. address pointer incremented each transfer 1-byte data cycled from This burst writing data transfer completed driving low.
Example Burst Writing Data Transfer (For Writing Data Addresses
Data Data
Writing data address
Data
Writing data address
Specifying EhSetting Writing data Address Pointer Transfer Format Register address
Data transfer from host
Data transfer from RTCs
Rev.1.03
R2061 Series
Reading Data Transfer Formats 1-byte Reading Data Transfer Format first type reading data transfer format designed transfer 1-byte data time selected specifying Address Pointer head address with which reading data transfer commenced then setting writing Transfer Format Register. This 1-byte reading data transfer completed driving continued specifying head address Address Pointer selecting this type reading data Transfer Format.
Example 1-byte Reading Data Transfer (For Reading Data from Addresses
Specifying EhSetting Address Pointer Transfer Format Register
Data
Reading data from address
Data
Specifying Setting Reading data from Address Pointer Transfer Format Register address
Data transfer from host
Data transfer from RTCs
Burst Reading Data Transfer Format second type reading data transfer format designed transfer sequence data serially selected specifying address pointer head address with which reading data transfer commenced then writing setting transfer format register. address pointer incremented each transfer 1-byte data cycled from This burst reading data transfer completed driving low.
Example Burst Reading Data Transfer (For Reading Data from Addresses
DATA DATA
Reading data from address
DATA
Reading data from address
Specifying FhSetting Reading data from Transfer address Address Pointer Format Register
Data transfer from host
Data transfer from RTCs
Rev.1.03
R2061 Series
Combination 1-byte Reading writing Data Transfer Formats 1-byte reading writing data transfer formats combined together further followed other data transfer format.
Example Reading Modify Writing Data Transfer (For Reading Writing Data from Address
DATA
Specifying FhSetting Address Pointer Transfer Format Register
DATA
Writing data address
Specifying FhSetting Reading data from Transfer address Address Pointer Format Register
Data transfer from host
Data transfer from RTCs
reading writing data transfer formats correspond settings transfer format register shown table below. Byte (1,0,0,0) (1,1,0,0) Burst (0,0,0,0) (0,1,0,0)
Writing data transfer Reading data transfer
Rev.1.03
R2061 Series
Considerations Reading Writing Time Data under special condition carry second digits process reading writing time data cause reading writing erroneous time data. example, suppose carry 13:59:59 into 14:00:00 occurs process reading time data middle shifting from minute digits hour digits. this moment, second digits, minute digits, hour digits read seconds, minutes, hours, respectively (indicating 14:59:59) cause reading time data deviating from actual time virtually hour. similar error also occurs writing time data. prevent such errors reading writing time data, R2043 function temporarily locking carry second digits during high interval unlocking such carry high transition. Note that carry second digits locked only second, during which time should driven low.
13:59:59 14:00:00 14:00:01
Actual time
Max.62µs
Time counts within
13:59:59
14:00:00
14:00:01
effective this function requires following considerations reading writing time data: Hold high each session reading writing time data. Ensure that high interval lasts within second. Should there possibility host going down process reading writing time data, make arrangements peripheral circuitry drive open moment that host actually goes down. Leave time span 31µs more from high transition start access addresses order that ongoing carry time digits completed within this time span. Leave time span 62µs more from high transition high transition order that ongoing carry time digits during high interval adjusted within this time span. considerations listed (1), (3), above required when process reading writing time data obviously free from carry time digits. (e.g. reading writing time data synchronization with periodic interrupt function level mode alarm interrupt function). Good examples reading writing time data illustrated next page.
Rev.1.03
R2061 Series
Good Example
Time span 31µs more
address other than addresses permits immediate reading writing without requiring time span
Address Pointer Transfer Format Register
DATA
Reading from Address (control2)
DATA
Reading from Address (sec.)
DATA
Reading from Address (min.)
DATA
Reading from Address (hr.)
Example (Where once driven process reading time data)
31µs more 31µs more
Address Pointer Transfer Format Register
Data
Reading from Address (sec.)
Address Pointer Transfer Format Register
Data
Reading from Address (min.)
Data
Reading from Address (hr.)
Example (Where time span less than 31µs left until start process writing time data)
Time span less than 31µs
Address Pointer Transfer Format Register
Data
Writing Address (contorl2)
Data
Writing Address (sec.)
Data
Writing Address (min.)
Data
Writing Address (hr.)
Example (Where time span less than 62µs left between adjacent processes reading time data)
Less than 62µs
Address Pointer Transfer Format Register
Data
Reading from Address (sec.)
Address Pointer Transfer Format Register
Data
Reading from Address (sec.)
Data transfer from host
Data
Data transfer from RTCs
Rev.1.03
R2061 Series Configuration Oscillation Circuit Correction Time Count Deviations
Configuration Oscillation Circuit Typical externally-equipped element X'tal 32.768kHz (R1=30k typ) (CL=6pF 8pF) Standard values internal elements CG,CD 10pF
OSCIN Oscillator Circuit OSCOUT
32kHz
oscillation circuit driven constant voltage approximately volts relative level input. such, configured generate oscillating waveform with peak-to-peak voltage order volts positive side input. Considerations Handling Crystal Oscillators Generally, crystal oscillators have basic characteristics including equivalent series resistance (R1) indicating ease their oscillation load capacitance (CL) indicating degree their center frequency. Particularly, crystal oscillators intended R2061 recommended have typical value typical value 8pF. confirm these recommended values, contact manufacturers crystal oscillators intended these particular models. Considerations Installing Components around Oscillation Circuit Install crystal oscillator closest possible vicinity real-time clock ICs. Avoid laying signal lines power lines vicinity oscillation circuit (particularly area marked above figure). Apply highest possible insulation resistance between OSCIN OSCOUT pins printed circuit board. Avoid using long parallel lines wire OSCIN OSCOUT pins. Take extreme care cause condensation, which leads various problems such oscillation halt. Other Relevant Considerations external input 32.768-kHz clock pulses OSCIN pin: coupling: Prohibited input level mismatch. coupling: Permissible except that oscillation halt sensing circuit does guarantee perfect operation because cause sensing errors such factors noise. maintain stable characteristics crystal oscillator, avoid driving other through 32.768-kHz clock pulses output from OSCOUT pin.
Rev.1.03
R2061 Series
Measurement Oscillation Frequency
OSCIN OSCOUT /INTR Frequency Counter 32768Hz
R2061 configured generate clock pulses output from /INTR setting (00XX0011) address frequency counter with (more preferably more digits order 1ppm recommended measurement oscillation frequency oscillation circuit.
Adjustment Oscillation frequency oscillation frequency oscillation circuit adjusted varying procedures depending usage Model R2061 system into which they built allowable degree time count errors. Course When time count precision each adjusted, crystal oscillator intended that have value requiring presetting. crystal oscillator subject frequency variations which selectable within allowable range time count precision. Several crystal oscillators RTCs should used find center frequency crystal oscillators method described "P27 Measurement Oscillation Frequency" then calculate appropriate oscillation adjustment value method described "P29 Oscillation Adjustment Circuit" writing this value R2061. Course When time count precision each adjusted within oscillation frequency variations crystal oscillator plus frequency variations real-time clock ICs, becomes necessary correct deviations time count each method described Oscillation Adjustment Circuit". Such oscillation adjustment provides crystal oscillators with wider range allowable settings their oscillation frequency variations their values. real-time clock crystal oscillator intended that real-time clock should used find center frequency crystal oscillator method described Measurement Oscillation Frequency" then confirm center frequency thus found fall within range adjustable oscillation adjustment circuit before adjusting oscillation frequency oscillation circuit. normal temperature, oscillation frequency oscillator circuit adjusted approximately ±0.5ppm. Generally, crystal oscillators commercial classified terms their center frequency depending their load capacitance (CL) further divided into ranks order ±10, ±20, ±50ppm depending degree their oscillation frequency variations. Basically, Model R2061 configured cause frequency variations order ±10ppm 25°C. Time count precision referred above flow chart applicable normal temperature actually affected temperature characteristics other properties crystal oscillators.
Rev.1.03
R2061 Series
R2061, which incorporate require adjusting oscillation frequency crystal oscillator through value. Generally, relationship between value values represented following equation: CD)/(CG where "CS" represents floating capacity printed circuit board. crystal oscillator intended R2061 recommended have value order 8pF. oscillation frequency should measured method described Measurement Oscillation Frequency". crystal oscillator found have excessively high oscillation frequency (causing time count gain loss, respectively) should replaced with another having smaller greater value, respectively until another having optimum value selected. this case, settings disabling oscillation adjustment circuit (see Oscillation Adjustment Circuit should written oscillation adjustment register. Incidentally, high oscillation frequency crystal oscillator also adjusted adding external oscillation stabilization capacitor CGOUT illustrated diagram below.
CGOUT should have capacitance ranging from
OSCIN Oscillator Circuit 32kHz OSCOUT CGOUT
Rev.1.03
R2061 Series
Oscillation Adjustment Circuit oscillation adjustment circuit used correct time count gain loss with high precision varying number 1-second clock pulses once seconds seconds. When Oscillation Adjustment Register R2061 varies number 1-second clock pulses once seconds. When R2061 varies number 1-second clock pulses once seconds. oscillation adjustment circuit disabled writing settings ("*" representing "1") bits oscillation adjustment circuit. Conversely, when such oscillation adjustment made, appropriate oscillation adjustment value calculated equation below writing oscillation adjustment circuit. When Oscillation Frequency Higher Than Target Frequency (Causing Time Count Gain) When DEV=0: Oscillation adjustment value (*3) (Oscillation frequency Target Frequency 0.1) Oscillation frequency 3.051 (Oscillation Frequency Target Frequency) When DEV=1: Oscillation adjustment value (*3) (Oscillation frequency Target Frequency 0.0333) Oscillation frequency 1.017 (Oscillation Frequency Target Frequency) Oscillation frequency: 32768 times frequency clock pulse output from /INTR normal temperature manner described Measurement Oscillation Frequency". Target frequency: Desired frequency set. Generally, 32.768-kHz crystal oscillator such temperature characteristics have highest oscillation frequency normal temperature. Consequently, crystal oscillator recommended have target frequency settings order 32.768 32.76810 (+3.05ppm relative 32.768 kHz). Note that target frequency differs depending environment location where equipment incorporating expected operated. Oscillation adjustment value: Value that finally written bits Oscillation Adjustment Register represented 7-bit coded decimal notation.
When Oscillation Frequency Equal Target Frequency (Causing Time Count neither Gain Loss) Oscillation adjustment value -64, When Oscillation Frequency Lower Than Target Frequency (Causing Time Count Loss) When DEV=0: Oscillation adjustment value (Oscillation frequency Target Frequency) Oscillation frequency 3.051 (Oscillation Frequency Target Frequency) When DEV=1: Oscillation adjustment value (Oscillation frequency Target Frequency) Oscillation frequency 1.017 (Oscillation Frequency Target Frequency) Oscillation adjustment value calculations exemplified below oscillation frequency 32768.85Hz target frequency 32768.05Hz When setting Oscillation adjustment value (32768.85 32768.05 0.1) (32768.85 3.051 (32768.85 32768.05) 9.001 this instance, write settings oscillation adjustment register. Thus, appropriate oscillation adjustment value presence time count gain represents distance from 01h. When setting
Rev.1.03
R2061 Series
Oscillation adjustment value (32768.85 32768.05 0.0333) (32768.85 1.017 (32768.85 32768.05) 23.51 this instance, write settings oscillation adjustment register.
oscillation frequency 32762.22Hz target frequency 32768.05Hz When setting Oscillation adjustment value (32762.22 32768.05) (32762.22 3.051 (32762.22 32768.05) -58.325 represent oscillation adjustment value 7-bit coded decimal notation, subtract (3Ah) from (80h) obtain 46h. this instance, write settings (DEV,F6,F5,F4,F3,F2,F1,F0) (0,1,0,0,0,1,1,0) oscillation adjustment register. Thus, appropriate oscillation adjustment value presence time count loss represents distance from 80h. When setting Oscillation adjustment value (32762.22 32768.05) (32762.22 1.017 (32762.22 32768.05) -174.97 -175 Oscillation adjustment value from Then, this case, Oscillation adjustment value range. Difference between DEV=0 DEV=1 Difference between DEV=0 DEV=1 following, DEV=0 -189.2ppm 189.2ppm 3ppm DEV=1 -62ppm 63ppm 1ppm
Maximum value range Minimum resolution
Notes: following conditions completed, actual clock adjustment value could different from target adjustment value that oscillator adjustment function. Using oscillator adjustment function Access R2051 random, synchronized with external clock that relation R2051, synchronized with periodic interrupt pulse mode. Access R2051 more than times each second average. more details, please contact Ricoh.
evaluate clock gain loss oscillator adjustment circuit configured change time counts second basis settings oscillation adjustment register once seconds seconds. measure clock error follows: Output clock pulse Pulse Mode with interrupt (0,0,x,x,0,0,1,1) Control Register address After setting oscillation adjustment register, clock period changes every 20seconds every seconds) like next page figure.
Rev.1.03
R2061 Series
clock pulse times time
Measure interval with frequency counter. recommended measurement. Calculate typical period from Calculate time error from
frequency counter with more digits
Rev.1.03
R2061 Series Power-on Reset, Oscillation Halt Sensing, Supply Voltage Monitoring
PON, /XST, VDET power-on reset circuit configured reset control register1, clock adjustment register when power from oscillation halt sensing circuit configured record halt oscillation 32.768-kHz clock pulses. supply voltage monitoring circuit configured record drop supply voltage below threshold voltage 1.35v. Each function monitor bit. I.e. power-on reset circuit, /XST oscillation halt sensing circuit, VDET supply voltage monitoring circuit. VDET bits activated "H". However, /XST activated "L". VDET accept only writing /XST accepts writing when power-up from VDET /XST indefinite. functions these three monitor bits shown table below. Monitoring power-on reset function Address High only /XST Monitoring oscillation halt sensing function Address indefinite Both VDET drop supply voltage below threshold voltage 1.35v Address High only
Function
Address Activated When power from accept writing
relationship between PON, /XST, VDET shown table below. /XST VDET Conditions supply voltage oscillation Halt oscillation, drop supply voltage below threshold voltage Halt oscillation drop supply voltage below threshold voltage, drop drop supply voltage below threshold voltage halt oscillation Drop supply voltage below threshold voltage halt oscillation Drop supply voltage Condition oscillator, back-up status Halt oscillation cause condensation etc. Halt oscillation cause drop back-up battery voltage Normal condition
halt oscillation, drop back-up battery voltage Power-up from
Threshold voltage (2.1V 1.35V)
32768Hz Oscillation Power-on reset flag (PON) Oscillation halt sensing flag (/XST) supply voltage monitor flag (VDET) VDET0 /XST1 PON0 VDET0 /XST1 VDET0 /XST1 PON0
Internal initialization period sec.)
Internal initialization period sec.)
When control register DEV, WALE, DALE, /1224, SCRATCH2,
Rev.1.03
R2061 Series
TEST, CT2, CT1, CT0, VDSL, VDET, SCRATCH1, CTFG, WAFG, DAFG bits reset oscillation adjustment register, control register control register also power-on from volts. Considerations Using Oscillation Halt Sensing Circuit sure prevent oscillation halt sensing circuit from malfunctioning preventing following: Instantaneous power-down Condensation crystal oscillator On-board noise crystal oscillator Applying individual pins voltage exceeding their respective maximum ratings particular, note that /XST fail presence applied supply voltage illustrated below such events backup battery installation. Further, give special considerations prevent excessive chattering oscillation halt sensing circuit.
Rev.1.03
R2061 Series
Voltage Monitoring Circuit R2061 incorporates kinds voltage monitoring function. These shown table below. Voltage Monitoring Circuit Voltage Monitoring Circuit (VDET) Purpose reset output Back-up battery checker Monitoring supply voltage (supply voltage internal circuit) Output result /VDCC Store Control Register Address Function After falling VCC, /VDCC outputs "L". tDEALY after rising VCC, /VDCC outputs (OFF) Below threshold voltage, turns turns Over threshold voltage, turns turns off. Detector Threshold (falling edge -VDET1 Selecting from VDETH VDETL power supply voltage) writing register Address Detector Released +VDET1 Same falling edge Voltage (rising edge power hysteresis) supply voltage) monitor Always time every second supply voltage monitoring circuit configured conduct sampling operation during interval 7.8ms second check drop supply voltage below threshold voltage 1.35v VDSL setting (the default setting) respectively, Control Register thus minimizing supply current requirements illustrated timing chart below. This circuit suspends sampling operation once VDET Control Register supply voltage monitor useful back-up battery checking.
2.1v 1.35v
Internal nitialization period 2sec.)
7.8ms
Sampling timing supply voltage monitor VDET Address VDET0
PON0 VDET0
Rev.1.03
R2061 Series
supply voltage monitor circuit operates always. When rising over +VDET1, turns turns off. tDELAY after rising VCC, /VDCC outputs OFF(H). when oscillation halt, outputs OFF(H) tDELAY after oscillation starting. When falling beyond -VDET1, turns off, turns /VDCC outputs "L".
Oscillation starting
-VDET1
+VDET1
Same voltage level
32768Hz Oscillation /VDCC tDELAY tDELAY tDELAY
Battery Switch Over Circuit
R2061 incorporates three power supply pins, VDD, VCC, VSB. power supply internal real time clock circuit. When voltage lower than ±VDET, supplies power VDD, when higher than ±VDET, supplies power VDD. timing chart VCC, VDD, shown following.
+VDET1
-VDET1
When rising from follows half voltage level. After rising over +VDET, follows voltage level. When higher than +VDET, level equal VCC. After falling beyond -VDET, level equal VSB.
Rev.1.03
R2061 Series Alarm Periodic Interrupt
R2061 incorporates alarm interrupt circuit periodic interrupt circuit that configured generate alarm signals periodic interrupt signals output from /INTR described below. Alarm Interrupt Circuit alarm interrupt circuit configured generate alarm signals output from /INTR, which driven (enabled) upon occurrence match between current time read time counters (the day-of-week, hour, minute counters) alarm time preset alarm registers (the Alarm_W registers intended day-of-week, hour, minute digit settings Alarm_D registers intended hour minute digit settings). Periodic Interrupt Circuit periodic interrupt circuit configured generate either clock pulses pulse mode interrupt signals level mode output from /INTR depending CT2, CT1, settings control register above types interrupt signals monitored flag bits (i.e. WAFG, DAFG, CTFG bits Control Register enabled disabled enable bits (i.e. WALE, DALE, CT2, CT1, bits Control Register listed table below. Flag bits WAFG Address DAFG Address CTFG Address Enable bits WALE Address DALE Address CT2=CT1=CT0=0 (These setting disable Periodic Interrupt) Address
Alarm_W Alarm_D Peridic interrupt
power-on, when WALE, DALE, CT2, CT1, bits Control Register /INTR driven high (disabled). When types interrupt signals output simultaneously from /INTR pin, output from /INTR becomes waveform their negative logic.
Example: Combined Output /INTR Under Control /ALARM_D Periodic Interrupt /Alarm_D Periodic Interrupt /INTR
this event, which type interrupt signal output from /INTR confirmed reading DAFG, CTFG settings Control Register
Alarm Interrupt alarm interrupt circuit controlled enable bits (i.e. WALE DALE bits Control Register flag bits (i.e. WAFG DAFG bits Control Register enable bits used enable this circuit when disable when When intended reading, flag bits used monitor alarm interrupt signals. When intended writing, flag bits will cause event when will drive high (disable) alarm interrupt circuit when enable bits will affected even when flag bits this event, therefore, alarm interrupt circuit will continue function until driven (enabled) upon next occurrence match between current time preset alarm time.
Rev.1.03
R2061 Series
alarm function presetting desired alarm time alarm registers (the Alarm_W Registers day-of-week digit settings both Alarm_W Registers Alarm_D Registers hour minute digit settings) with WALE DALE bits once then Control Register Note that WALE DALE bits should once order disable alarm interrupt circuit upon coincidental occurrence match between current time preset alarm time process setting alarm function.
Interval (1min.) during which match between current time preset alarm time occurs
/INTR
WALE1 current time WALE0 preset alarm time (DALE) (DALE)
WALE1 (DALE)
current time preset alarm time
/INTR
WALE1 current time preset alarm time (DALE)
WAFG0 (DAFG)
current time preset alarm time
After setting WALE(DALW) Alarm registers current time, WALE(DALE) /INTR will driven immediately, /INTR will driven next alarm setting time.
Periodic Interrupt Setting periodic selection bits (CT2 CT0) enables periodic interrupt CPU. There waveform modes: pulse mode level mode. pulse mode, output waveform duty cycle around 50%. level mode, output cyclically driven and, when CTFG output return High (OFF). Description Wave form mode Pulse Mode Pulse Mode Level Mode Level Mode Level Mode Level Mode
Interrupt Cycle Falling Timing OFF(H) Fixed 2Hz(Duty50%) 1Hz(Duty50%) Once second (Synchronized with Second counter increment) Once minute seconds every Minute) Once hour minutes Seconds every hour) Once month hours, minutes, seconds first every month)
(Default)
Pulse Mode: 2-Hz 1-Hz clock pulses output synchronization with increment second counter illustrated timing chart below.
CTFG /INTR Approx. 92µs (Increment second counter) Rewriting second counter
Rev.1.03
R2061 Series
pulse mode, increment second counter delayed approximately from falling edge clock pulses. Consequently, time readings immediately after falling edge clock pulses appear behind time counts real-time clocks approximately second. Rewriting second counter will reset other time counters less than second, driving /INTR low. Level Mode: Periodic interrupt signals output with selectable interrupt cycle settings second, minute, hour, month. increment second counter synchronized with falling edge periodic interrupt signals. example, periodic interrupt signals with interrupt cycle setting second output synchronization with increment second counter illustrated timing chart below.
CTFG /INTR Setting CTFG (Increment second counter) (Increment second counter) Setting CTFG (Increment second counter)
*1), When oscillation adjustment circuit used, interrupt cycle will fluctuate once 20sec. follows: Pulse Mode: period output pulses will increment decrement maximum ±3.784ms. example, 1-Hz clock pulses will have duty cycle ±0.3784%. Level Mode: periodic interrupt cycle second will increment decrement maximum ±3.784
Rev.1.03
R2061 Series Typical Applications
Typical Power Circuit Configurations case back-up primary battery
case back-up capacitor secondary battery (Charging voltage equal power supply voltage)
case back-up capacitor secondary battery (Charging voltage equal power supply voltage)
Power Supply
power supply
power supply (3V)
0.1µF
Double layer capacitor etc.
CR2025 etc.
ML614 etc.
cannot connect additional heavy load components such SRAM. must connected should over 0.1µF.
R2061 Series
Vbat VOLTAGE DETECTOR -VDET1
power supply
Rcpu
When secondary battery double layer capacitor connects pin, after power supply turning off, secondray battery discharges through root above figure. much smaller than impedance (Rcpu), voltage keeps higher than -VDET1, keeps Therefore must specified following formula. Rcpu (Vbat (-VDET1)) (-VDET1) specified back-up battery double layer capacitor, too. Please check data sheet back-up devices.
Connection Please connect capacitor over 0.1µF between pin.
Rev.1.03
R2061 Series
Connection /INTR /VDCC /INTR /VDCC pins follow N-channel open drain output logic contains protective diode power supply side. such, connected pull-up resistor volts regardless supply voltage.
power supply
/INTR /VDCC OSCIN OSCOUT 32768Hz
Backup power supply
Depending whether /INTR /VDCC pins used during battery backup, should connected pull-up resistor following different positions: Position left diagram when used during battery backup. Position left diagram when used during battery backup.
Rev.1.03
R2061 Series Typical Characteristics
Time keeping current (ISB) Supply voltage (VSB) (Topt=25°C)
Time keeping current (uA)
Test Circuit
/INTR /VDCC OSCIN OSCOUT 0.1µF SCLK 0.1µF
VSB(v)
Stand-by current (ICC) Supply voltage (VCC) (Topt=25°C)
Stand-by Current (uA)
Test circuit
OSCIN OSCOUT 0.1µF SCLK 0.1µF
/INTR /VDCC
VCC(v)
Time keeping current (ISB) Operating Temperature (Topt) (VSB=3V)
Time keeping current (uA)
Test circuit
/INTR OSCIN OSCOUT 0.1µF SCLK 0.1µF
/VDCC
Operating Temperature (Celsius)
Rev.1.03
R2061 Series
Stand-by current (ICC) Operating Temperature (Topt) (VCC=3V)
Stand-by current(uA)
Test circuit
OSCIN OSCOUT 0.1µF 0.1µF
/INTR /VDCC
Operating temperature (Celsius)
SCLK
access current SCLK clock frequency (kHz) (Topt=25°C)
access current (uA)
VCC=5v
VCC=3v
1000 clock frequency (KHz)
Oscillation frequency deviation (f/f0) Operating temperature (Topt) (VCC=3V Topt=25°C standard) Test circuit
-100 -120 -140 -160
Oscillation frequency deviation df/f0(ppm)
/VDCC Frequency counter /INTR SCLK
OSCIN OSCOUT 0.1µF 0.1µF
Operating temperature Topt(Celsius)
Rev.1.03
R2061 Series
Frequency deviation (f/f0) Supply voltage (VSB/VCC) (Topt=25°C) VCC/VSB=3V standard
Frequency deviation df/f0(ppm) VCC/VSB(v)
Test circuit
/VDCC OSCIN OSCOUT 0.1µF SCLK 0.1µF
Frequency counter
/INTR
Frequency deviation (f/f0) CGOUT (Topt=25°C, VCC=3V)CGOUT=0pF standard
Frequency deviation df/f0(ppm) CGOUT(pF)
Test circuit
/VDCC Frequency counter /INTR SCLK OSCIN OSCOUT 0.1µF 0.1µF
Detector threshold voltage (+VDET1/-VDET1) Operating temperature (Topt) (R2061K01) (VSB=3V) Test circuit
Detector threshold voltage ±VDET1(V)
OSCIN OSCOUT 0.1µF 0.1µF
+VDET1 -VDET1
/INTR /VDCC
Operating Temperature Topt(Celsius)
SCLK
Rev.1.03
R2061 Series
VCC-VDD(VDDOUT1) Output load current (IOUT1) (R2061K01) (Topt=25°C) Test circuit
-0.1 VCC-VDD(V) -0.2 -0.3 -0.4
OSCIN OSCOUT 0.1µF 0.1µF
VCC=5V
/INTR
VCC=3V VCC=2.5V
/VDCC
VCC=2.0V
-0.5 Output load current IOUT1(mA)
SCLK
VSB-VDD(VDDOUT2) Output load current (IOUT2) (R2061K01) (Topt=25°C) Test circuit
-0.1 VSB-VDD(V) -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 Output load current IOUT2(mA)
OSCIN OSCOUT 0.1µF 0.1µF
VSB=3V VSB=1V VSB=2V
/INTR /VDCC SCLK
(/VDCC pin) (Topt=25°C, VSB=VCC=1.5v)
VOL(v) VOL(v) IOL(mA)
(/INTR pin) (Topt=25°C)
VCC=3V
VCC=5V
IOL(mA)
Rev.1.03
R2061 Series
Typical Software-based Operations
Initialization Power-on
Start Power-on
PON=1?
VDET=0?
Oscillation Adjustment Register Control Register etc.
Warning Back-up Battery Run-down
After power-on from volt, process internal initialization require time span 1sec, that access should done after /VDCC turning OFF(H). setting Control Register indicates power-on from backup battery from further details, "P.32 sPower-on Reset, Oscillation Halt Sensing, Supply Voltage Monitoring qPON, /XST, VDET This step required when supply voltage monitoring circuit used. This step involves ordinary initialization including Oscillation Adjustment Register interrupt cycle settings, etc.
Writing Time Calendar Data
When writing clock calendar counters, insert CE=L until
times from second year have been written prevent error writing time. (Detailed "P.24 qConsiderations Reading Writing Time Data under special condition". writing second counter will reset divider units lower than second digits.
Write Time Counter Calendar Counter
R2061 also initialized power-on process writing time calendar data.
Rev.1.03
R2061 Series
Reading Time Calendar Data Ordinary Process Reading Time Calendar Data
When reading clock calendar counters, insert CE=L until times from second year have been read prevent error reading time. (Detailed "P.24 qConsiderations Reading Writing Time Data under special condition".
Read from Time Counter Calendar Counter
Basic Process Reading Time Calendar Data with Periodic Interrupt Function
Periodic Interrupt Cycle Selection Bits
This step intended select level mode waveform mode periodic interrupt function. This step must completed within second. This step intended CTFG Control Register cancel interrupt CPU.
Generate Interrupt
CTFG=1?
Read from Time Counter Calendar Counter
Other Interrupt Processes
Control Register (X1X1X011)
Rev.1.03
R2061 Series
Applied Process Reading Time Calendar Data with Periodic Interrupt Function Time data need read from time counters when used such ordinary purposes time count indication. This applied process used read time calendar data with substantial reductions load involved such reading. Time Indication "Day-of-Month, Day-of-week, Hour, Minute, Second" Format:
Control Register (XXXX0100) Control Register (X1X1X011)
Generate interrupt Other interrupts Processes
CTFG=1?
This step intended select level mode waveform mode periodic interrupt function. This step must completed within sec. This step intended read time data from time counters only first session reading time data after writing time data. This step intended CTFG Control Register cancel interrupt CPU.
Sec.=00?
Previous Min.,Hr., Day,and Day-of-week data
Read Min.,Hr.,Day, Day-of-week
Control Register (X1X1X011)
Rev.1.03
R2061 Series
Interrupt Process Periodic Interrupt
Periodic Interrupt Cycle Selection Bits
This step intended select level mode waveform mode periodic interrupt function. This step intended CTFG Control Register cancel interrupt CPU.
Generate Interrupt
CTFG=1?
Conduct Periodic Interrupt
Other Interrupt Processes
Control Register (X1X1X011)
Alarm Interrupt
WALE DALE0
Alarm Min., Hr., Day-of-week Registers
WALE DALE1
This step intended once disable alarm interrupt circuit setting WALE DALE bits anticipation coincidental occurrence match between current time preset alarm time process setting alarm interrupt function. This step intended enable alarm interrupt function after completion alarm interrupt settings. This step intended once cancel alarm interrupt function writing settings "X,1,X, 1,X,1,0,1" "X,1,X,1,X,1,1,0" Alarm_W Registers Alarm_D Registers, respectively.
Generate Interrupt
WAFG DAFG=1?
Other Interrupt
Processes
Conduct Alarm Interrupt
Control Register (X1X1X101)
Rev.1.03

'03.07.15 wire interface Real-Time Clock with Battery Backup swit

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