Image Digitizers with CDS, 10-Bit FEATURES APPLICATIONS

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Image Digitizers with CDS, 10-Bit FEATURES APPLICATIONS

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XRD9855/L55
Image Digitizers with CDS, 10-Bit
FEATURES
APPLICATIONS
10-Bit Resolution 25MHz Sampling Rate Correlated Double Sampling (CDS) Programmable Gain from 38dB (PGA) Digital Offset-Calibration Black Level Offset Compensation Clocks Sample Rising Edge Falling Edge Single Power Supply Power Battery Applications: XRD9855: 250mW 5.0V XRD98L55: 120mW 3.0V 50µA-Typ Current Stand Mode 3-State Digital Outputs Protection Over 2000V
Digital Video Camcorders Digital Still Cameras Video Teleconferencing Digital Copiers Infrared Image Digitizers CCD/CIS Imager Interface
GENERAL DESCRIPTION XRD9855/XRD98L55 complete Image Digitizers digital cameras. products include high bandwidth differential Correlated Double Sampler (CDS), 8-bit digitally Programmable Gain Amplifier (PGA), 10-bit Analog-to-Digital Converter (ADC) digital black level auto-calibration circuitry. Correlated Double Sampler (CDS) subtracts output signal black level from video level. Common mode signal noise power supply noise rejected differential input stage. inputs designed used either differential singleended. auto calibration circuit compensates internal offset XRD9855/XRD98L55 well black level offset from CCD. ORDERING INFORMATION
Operating Power Supply 5.0V 3.0V
digitally controlled with 8-bit resolution linear scale, resulting gain range 38dB with 0.125dB gain code. black level auto-calibration controlled through simple 3-wire serial interface. timing circuitry designed enable users select wide variety available image sensors their applications. XRD9855/XRD98L55 direct access output input through TESTVIN. XRD9855/XRD98L55 packaged 48-lead surface mount TQFP reduce space weight, suitable hand-held portable applications.
Part XRD9855AIV XRD98L55AIV
Package Lead TQFP Lead TQFP
Temperature Range -40°C 85°C -40°C 85°C
EXAR Corporation, 48720 Kato Road, Fremont, 94538 (510) 668-7000 (510) 668-7017
XRD9855/L55
VRBO
TESTVIN
VRTO DVDD
In_Pos In_Neg DGND RSTCCD CLAMP CLK_POL Timing Generator SYNC OVER Offset Calibration Serial Port Registers UNDER DB[9:0]
SCLK LOAD
STBY1 STBY2
RESET
EnableCal
Figure XRD9855/XRD98L55 Simplified Block Diagram
Rev. 1.00
In_Pos In_Neg LOAD
XRD9855/L55
CONFIGURATION
CLAMP RSTCCD CLK_POL SYNC UNDER
SCLK RESET STBY2 STBY1 Test EnableCal OVER
Lead TQFP
DESCRIPTION TQFP
Symbol DGND OVER Description Connect. Connect. Output. LSB, MSB. Output. Output. Digital Output Ground. Digital Output Power Supply. Must less than equal Output. Output. Output. Connect. Connect. Output. Output. Over Range Output Bit. OVER goes high indicate input voltage greater than VRT.
Rev. 1.00
DGND DVDD
XRD9855/L55
DESCRIPTION TQFP (CONT'D)
Symbol EnableCal TESTVIN STBY1 STBY2 RESET SCLK LOAD VRTO In_Neg In_Pos VRBO CLAMP RSTCCD CLK_POL SYNC UNDER Description Digital Output Enable (Three-State Control). Pull enable output drivers. Pull high output drivers high impedance state. Analog Power Supply. Calibration Enable. Automatic offset calibration control. Analog Ground. Test Input Test Output. Standby Control Pull chip power down mode. Standby Control Short STBY1 using TESTVIN pin. Chip Reset. Pull high reset internal registers. Shift Clock. Shift register latches data rising edges SCLK. Connect. Data Load. Rising edge loads data from shift register internal register. Load must enable shift register. Serial Data Input. Reference. Voltage sets full-scale ADC. Internal Bias VRT. Short VRTO internal reference voltage. Analog Power Supply. Inverting Input. Connect capacitor video output. Non-inverting Input. Connect capacitor supply. Analog Ground. Internal Bias VRB. Short VRB0 internal reference voltage. Bottom Reference. Voltage sets zero scale ADC. Connect. Restore Clamp. Clamps In_Pos In_Neg internal bias voltage. Clock. Controls sampling pixel video level. Clock. Controls sampling pixel black level. Reset Pulse Disconnect. Used decouple during reset pulse. Analog Ground. Clock Polarity. Controls polarity SHP, CLAMP. Analog Power Supply. Digital output Exar test purposes only. connect. Under Range Output Bit. UNDER goes high indicate input voltage less than VRB. Output. Output. Connect.
Rev. 1.00
XRD9855/L55
ELECTRICAL CHARACTERISTICS XRD9855 Unless otherwise specified: DVDD 5.0V, Pixel Rate 18MSPS, 3.8V, 0.5V
Symbol Parameter Min. Typ. Max. Unit Conditions
Performance CDSVIN Input Range Small Signal Bandwidth (-3dB) Slew Rate Feed-through (Hold Mode) V/µs 400mV Step Input. Pixel (Black Level Video Level)
Parameters AVMIN AVMAX Minimum Gain Maximum Gain Resolution Gain Error bits Transfer function linear steps (1LSB 0.125dB). maximum minimum gain setting.
Parameters (Measured Through TESTVIN) DNL25 Resolution Sample Rate Differential Non-Linearity Differential Non-Linearity Zero Scale Error Full Scale Error Input Range +0.75 +0.9 bits MSPS swing from VDD. Input range limited output swing PGA. >VRB >VRB 18MHz sample rate. 25MHz sample rate. Measured relative VRB.
VREF
Reference Voltage Bottom Reference Voltage Differential Reference Voltage Ladder Resistance
VDD-1
Ohms
Self Bias Self Bias
1.30
connected VRBO. connected VRTO.
Rev. 1.00
XRD9855/L55
ELECTRICAL CHARACTERISTICS XRD9855 (CONT'D) Unless otherwise specified: DVDD 5.0V, Pixel Rate 18MSPS, 3.8V, 0.5V
Symbol Parameter Min. Typ. Max. Unit Conditions
System Specifications DNLSMIN SMAX INLSMIN INLSMAX MINAV Minimum Gain Maximum Gain Minimum Gain Maximum Gain Offset (Input Referred) Minimum Gain 0.75 0.75 error dominated CDS/PGA linearity. error dominated CDS/PGA linearity. Offset defined input pixel value-0.5 required cause output switch from "Zero scale" "Zero scale 1LSB". Offset measured after calibration. Zero scale code offset register. Offset depends gain code. MAXAV MINAV Digital Inputs Digital Outputs Digital Output High Voltage Digital Output Voltage High-Z Leakage DVDD-0.5 While sourcing 2mA. While sinking 2mA. OE=1 STBY1= STBY2 Output between Digital Input High Voltage Digital Input Voltage Leakage Current Input Capacitance Input Between VDD. Input Referred Noise Maximum Gain Input Referred Noise Minimum Gain mVrms mVrms Noise depends upon gain setting PGA. Noise depends upon gain setting PGA.
MAXAV
Offset (Input Referred) Maximum Gain
Rev. 1.00
XRD9855/L55
ELECTRICAL CHARACTERISTICS XRD9855 Unless otherwise specified: DVDD 5.0V, Pixel Rate 18MSPS, 3.8V, 0.5V
Symbol Parameter Min. Typ. Max. Unit Conditions
Digital Timing TPW1 TPW2 TPIX TRST TSET Latency Power Supplies DVDD IDD25 IDDPD Analog Supply Voltage Digital Output Supply Voltage Supply Current Supply Current 25MHz Power Down Supply Current Always DVDD 5.0V 25MHz STBY1 STBY2 Data Valid Delay Pulse Width Pulse Width Pixel Period Sample Black Aperture Delay 4.5V 5.5V, Temperature -40°C 85°C range Sample Video Aperture Delay 4.5V 5.5V, Temperature -40°C 85°C range RSTCCD Switch Delay 4.5V 5.5V, Temperature -40°C 85°C range Shift Clock Period Shift Register Setup Time Pipeline Delay cycles
Rev. 1.00
XRD9855/L55
ELECTRICAL CHARACTERISTICS XRD98L55 Unless otherwise specified: DVDD 2.7V, Pixel Rate 18MSPS, 2.07V, 0.27V
Symbol Parameter Min. Typ. Max. Unit Conditions
Performance CDSVIN Input Range Small Signal Bandwidth (-3dB) Slew Rate Feed-through (Hold Mode) V/µs 400mV Step Input. Pixel (Black Level Video Level)
Parameters AVMIN AVMAX Minimum Gain Maximum Gain Resolution Gain Error bits Transfer function linear steps (1LSB 0.125dB). maximum minimum gain setting.
Parameters (Measured Through TESTVIN) DNL25 Resolution Sample Rate Differential Non-Linearity Differential Non-Linearity Zero Scale Error Full Scale Error Input Range +0.75 +0.9 bits MSPS swing from VDD. Input range limited output swing PGA. >VRB >VRB 18MHz sample rate. 25MHz sample rate. Measured relative VRB.
VREF
Reference Voltage Bottom Reference Voltage Differential Reference Voltage Ladder Resistance
2.07
Ohms
0.27 VDD-1
Self Bias Self Bias
1.30
0.27
connected VRBO. connected VRTO.
2.07
Rev. 1.00
XRD9855/L55
ELECTRICAL CHARACTERISTICS XRD98L55 (CONT'D) Unless otherwise specified: DVDD 2.7V, Pixel Rate 18MSPS, 2.7V, 0.27V
Symbol Parameter Min. Typ. Max. Unit Conditions
System Specifications DNLSMIN SMAX INLSMIN INLSMAX MINAV Minimum Gain Maximum Gain Minimum Gain Maximum Gain Offset (Input Referred) Minimum Gain 0.75 0.75 error dominated CDS/PGA linearity. error dominated CDS/PGA linearity. Offset defined input pixel value -0.5 required cause output switch from "Zero scale" "Zero scale 1LSB". Offset measured after calibration. MAXAV Offset (Input Referred) Maximum Gain Zero scale code offset register. Offset depends gain code. MAXAV MINAV Digital Inputs Digital Outputs Digital Output High Voltage Digital Output Voltage High-Z Leakage DVDD-0.5 While sourcing 2mA. While sinking 2mA. OE=1 STBY1= STBY2 Output between Digital Input High Voltage Digital Input Voltage Leakage Current Input Capacitance Input Between VDD. Input Referred Noise Maximum Gain Input Referred Noise Minimum Gain mVrms mVrms Noise depends upon gain setting PGA. Noise depends upon gain setting PGA.
Rev. 1.00
XRD9855/L55
ELECTRICAL CHARACTERISTICS XRD98L55 (CONT'D) Unless otherwise specified: DVDD 2.7V, Pixel Rate 18MSPS, 2.07V, 0.27V
Symbol Parameter Min. Typ. Max. Unit Conditions
Digital Timing TPW1 TPW2 TPIX TRST TSET Latency Data Valid Delay Pulse Width Pulse Width Pixel Period Sample Black Aperture Delay 2.7V 3.6V, Temperature -40°C 85°C range Sample Video Aperture Delay 2.7V 3.6V, Temperature -40°C 85°C range RSTCCD Switch Delay 2.7V 3.6V, Temperature -40°C 85°C range Shift Clock Period Shift Register Setup Time Pipeline Delay cycles
Power Supplies DVDD IDD25 IDDPD Analog Supply Voltage Digital Output Supply Voltage Supply Current Supply Current 25MHz Power Down Supply Current Always DVDD 25MHz STBY1 STBY2
ABSOLUTE MAXIMUM RATINGS +25°C unless otherwise noted)1,
Notes: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation above this specification implied. Exposure maximum rating conditions extended periods affect device reliability. input which value outside absolute maximum ratings should protected Schottky diode clamps (HP5082-2835) from input supplies. inputs have protection diodes which will protect device from short transients outside supplies less than 100mA less than 100µs. refers AVDD refers AGND DGND.
Rev. 1.00
Inputs Outputs Storage Temperature
+0.5 -0.5V +0.5 -0.5V +0.5 -0.5V +0.5 -0.5V -65°C 150°C
+7.0V
Lead Temperature (Soldering seconds) 300°C Maximum Junction Temperature 150°C Package Power Dissipation Ratings (TA= +70°C) TQFP 54°C/W 2000V
XRD9855/L55
SYSTEM DESCRIPTION Correlated Double Sample/Hold (CDS) Programmable Gain Amplifier (PGA); Gain [7:0] function block, shown Figure sense voltage difference between black level video level each pixel. fully differential. output converted single ended signal, then ADC. IN_POS (CDS non-inverting input) should connected, capacitor, "Common" voltage. This typically CCD, could also Reference output ground. IN_NEG (CDS inverting input) should connected, capacitor, output signal.
During black reference phase each pixel SDRK switches turned shorting PGA1 inputs VDD. sampling edge turns SDRK switches, sampling black reference voltage capacitors During video phase each pixel SPIX switches turned difference between pixel reference level video level transmitted through capacitors converted fully differential signal differential amplifier PGA1. sampling edge turns SPIX switches, sampling pixel value capacitors
External Coupling Capacitors Supply Signal
Gain Register
SDRK RSTCCD In_Pos In_Neg PGA1
SPIX
PGA2
CLAMP Offset Calibration VBIAS~0.8 XRD9855/XRD98L55 Enable Code
Figure Block Diagram
Rev. 1.00
XRD9855/L55
RSTCCD (Internal Signals) SDRK SPIX PGA1 Output PGA2 Output ADCLK Hold Track
Figure Timing Diagram Clocks Internal Signals, CLK_POL
PGA1 provides gains 0dB, 16dB (1x, 2.5x, 6.25x). gain transitions occur gain codes 128d (40h 80h). PGA2 provides gain from 22dB 12.5x) with 0.125dB steps. Figure shows measured gain Gain Code. combined blocks provide programmable gain range 32dB. minimum gain (code 00h) 1dB. maximum gain (code FFh) 38dB 1dB. following equation used compute gain from gain code:
18MHz 3.0V 2.3V 0.3V 25°C
Gain [dB]
code Gain[dB]
where code between 255. device mismatch gain steps codes 6364 127-128 monotonic. maximum error within 0.25dB.
Gain Code
Figure Gain Gain Code
Rev. 1.00
XRD9855/L55
Analog-to-Digital Converter analog-to-digital converter based upon twostep sub-ranging flash converter architecture with built track hold input stage. conversion controlled internally generated signal, ADCLK (see Figure tracks output CDS/ while ADCLK high holds when ADCLK low. This allows maximum time CDS/PGA output settle final value before being sampled. conversion then performed parallel output updated, after cycle pipeline delay, rising edge RSTCCD. pipeline delay entire XRD9855/XRD98L55 clock cycles. references generated internally external voltages applied. internal reference values resistor divider between GND. enable internal reference, connect VRTO connect VRBO VRB. maximize performance XRD9855/ XRD98L55, internal references should used decoupled GND. Although internal references have been maximize performance CDS/PGA channel, some applications require other reference values. external references, drive pins directly with desired voltages, leave VRBO VRTO open (NC). parallel output equipped with high impedance capability, controlled outputs enabled when low.
Automatic Offset Calibration, Offset [7:0] maximum color resolution dynamic range, this part uses digital offset calibration system compensate external offset signal well internal offsets CDS, ADC. calibration performed every line when outputs Optical Black pixels, please section Line Timing. Calibration logic compares output value stored serial port offset register, increments decrements offset adjust make code equal code offset register. every line, first adjustment requires pixels, then pixels subsequent adjustments. offset register bits wide. MSBs added when compared 10-bit code. After power-up part require adjustments converge proper offset. These adjustments made over many lines. example, with optical black pixels line, calibration will make adjustments line, initial convergence will require most lines.
Calibration Range (mV)
Gain Setting (code)
Graph XRD9855 Typical Vdrk (CCD Offset) Calibration Range
Rev. 1.00
XRD9855/L55
IN_NEG
IN_POS
DB[9:0]
Offset Adjust
Up/Down Counter
Offset
Enable
EnableCal
State Machine
ADCLOCK
Figure Automatic Offset Calibration Loop
Manual Global Offset, [1:0] some systems black level offset larger than Automatic Offset Calibration Range. XRD9855 provides user programmable global offset adjustment which adds automatic offset calibration. global offset applied input, it's input referred value does change with gain code, Figure magnitude global offset controlled bits V[1:0] mode register. (See Table
Input
DB[9:0]
V[1:0] Manual Global Offset
Automatic Offset Calibration
Figure Manual Global Offset Automatic Offset Calibration Serial Interface
V[1]
V[0]
Offset 25mV (default) 50mV 75mV
Table Manual Global Offset Programming
three wire serial interface, (LOAD, SCLK, SDI), used program gain register, Calibration offset register, Mode control register, Aperture delay register. shift register bits long. first bits loaded address bits that determine which four registers update. following eight bits data bits (MSB first, last). When LOAD high SCLK internally disabled. Since SCLK gated LOAD, SCLK continuously running clock signal, this will increase system noise. enable shift register LOAD must pulled low. data strobed into shift register rising edges SCLK. When LOAD signal goes high data bits will written register selected address bits (see Figure
Rev. 1.00
XRD9855/L55
ADDRESS (MSB)
DATA (LSB)
TSET=10ns min. SCLK
Data Shifts Rising Edges
TSC=50ns min. TSET=10ns min. LOAD TSET=10ns min. Load Internal Register
Figure Serial Port Timing Diagram
Address Name Gain Offset Mode Delay Gain[7] Offset[7] V[1] Dp[2] Gain[6] Offset[6] V[0] Dp[1] Gain[5] Offset[5] Dp[0] Data Gain[4] Offset[4] Dd[2] Gain[3] Offset[3] Test3 Dd[1] Gain[2] Offset[2] Test2 Dd[0] Gain[1] Offset[1] Dr[1] Gain[0] Offset[0] Reset Dr[0]
Table Serial Interface Register Address
Gain [7:0]
minimum gain (6dB) maximum gain
Table Gain Register Assignment
Offset [7:0] minimum offset code typical offset code maximum offset code
Table Offset Register Assignment
Note: Indicates default value
Rev. 1.00
XRD9855/L55
V[1:0]
offset 25mV offset* 50mV offset 75mV offset
Clamp only* Clamp
RSTCCD* RSTCCD
Test3
TestVin off*
Test2
test off*
auto detect* manual
Reset
normal* reset
TestVin factory test
Table Mode Register Assignment
Dp[2:0] delay delay
[2:0] delay delay
Dr[1:0] RSTCCD delay RSTCCD delay
Table Delay Register Assignment
Note: Indicates default value
SHP, RSTCCD Signals, input XRD9855/XRD98L55 determines when Black level each pixel sampled. CLK_POL=high timing mode, black level sampled falling edge SHP. CLK_POL=low timing mode, black level sampled rising edge SHP. sampling edge should positioned that samples pixel black level stable repeatable point. black level should sampled after output time settle from reset pulse before output transitions video level (see Figure Aperture delay needs taken into consideration when positioning sampling edge (see Figure This aperture delay time from sampling edge time pixel black level actually sampled CDS. correct positioning will prior where black level adequately settled. This typically just before signal starts transition video level. input XRD9855/XRD98L55 determines when Video level each pixel sampled. CLK_POL=high timing mode, video level sampled falling edge SHD. CLK_POL=low timing mode, video level sampled rising edge SHD.
Rev. 1.00
XRD9855/L55
sampling edge should positioned that samples pixel video level stable repeatable point. video level should sampled after output settled from black level before output transitions reset pulse. Aperture delay needs taken into consideration when positioning sampling edge (see Figure This aperture delay time from sampling edge time pixel video level actually sampled CDS. correct positioning will prior where video level adequately settled.
RSTCCD intended overlap reset pulse each pixel. This intended eliminate reset pulse transients from getting into XRD9855's circuitry. Positioning RSTCCD signal that overlaps signal reset pulse always practical timing generators being used frequency which running. most critical thing remember RSTCCD that high when sampling either black level video level.
Reset Pulse RSTCCD Switch Turn
RSTCCD Switch Turn Pixel Black Level Sample Point Pixel Video Level Sample Point
Signal
RSTCCD
Figure Timing Diagram (CLK_POL
Rev. 1.00
XRD9855/L55
Pixel
Signal Sample Pixel Black Level Sample Pixel Video Level
RSTCCD DB[9:0] (Output) Data Data Data Data Data
Figure Conversion Timing Diagram Showing Pipeline Delay (CLK_POL
Rev. 1.00
XRD9855/L55
Clock Polarity CLK_POL used determine polarity clocks (SHD, SHP, CLAMP). Figures Tables
Event RSTCCD RSTCCD SHP/SHD Action Disconnect Inputs from Reset Noise Connect Inputs Track Black Level Hold Black Level Track Video Level Hold Video Level Action Event RSTCCD RSTCCD SHP/SHD Clamp High Action Disconnect Inputs from Reset Noise Connect Inputs Track Black Level Hold Black Level Track Video Level Hold Video Level Action Activate Restore Clamp
Clamp High Activate Restore Clamp Enable_Cal Activate Offset Calibration High
Enable_Cal Activate Offset Calibration
Table Timing Event Description Table Valid CLK_POL=1, M2=0
Table Timing Event Description Table Valid CLK_POL=0, M2=0
Line Vertical Shift Active Video Pixels pixels Dummy Pixels
Line Active Video Pixels
Signal EnableCal Clamp RSTCCD
Note: Optically Black Shielded pixels.
Figure Line Timing with CLK_POL
Rev. 1.00
XRD9855/L55
Line Active Video Pixels Pixels
Line Vertical Shift Dummy Pixels Active Video Pixels
Signal EnableCal Clamp RSTCCD CLK_POL=Low
Note: Optically Black Shielded pixels.
Figure Line Timing with CLK_POL
RSTCCD Pulse Timing, help simplify timing required drive XRD9855 have included timing mode which does require active signal RSTCCD. this timing, timing mode register must high. this timing mode, RSTCCD must kept low. changes required timing signals. polarity SHP, Clamp still controlled CLK_POL pin. digital outputs change sampling edge (see Figure 12). This mode used with both XRD4460 timing XRD9853 timing described Line Timing section.
Signal
Pixel
RSTCCD
Data Data Data Data Data
DB[9:0]
Figure XRD9855 Timing RSTCCD Pulse, M2=1 CLK_POL=1, RSTCCD=0
Rev. 1.00
XRD9855/L55
Dr[0] RSTCCD Aperture Delay TRST (typ) (default) 11ns 15ns
Programmable Aperture Delays Dp[2:0], Dd[2:0], Dr[1:0] help fine tune pixel timing, XRD9855 allows system adjust aperture delays associated with (TBK), (TVD) RSTCCD (TRST) programming Aperture Delay serial port register. power these three aperture delays their minimum values. aperture delay bits Dp[2:0]. Each adds approximately delay. aperture delay bits Dd[2:0]. Each adds approximately delay. RSTCCD aperture delay bits Dr[1:0]. Each adds approximately delay.
Dr[1]
Table Programmable RSTCCD Delays
Line Timing beginning and/or every line there number Optical black pixels. XRD9855 uses output from these pixels Restore Clamp Black Level Offset Calibration functions. These functions controlled Clamp and/or EnableCal pins. XRD9855 designed compatible with Clamp Only timing XRD4460 Clamp EnableCal timing XRD9853. power chip will automatically detect which timing being used make necessary internal adjustments. EnableCal high when Clamp active, then "Clamp Only" timing selected (M3=0). EnableCal when Clamp active, then "Clamp Cal" timing selected (M3=1). required, automatic detection function disabled through serial port, chip forced into timing modes programming mode register bits Clamp Only Timing (XRD4460 compatible) M1=1, M3=0 this mode EnableCal held high, Clamp activated during Optical Black pixels. Clamp signal used trigger one-shot which controls internal restore switch calibration logic. restore switch turned pixels after Clamp activated. Then Calibration logic enabled runs until Clamp deactivated. chip forced into this timing mode programming Mode control register bits M1=1 M3=0.
Dp[2]
Dp[1]
Dp[0]
Aperture Delay (typ) (default) 10ns 12ns 14ns 16ns 18ns 20ns
Table Programmable Delays
Dd[2]
Dd[1]
Dd[0]
Aperture Delay (typ) (default) 11ns 13ns 15ns 17ns 19ns
Table Programmable Delays
Rev. 1.00
XRD9855/L55
Line Signal Pixels
Line Dummy Pixels Signal Pixels
Pixels
Vertical Shift
(Horizontal Clocking Off)
Signal EnableCal Note: Optically Black Shielded pixels.
Minimum Pixels
Clamp Internal Restore Switch Internal Calibrate RSTCCD
Pixels
Figure Clamp Only Line Timing CLK_POL=1, EnableCal=1, M1=1, M3=0, M2=0
Clamp Only Mode
Input DB[9:0]
Restore Switch Bias Clk_Pol Clamp EnableCal Control Logic
Offset Calibration
Figure Clamp Only Mode (XRD4460 Compatible) M1=1, M3=0
Rev. 1.00
XRD9855/L55
Optical Black Pixels
(Shielded)
Dummy Optical Black Pixels
Active Video Pixels
Figure Typical Array with Active Pixels Optically Black Pixels
Clamp EnableCal Timing (XRD9853 Compatible) M1=1, M3=1 this mode EnableCal must active during large number Optical Black pixels (usually each line), Clamp should active during Dummy pixels (usually beginning each line). EnableCal (always active high) directly controls calibration logic. Clamp (polarity determined CLK_POL) controls only restore switch input. EnableCal Clamp must active same time. chip forced into this timing mode programming Mode control register bits M1=1 M3=1.
Line
Line
Signal Pixels
Pixels
Vertical Shift
(Horizontal Clocking Off)
Dummy Pixels
Signal Pixels
Signal EnableCal Clamp Min. Pixels RSTCCD Note: Optically Black Shielded Pixels.
Min. Pixels
Figure Clamp EnableCal Timing, CLK_POL=1, M1=1, M3=1, M2=0
Rev. 1.00
XRD9855/L55
Clamp EnableCal Mode Input DB[9:0]
Restore switch bias Clk_Pol Clamp EnableCal
Offset Calibration
Figure Clamp Enable Mode (XRD9853 Compatible), M1=1, M3=3
Stand-by Mode (Power Down) STBY1 STBY2 pins used chip into Stand-by Power down mode. this mode sampling conversion stops, digital outputs into high impedance mode, power supply current will drop less than 50µA. most applications STBY1 STBY2 should connected together treated single control pin. application uses TestVin access output input then STBY1 STBY2 must separately controlled, truth table below.
STBY2
STBY1
CDS/
Clock Inputs
Digital Outputs High-z High-z
Table Stand-by Truth Table
Rev. 1.00
XRD9855/L55
Default 00000000 00001000 Notes minimum gain code offset Clamp only RSTCCD required Automatic timing detect Test modes Test modes reset will reset itself minimum delay minimum delay minimum delay
Chip Reset chip Internal Power-On-Reset function ensure internal control registers start known state. Pulling Reset high writing logic Mode Registers reset will also reset chip Power-up default conditions.
Register Gain[7:0] OS[7:0] V[1:0] Test3 Test2 Reset Dp[2:0] Dd[2:0] Dr[1:0]
Table Reset Conditions
Using TestVin (Pin TestVin allows access input ADC, used monitor CDS/PGA output. TestVin accesses input node through switch (see Figure 18). This switch controlled Bit3 serial port Test register. When TEST3 mode register high, switch "ON" TestVin used access input/ output. When TEST3 mode register low, switch "OFF" TestVin disconnected from input/PGA output.
TestVin auxiliary input force STBY2=low STBY1=high. This will disable CDS/PGA leave operating. M2=0, clock generated from RSTCCD (See Figure 19). M2=1, clock generated from (See Figure 20).
Rev. 1.00
XRD9855/L55
TestVin
Figure Using TestVin Access Output Input
Mode Reg. TestVin Normal
V[1]
V[0]
Test3
Test2
Reset
Table Serial Port Data TestVin
Signal
Signal
RSTCCD
RSTCCD
Clock (internal)
Track
Hold
Clock (Internal)
Track
Hold
Data
Data
Figure Clock Generation, CLK_POL=1, M2=0
Figure Clock Generation, CLK_POL=1, M2=1
Rev. 1.00
XRD9855/L55
Digital Output Power Supplies DVDD DGND pins supply power digital output drivers pins DB[9:0], UNDER, OVER. DVDD isolated from voltage level less than equal VDD. This allows digital outputs interface with advanced digital ASICs requiring reduced supply voltages. example 3.3V, while DVDD 2.5V. Systems which same voltage level both analog digital power supplies take advantage isolated DVDD DGND pins reduce system noise. output drivers create large supply transients they switch. Therefore DVDD DGND should routed separately from analog avoid injecting this noise into analog power network (see Figure 21.)
Power Supply Sequencing There power supply sequencing issues DVDD XRD9855/98L55 driven from same supply. When DVDD driven separately, must come same time before DVDD, down same time after DVDD. power supply sequencing this case followed, then damage occur product current flow through source-body junction diodes between DVDD VDD. external diode (50822235) layed close converter from DVDD prevents damage from occurring when power cycled incorrectly.
Note: must greater than equal DVDD source-body diodes will forward based.
DVDD
Source-Body Junction Diode Between DVDD Output Register Digital Output Source-Body Junction Diode Between DGND
DGND
Figure DVDD DGND Digital Output Power Supplies, DVDD
Rev. 1.00
XRD9855/L55
General Power Supply Board Design Issues pins, other than DGND, tied substrate should connected directly analog ground plane under XRD9855/XRD98L55. VDD's should supplied from noise, well filtered regulator which derives power supply voltage from power supply. pins analog power supplies should locally decoupled nearest with 0.1µF, high frequency capacitor. DVDD DGND power supplies digital outputs should locally decoupled. DVDD DGND should connected same power supply network digital ASIC which receives data from XRD9855/XRD98L55. general, traces leading XRD9855/ XRD98L55 should short possible minimize signal crosstalk high frequency digital signals from feeding into sensitive analog inputs. inputs, In_Pos In_Neg, should routed fully differential signals should shielded matched. Efforts should made minimize board leakage currents In_Pos In_Neg since these nodes coupled from XRD9855/ XRD98L55. digital output traces should short possible minimize capacitive loading output drivers (see Figure 22.)
5V/3V Regulator In_Neg In_Pos DB[9:0] DVDD DVDD Digital ASIC DGND 5V/3V Regulator
DGND
XRD9855/XRD98L55 AGND DGND
Figure XRD9855/XRD98L55 Power Supply Connections
Application Note increasing Gain code (80h) higher causes larger than expected offset increase digital output codes, problem limited Automatic Offest Calibration range. This problem solved increasing Global Offset code, V[1:0], Mode Register. default V[1:0] (binary). increasing V[1:0] V[1:0]
Rev. 1.00
XRD9855/L55
Ground
Signal
0.01µF
Serial Interface
0.01µF
0.1µF
0.01µF
In_Pos
CLAMP
In_Neg
LOAD
VRBO
VRTO
SCLK RESET STBY2 STBY1 Test from Clock Signal Generator
From Clock Signal Generator
RSTCCD CLK_POL SYNC UNDER XRD9855/XRD98L55
0.1µF
EnableCal OVER
0.1µF
DGND
DVDD
Digital Data
Figure XRD9855/XRD98L55 Application Schematic CLK_POL=0
Rev. 1.00
DVDD
0.1µF
XRD9855/L55
Rev. 1.00
XRD9855/L55
Notes
Rev. 1.00
XRD9855/L55
NOTICE EXAR Corporation reserves right make changes products contained this publication order improve design, performance reliability. EXAR Corporation assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained here only illustration purposes vary depending upon user's specific application. While information this publication been carefully checked; responsibility, however, assumed accuracies. EXAR Corporation does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless EXAR Corporation receives, writing, assurances satisfaction that: risk injury damage been minimized; user assumes such risks; potential liability EXAR Corporation adequately protected under circumstances. Copyright 1998 EXAR Corporation Datasheet December 1998 Reproduction, part whole, without prior written consent EXAR Corporation prohibited.
Rev. 1.00

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