Block Product Guide v1.3 RFB915 knowledge required Fully assemble
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BLUECHIP COMMUNICATION
Block Product Guide v1.3 RFB915
knowledge required Fully assembled tested units 28mm 28mm 3.3mm size Surface mountable application board components board Very external component count input output external antenna 2.5V 3.4V operation lines required operation 9.6kbit (19.2kbaud Manchester encoded) data rates Software driver supplied Microchip series
Hovfaret 17B, N-0275 Oslo, Norway. Tel: Fax: E-mail: post@bluechip.no Orgnr. www.bluechip.no
BLUECHIP COMMUNICATION
RSSI XOSCIN DIGVDD PUEXT DATA RFVDD IFVDD
description
Ground plane connection Analog received signal strength indicator output (optional use) Lock detect output (optional use) Ground plane connection Crystal oscillator input (optional use) Digital circuitry power External power down (0=power down) directional data Control register data clock Control register data input, programming block Ground plane connection input output power Ground plane connection TX/RX switch control input power
Hovfaret 17B, N-0275 Oslo, Norway. Tel: Fax: E-mail: post@bluechip.no Orgnr. www.bluechip.no
BLUECHIP COMMUNICATION
Vdd=2.5-3.4V, T=25°C, unless otherwise specified Parameter Conditions Overall Operating frequency Supply voltage Power down current Logic high input, Logic input, DataIXO, logic high output (Voh) Ioh=-500µA DataIXO, logic output (Vol) Iol= 500µA LockDet, logic high output (Voh) Ioh=-100µA LockDet, logic output (Vol) Iol= 100µA Clock/Data frequency Clock/Data duty-cycle Data setup clock (rising edge) Operating temperature range section lock time with switch time fOUT =915MHz Transmit section Output power RLOAD=50, Vdd=3.0V Transmit data rate Freq. deviation modulation rate ratio Unfiltered Current consumption transmit mode dBm, RLOAD=50 fIN=915MHz Receive section Receiver sensitivity BER=10-3 Input compression level Input RSSI dynamic range RSSI output voltage -100dBm -30dBm Adjacent channel rejection 200kHz channel spacing Blocking immunity (1MHz) Receiver settling time Current consumption receive mode
Min.
Typ.
Max.
Unit kbauds
Vdd-0.3 Vdd-0.25 0.25 19.2 -103
Hovfaret 17B, N-0275 Oslo, Norway. Tel: Fax: E-mail: post@bluechip.no Orgnr. www.bluechip.no
BLUECHIP COMMUNICATION
Application notes
DATA Bi-directional data. Modulation applied therefore modulation cannot have component. Some kind coding needed ensure that modulation free, e.g. Manchester code block code. With Manchester code rate half baud rate, with 3B4B block code rate baud rate Connection Microcontroller capture/ compare allows clock recovery sync routines supplied software. should input after programming block mode, prior starting transmission data. This gives fastest times transmit. settling time P.A. stage ramp line should input after completion keying data, prior loading control word block. recommended that DIGVDD divided from IFVDD RFVDD joined common point. Block lock detector feature that indicates whether lock not. logic high means that lock. reference manual BCC918. Received Signal Strength Indicator (RSSI) RSSI provides output voltage proportional strength input signal. Impedance approximate 50k. reference manual BCC918. PUEXT should connected line. After power should held while loading control word first time. alternative, lines available, connect PUEXT resistor capacitor GND. After power applied, control word should clocked during time PUEXT logic levels (30% VDD). time constant should chosen match data clock rate from Microcontroller. Further loading control words done normal manner.
DIGVDD
RSSI
PUEXT
Hovfaret 17B, N-0275 Oslo, Norway. Tel: Fax: E-mail: post@bluechip.no Orgnr. www.bluechip.no
BLUECHIP COMMUNICATION
layout
Keep digital lines away from side with Xtal. Keep ground plane areas large possible. Keep track connector/ antenna short possible. best strip line solution. must "clean" good performance. RS232 converter used voltage regulator they introduce spikes VDD. Avoid switch mode power supplies possible linear regulator after them. final type approval complete product, there must detection voltage condition that microcontroller places block standby, otherwise lock below 2.4V there could unintentional radiation outside intended band. Current samples blocks have dimensions inch inch. Blue Chip Communication plans reduce these dimensions 0.99inch 0.99 inch future production runs. This optimise production allow standardised packaging transport material. footprint described below will accept current future versions blocks.
Hovfaret 17B, N-0275 Oslo, Norway. Tel: Fax: E-mail: post@bluechip.no Orgnr. www.bluechip.no
BLUECHIP COMMUNICATION
Interfacing microcontrollers operating higher voltage levels
Standard blocks designed operate from 2.7v 3.3V. Some Microcontrollers require higher operating voltages maximum clock rates. circuit below allows interfacing block with supply Microcontroller with supply. resistors form voltage divider logic levels from Microcontroller. detects logic high level inverted signal converted levels RX_EN held during state standby mode transmit, together with internal 40k.
R1,R2,R3,R4,R5, general purpose bipolar transistor N.B. resistor values 3.3V interface Data internal impedance approx.
Hovfaret 17B, N-0275 Oslo, Norway. Tel: Fax: E-mail: post@bluechip.no Orgnr. www.bluechip.no
BLUECHIP COMMUNICATION
Programming
two-line used program circuit; lines being REG. 2-line serial interface allows control over frequency dividers selective powering Synthesizer circuit blocks. After power PUEXT should held while loading control word first time. When control Table allocation
Ref2 Ref1 Ref0 ByLNA Cpmp1 Ref6 Cpmp0 Ref5 Ref4 Ref3
word been loaded, PUEXT brought high rest power cycle. interface consists 80-bit programming register. Data entered RegIn line with most significant first. first entered called last p80. bits programming register arranged shown table1.
Table description
Name ByLNA Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0 Cpmp1 Cpmp0 Description frequency divider bits frequency divider bits frequency divider bits frequency divider bits frequency divider bits frequency divider bits gain setting power amplifier pa2, pa1, lowest output power pa2, pa1, highest output power gain control power amplifier buffer,1=high gain Noise Amplifier (LNA) bypassed reference settings lock detector 0's: highest reference 1's: lowest reference
charge pump setting:
Cpmp1=0, Cpmp0=0 ±125uA Cpmp1=0, Cpmp0=1 ±500uA Cpmp1=1, Cpmp0=0 controlled (LD) LD=0: ±500uA, LD=1: ±125uA Cpmp1=1, Cpmp0=1 same previous current ±500µA. receive mode transmit mode power power down (When Pu=1, power down controlled PuExt)
Hovfaret 17B, N-0275 Oslo, Norway. Tel: Fax: E-mail: post@bluechip.no Orgnr. www.bluechip.no
BLUECHIP COMMUNICATION 80bit control word first read into shift-register, then loaded into parallel register transition signal (positive negative) when signal high. circuit then goes directly into specified mode (receive, transmit, etc.).
where fXCO crystal oscillator frequency 10MHz. Example1: 905MHz
Ref6 Ref0 Ref5 Cpmp1 Ref4 Cpmp0 Ref3 Ref2 ByLNA Ref1
Figure Timing CLK, internal Load_int PA_C signals first time after power second last clocked into first shift register (`1'). last clocked into first shift register (`1'). transition signal generates internal load pulse that loads control word into parallel register. circuit enters mode this case Tx-mode). circuit stabilizes mode. should brought when clock signal goes low. When clock signal power amplifier (PA) turned slowly order minimize spurious components output signal. sure lock before turned should turned after negative transition clock signal should come minimum time period comparison frequency after internal load pulse generated. power amplifier fully turned control word entered into first register. transition signal when high will turn power amplifier off. When power amplifier turned off, internal load pulse generated. should brought high when off. control word loaded into parallel register circuit enters mode this case power down mode). must after internal load pulse generated. long transitions avoided when high, control word clocked into first register time without affecting operation transceiver. values calculated from formula:
Binary form: (MSB left):
011011 011011 000010001111 000010001111 0001101010 0001101010 011110000000001100000011 011011 011011 000010001111 000010001111 0001101010 0001101010 011110000000001100000001
Example2: 921MHz
Ref6 Ref0 Ref5 Cpmp1 Ref4 Cpmp0 Ref3 Ref2 ByLNA Ref1
Binary form: (MSB left):
001110 001110 000010000111 000010000111 0001100100 0001100100 011110000000001100000011 001110 001110 000010000111 000010000111 0001100100 0001100100 011110000000001100000001
Hovfaret 17B, N-0275 Oslo, Norway. Tel: Fax: E-mail: post@bluechip.no Orgnr. www.bluechip.no
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