MACH465-12/15/20 High-Density CMOS Programmable Logic DISTIN

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MACH465-12/15/20 High-Density CMOS Programmable Logic DISTIN

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COM'L: -12/15/20
MACH465-12/15/20
High-Density CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
pins PQFP JTAG, 5-V, in-circuit programmable IEEE 1149.1 JTAG testing capability macrocells 83.3 fCNT Inputs with pull-up resistors Outputs flip-flops Macrocell flip-flops Input flip-flops
Advanced Micro Devices
product terms function, with Flexible clocking Four global clock pins with selectable edges Asynchronous mode available each macrocell "PAL34V16" blocks Input output switch matrices high routability Fixed, predictable, deterministic delays Zero-hold-time input register option Peripheral Component Interconnect (PCI) compliant
GENERAL DESCRIPTION
MACH465 member AMD's high-performance CMOS MACH family. This device approximately times macrocell capability popular PAL22V10, with significant density functional features that PAL22V10 does provide. MACH465 consists blocks interconnected programmable central switch matrix. central switch matrix connects blocks each other input pins, providing high degree connectivity between fully-connected blocks. This allows designs placed routed efficiently. Routability further enhanced input switch matrix output switch matrix. input switch matrix provides input signals with alternative paths into central switch matrix; output switch matrix provides flexibility assigning macrocells pins. MACH465 macrocells that configured synchronous asynchronous. This allows designers implement both synchronous asynchronous logic together same device. types design mixed proportion, since selection each macrocell affects only that macrocell. product terms function assigned. possible allocate some product terms away from macrocell without losing that macrocell logic generation. MACH465 macrocell provides either registered combinatorial outputs with programmable polarity. registered configuration chosen, register configured D-type, T-type, J-K, help reduce number product terms used. flip-flop also configured latch. register type decision made designer software. macrocells connected cell through output switch matrix. output switch matrix makes possible make significant design changes while minimizing risk pinout changes.
Publication# 17470 Rev. Issue Date: 1995
Amendment
BLOCK DIAGRAM
Block I/O8-I/O15 Block I/O0-I/O7 CLK0-CLK3 Block I/O120-I/O127 Block I/O112-I/O119
Cells Clock Generator Output Switch Matrix Macrocells Input Switch Matrix Logic Array Logic Allocator Cells Clock Generator Clock Generator Output Switch Matrix Macrocells Input Switch Matrix Logic Array Logic Allocator Cells Output Switch Matrix Macrocells Input Switch Matrix Clock Generator Cells Output Switch Matrix Macrocells Logic Array Logic Allocator
Logic Array Logic Allocator
Input Switch Matrix
Logic Array Logic Allocator Macrocells Output Switch Matrix Cells
Input Switch Matrix
Logic Array Logic Allocator Macrocells
Logic Array Logic Allocator Macrocells Clock Generator Clock Generator
Input Switch Matrix
Logic Array Logic Allocator Macrocells
Input Switch Matrix
Clock Generator
Output Switch Matrix Cells
Output Switch Matrix Cells
Clock Generator
Output Switch Matrix Cells
Central Switch Matrix
I/O104-I/O111 Block I/O96-I/O103 Block I/O88-I/O95 Block I/O80-I/O87 Block Cells Clock Generator Output Switch Matrix Macrocells Logic Array Logic Allocator Input Switch Matrix Input Switch Matrix
Block I/O16-I/O23 Block I/O24-I/O31 Block I/O32-I/O39 Block I/O40-I/O47
Cells Clock Generator Output Switch Matrix Macrocells Input Switch Matrix Logic Array Logic Allocator
Cells Clock Generator Output Switch Matrix Macrocells Input Switch Matrix Logic Array Logic Allocator Clock Generator
Cells Output Switch Matrix Macrocells Logic Array Logic Allocator Input Switch Matrix
Input Switch Matrix
Logic Array Logic Allocator Macrocells Output Switch Matrix Cells
Input Switch Matrix
Logic Array Logic Allocator Macrocells Output Switch Matrix Cells
Logic Array Logic Allocator Macrocells Clock Generator Clock Generator
Input Switch Matrix
Logic Array Logic Allocator Macrocells
Clock Generator
Output Switch Matrix Cells
Clock Generator
Output Switch Matrix Cells
I/O48-I/O55 Block
I/O56-I/O63 Block
I0-I13
I/O64-I/O71 Block
I/O72-I/O79 Block
Input Switch Matrix
17470D-1
MACH465-12/15/20
CONNECTION DIAGRAM View PQFP
Block Block Block Block
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 CLK0 CLK3 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112
I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47
TRST* I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 I/O96 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 ENABLE*
Block
Block
Block
Block
Block
Block
Block
Block
I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 CLK1 CLK2 I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 I/O79
Block
Block
Block
Block 17470D-2
DESIGNATIONS
Clock Ground Input Input/Output Supply Voltage
MACH465-12/15/20
ORDERING INFORMATION Commercial Products
programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank Shipped Trays
DEVICE NUMBER Generation, Macrocells, Pins
OPERATING CONDITIONS Commercial (0°C +70°C)
SPEED
PACKAGE TYPE 208-Pin Plastic Quad Flat Pack (PQR208)
Valid Combinations MACH465-12 MACH465-15 MACH465-20
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
MACH465-12/15/20
FUNCTIONAL DESCRIPTION
MACH465 consists sixteen blocks connected central switch matrix. There pins dedicated input pins feeding central switch matrix. These signals distributed sixteen blocks efficient design implementation. There also global clock pins. inputs pins have built-in pull-up resistors. While always good design practice unused pins high, pull-up resistors provide design security stability event that unused pins left disconnected.
These four signals available macrocells cells block, whether synchronous asynchronous mode. clock generator chooses four signals from eight possible signals given true complement versions four global clock signals.
Product-Term Array
MACH465 product-term array consists product terms logic use, eight product terms output enable use, product terms global block initialization. Each macrocell nominal allocation product terms logic, although logic allocator allows logic redistribution. Each individual output enable term. initialization product terms provide asynchronous reset preset synchronous-mode macrocells block.
Blocks
Each block MACH465 (Figure contains clock generator, 90-product-term logic array, logic allocator, macrocells, output switch matrix, cells, input switch matrix. central switch matrix feeds each block with inputs. This makes block look effectively like independent "PAL34V16". addition logic product terms, individual output enable product terms block initialization product term provided. Each individually enabled. flip-flops that synchronous mode within block initialized together either block initialization product terms.
Logic Allocator
logic allocator MACH465 takes logic product terms allocates them macrocells needed. Each macrocell driven product terms synchronous mode, product terms asynchronous mode. When product terms routed away from macrocell, possible route product terms away, which precludes macrocell logic generation; possible route only product terms away, leaving simple function generation. design software automatically configures logic allocator when fitting design into device. logic allocator also provides exclusive-OR gate. This gate allows generation combinatorial exclusiveOR logic, such comparison addition. allows registered exclusive-OR functions, such generation, implemented more efficiently. also makes possible emulate flip-flop types with D-type flip-flop. Register type emulation automatically handled design software. Table illustrates which product term clusters available each macrocell within block. Refer Figure cluster macrocell numbers.
Central Switch Matrix Input Switch Matrix
MACH465 central switch matrix input switch matrices each block. Each block provides internal feedback signals, registered input signals, signals input switch matrix. these signals, decoded signals provided central switch matrix input switch matrix. central switch matrix distributes these signals back blocks very efficient manner that provides high performance. design software automatically configures input central switch matrices when fitting design into device.
Clock Generator
Each block clock generator that generate four clock signals throughout block.
MACH465-12/15/20
Table Logic Allocation
Macrocell Available Clusters C10, C10, C11, C10, C11, C12, C11, C12, C13, C12, C13, C14, C13, C14, C14,
macrocells configured registered, latched, combinatorial. combination with logic allocator, registered configuration standard flip-flop types. macrocell provides internal feedback whether configured with without flipflop, whether macrocell drives cell. flip-flop clock depends mode selected macrocell. synchronous mode, block clocks generated Clock Generator used. asynchronous mode, additional choice either edge individual product-term clock available. Initialization handled part bank macrocells block initialization terms synchronous mode, individually asynchronous mode. synchronous mode, block product terms available each preset reset. swap function determines which product term drives which function. This allows initialization polarity compatibility with MACH series. asynchronous mode, product term used either drive reset preset.
Macrocell Output Switch Matrix
MACH465 macrocells, half which drive pins; this selection made output switch matrix. Each macrocell drive four cells. allowed combinations shown Table Please refer Figure macrocell numbers. Table Output Switch Matrix Combinations
Macrocell M10, M12, M14, I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Routable Pins I/O5, I/O6, I/O7, I/O0 I/O6, I/O7, I/O0, I/O1 I/O7, I/O0, I/O1, I/O2 I/O0, I/O1, I/O2, I/O3 I/O1, I/O2, I/O3, I/O4 I/O2, I/O3, I/O4, I/O5 I/O3, I/O4, I/O5, I/O6 I/O4, I/O5, I/O6, I/O7 Available Macrocells M10, M10, M11, M12, M10, M11, M12, M13, M14, M10, M11, M12, M13, M14, M15, M12, M13, M14, M15, M14, M15,
Cell
cell MACH465 consists three-state buffer input flip-flop. cell driven macrocells, selected output switch matrix. Each cell take input from eight macrocells. three-state buffer controlled individual product term. direct signal available input switch matrix, used desired.
JTAG Testing
JTAG commonly used acronym IEEE Standard 1149.1-1990. JTAG standard defines output pins, logic control functions, instructions. incorporated this standard into MACH465 device. JTAG standard developed means providing both board-level device-level testing. Details this feature found application note titled, Introduction JTAG Five-Volt Programming with MACH Devices, this data book.
MACH465-12/15/20
CLK0/I0 CLK1/I1 CLK2/I3 CLK3/I4
Clock Generator
Macrocell
Cell
I/O0
Macrocell
Macrocell
Cell
I/O1
Macrocell
Macrocell
Cell
I/O2
Macrocell
Macrocell
Cell
I/O3
Central Switch Matrix
Macrocell
Macrocell
Output Switch Matrix
Logic Allocator
Cell
I/O4
Macrocell
Macrocell
Cell
I/O5
Macrocell
Macrocell
Cell
I/O6
Macrocell
Macrocell
Cell
I/O7
Macrocell
Input Switch Matrix
17470D-3
Figure MACH465 Block MACH465-12/15/20
Five-Volt Programming
Another benefit from JTAG circuitry that derived ability JTAG port five-volt programming. This allows device soldered board before programming. Once device attached, delicate Plastic Quad Flat Pack, PQFP, leads protected from programming testing operations that could potentially damage them. Programming verification device done serially which ideal on-board programming since only requires Test Access Port, along with additional ENABLE* pin. Programming also done JTAG chain. Details this feature also found Introduction JTAG Five-Volt Programming with MACH Devices application note, this data book.
Zero-Hold-Time Input Register
MACH465 device zero-hold time (ZHT) fuse. This fuse controls time delay associated with loading data into cell registers latches MACH465 device. When programmed, fuse increases data path setup delays input storage elements, matching equivalent delays clock path. When fuse erased, setup time input storage element minimized. This feature facilitates doing worst-case designs which data loaded from sources which have zero) minimum output propagation delays from clock edges.
MACH465-12/15/20
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 +0.5 Output Voltage -0.5 +0.5 Static Discharge Voltage 2001 Latchup Current +70°C)
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed. Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 (Note Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT mA), 25°C (Note -100 -100 -160 Unit
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Notes: Total block should exceed These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 16-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled, reset. These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
MACH465-12 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output Setup Time from Input, I/O, Feedback Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock Output Product Term, Clock Width HIGH D-type T-type D-type T-type D-type T-type D-type T-type 52.6 50.0 58.8 55.6 62.5 HIGH Maximum Frequency Using Global Clock (Note External Feedback D-type T-type D-type Internal Feedback CNTA) Feedback (Note tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS tICO Setup Time from Input, I/O, Feedback Product Term Clock Latch Data Hold Time Using Product Term Clock Product Term Gate Output Product Term Gate Width (for transparent) HIGH (for HIGH transparent) Setup Time from Input, I/O, Feedback Global Gate Latch Data Hold Time Using Global Gate Gate Output Global Gate Width (for transparent) HIGH (for HIGH transparent) Input Register Clock Combinatorial Output T-type 66.7 62.5 83.3 76.9 83.3 Unit
tCOA tWLA tWHA
fMAXA
Maximum Frequency Using Product Term Clock (Note
External Feedback Internal Feedback CNTA) Feedback (Note
tCOS tWLS tWHS
Setup Time from Input, I/O, Feedback Global Clock Register Data Hold Time Using Global Clock Global Clock Output Global Clock Width
fMAXS
MACH465-12 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol tICS tWICL tWICH fMAXIR tIGO tIGOL tIGSA tIGSS tWIGL tARW tARR tAPW tAPR Input Register Clock Width Maximum Input Register Frequency 1/(t WICL WICH Parameter Description Input Register Clock Output Register Setup D-type T-type HIGH 83.3 Unit
Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Input Latch Gate Output Latch Setup Using Product Term Output Latch Gate Input Latch Gate Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable Input, I/O, Feedback Output Disable
Input Register with Standard-Hold-Time Option tPDL tSIR tHIR tSIL tHIL tSLLA tSLLS tPDLL Input, I/O, Feedback Output Through Transparent Input Latch Input Register Setup Time Input Register Hold Time Input Latch Setup Time Input Latch Hold Time Setup Time from Input, I/O, Feedback Through Transparent Input Latch Product Term Output Gate Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Gate Input, I/O, Feedback Output Through Transparent Input Output Latches
MACH465-12 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol tPDL tSIR tHIR tSIL
Parameter Description Input, I/O, Feedback Output Through Transparent Input Latch Input Register Setup Time Input Register Hold Time Input Latch Setup Time Input Latch Hold Time Unit
Input Register with Zero-Hold-Time Option
tHIL tSLLA
Setup Time from Input, I/O, Feedback Through Transparent Input Latch Product Term Output Gate Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Gate Input, I/O, Feedback Output Through Transparent Input Output Latches
tSLLS tPDLL
Notes: Switching Test Circuit back this Data Book test conditions. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. This parameter does apply flip-flops emulated mode since feedback path required emulation.
MACH465-12 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 +0.5 Output Voltage -0.5 +0.5 Static Discharge Voltage 2001 Latchup Current +70°C)
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed. Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 (Note Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT mA), 25°C (Note -100 -100 -160 Unit
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Notes: Total block should exceed These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 16-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled, reset. These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
MACH465-15/20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock Output (Note Product Term, Clock Width HIGH D-type External Feedback 1/(t fMAXA Maximum Frequency Using Product Term Clock (Note T-type Internal Feedback CNTA) Feedback (Note 1/(t D-type T-type D-type T-type 47.6 45.4 55.6 Global Clock Width tWHS External Feedback 1/(t fMAXS Maximum Frequency Using Global Clock (Note
D-type T-type 38.5 31.2 30.3 35.7 41.7 38.5 47.6 62.5
Unit
tCOA tWLA tWHA
Setup Time from Input, I/O, Feedback Global Clock Register Data Hold Time Using Global Clock Global Clock Output (Note
tCOS tWLS
47.6 66.6 62.5 83.3
HIGH D-type T-type D-type Internal Feedback CNTS) Feedback (Note 1/(t T-type
tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS tICO
Setup Time from Input, I/O, Feedback Product Term Clock Latch Data Hold Time Using Product Term Clock Product Term Gate Output (Note Product Term Gate Width (for transparent) HIGH (for HIGH transparent) Setup Time from Input, I/O, Feedback Global Gate Latch Data Hold Time Using Global Gate Gate Output (Note Global Gate Width (for transparent) HIGH (for HIGH transparent) Input Register Clock Combinatorial Output
MACH465-15/20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol Parameter Description tICS Input Register Clock Output Register Setup D-type T-type tWICL Input Register Clock Width tWICH fMAXIR tIGO tIGOL tIGSA tIGSS tWIGL tARW tARR tAPW tAPR tPDL tSIR tHIR tSIL tHIL tSLLA tSLLS tPDLL Maximum Input Register Frequency HIGH 1/(t WICL WICH 83.3 62.5 Unit
Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Input Latch Gate Output Latch Setup Using Product Term Output Latch Gate Input Latch Gate Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note
Input Register with Standard-Hold-Time Option Input, I/O, Feedback Output Through Transparent Input Latch Input Register Setup Time Input Register Hold Time Input Latch Setup Time Input Latch Hold Time Setup Time from Input, I/O, Feedback Through Transparent Input Latch Product Term Output Gate Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Gate Input, I/O, Feedback Output Through Transparent Input Output Latches
MACH465-15/20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol Parameter Description Input Register with Zero-Hold-Time Option tPDL tSIR tHIR tSIL
Unit
Input, I/O, Feedback Output Through Transparent Input Latch Input Register Setup Time Input Register Hold Time Input Latch Setup Time Input Latch Hold Time
tHIL tSLLA
Setup Time from Input, I/O, Feedback Through Transparent Input Latch Product Term Output Gate Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Gate Input, I/O, Feedback Output Through Transparent Input Output Latches
tSLLS tPDLL
Notes: Switching Test Circuit this Data Book test conditions. Parameters measured with outputs switching. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. This parameter does apply flip-flops emulated mode since feedback path required emulation.
MACH465-15/20 (Com'l)
TYPICAL CURRENT VOLTAGE (I-V) CHARACTERISTICS
25°C
(mA) -1.0 -0.8 -0.6 -0.4 -0.2
Output,
(mA) -100 -125 -150
17470D-4
17470D-5
Output, HIGH (mA)
-100
17470D-6
Input
MACH465-12/15/20
TYPICAL CHARACTERISTICS 25°C
(mA)
17470D-7
MACH465
Frequency (MHz)
selected "typical" pattern 16-bit up/down counter. This pattern programmed each block capable being loaded, enabled, reset. Maximum frequency shown uses internal feedback D-type register.
MACH465-12/15/20
TYPICAL THERMAL GUIDELINES
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm PQFP 23.2 20.6 17.7 15.1 13.8 Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations
data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
MACH465-12/15/20
SWITCHINGWAVEFORMS
Input, I/O, Feedback
Combinatorial Output
17470D-8
Combinatorial Output
Input, I/O, Feedback Clock Registered Output
Input, I/O, Feedback Gate tPDL
17470D-9
17470D-10
Latched
Registered Output
Latched Output (MACH
Clock
17470D-11
Gate tGWS
17470D-12
Clock Width
Gate Width (MACH
Registered Input tSIR Input Register Clock Combinatorial Output tICO
tHIR
Registered Input Input Register Clock Output Register Clock
tICS
17470D-14
17470D-13
Registered Input (MACH
Input Register Output Register Setup (MACH
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH465-12/15/20
SWITCHINGWAVEFORMS
Latched tSIL Gate
tHIL tIGO
Combinatorial Output
17470D-15
Latched Input (MACH
tPDLL Latched Latched Input LatchGate tIGOL
tIGS Output Latch Gate
tSLL
17470D-16
Latched Input Output (MACH
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH465-12/15/20
SWITCHINGWAVEFORMS
tWICH Clock tWICL
17470D-17
Input Latch Gate tWIGL
17470D-18
Input Register Clock Width (MACH
Input Latch Gate Width (MACH
tARW Input, I/O, Feedback Registered Output tARR Clock
17470D-19
tAPW Input, I/O, Feedback Registered Output tAPR Clock
17470D-20
Asynchronous Reset
Asynchronous Preset
Input, I/O, Feedback Outputs 0.5V 0.5V
17470D-21
OutputDisable/Enable
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH465-12/15/20
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
17470D-22
Commercial Specification tPD, Closed Open Closed Open Closed
Measured Output Value
*Switching several outputs simultaneously should avoided
accurate measurement.
MACH465-12/15/20
fMAX PARAMETERS
parameter fMAX maximum clock rate which device guaranteed operate. Because flexibility inherent programmable logic devices offers choice clocked flip-flop designs, fMAX specified three types synchronous designs. first type design state machine with feedback signals sent off-chip. This external feedback could back device inputs, second device multi-chip state machine. slowest path defining period clock-to-output time input setup time external signals tCO). reciprocal, fMAX, maximum frequency with external feedback conjunction with equivalent speed device. This fMAX designated "fMAX external." second type design single-chip state machine with internal feedback only. this case, flip-flop inputs defined device inputs flip-flop outputs. Under these conditions, period limited internal delay from flip-flop outputs through internal feedback logic flip-flop inputs. This fMAX designated "fMAX internal". simple internal counter good example this type design; therefore, this parameter sometimes called "fCNT." third type design simple data path application. this case, input data presented flip-flop clocked through; feedback employed. Under these conditions, period limited data setup time data hold time tH). However, lower limit period each fMAX type minimum clock period (tWH tWL). Usually, this minimum clock period determines period third fMAX, designated "fMAX feedback." devices with input registers, additional fMAX parameter specified: fMAXIR. Because this involves feedback, calculated same fMAX feedback. minimum period will limited either setup hold times (tSIR tHIR) clock widths (tWICL tWICH). clock widths normally limiting parameters, that fMAXIR specified 1/(tWICL tWICH). Note that both input output registers same path, overall frequency will limited tICS. frequencies except fMAX internal calculated from other measured parameters. fMAX internal measured directly.
(SECOND CHIP) LOGIC REGISTER LOGIC REGISTER
fMAX External; 1/(tS tCO)
fMAX Internal (fCNT)
LOGIC
REGISTER
REGISTER
LOGIC
tSIR
tHIR fMAXIR 1/(tSIR tHIR) 1/(tWICL tWICH)
17470D-23
fMAX Feedback; 1/(tS 1/(tWH tWL)
MACH465-12/15/20
ENDURANCE CHARACTERISTICS
MACH families manufactured using AMD's advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar parts. result, device erased reprogrammed, feature which allows 100% testing factory.
Endurance Characteristics
Parameter Symbol Parameter Description Pattern Data Retention Time Reprogramming Cycles Units Years Years Cycles Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions
MACH465-12/15/20
INPUT/OUTPUT EQUIVALENT SCHEMATICS
100k
Protection
Input
Preload Circuitry
Feedback Input
17470D-24
MACH465-12/15/20
POWER-UP RESET
MACH devices have been designed with capability reset during system power-up. Following powerup, flip-flops will reset LOW. output state will depend logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset
Parameter Symbol
wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
Parameter Descriptions Power-Up Reset Time Input Feedback Setup Time Clock Width
Switching Characteristics
Unit
Power
Registered Output
Clock
17470D-25
Power-Up Reset Waveform
MACH465-12/15/20
USING PRELOAD OBSERVABILITY
order testable, circuit must both controllable observable. achieve this, MACH devices incorporate register preload observability. preload mode, each flip-flop MACH device loaded from pins, order perform functional testing complex state machines. Register preload makes possible series tests from known starting state, load illegal states test proper recovery. This ability control MACH device's internal state shorten test sequences, since easier reach state interest. observability function makes possible internal state buried registers during test overriding each register's output enable activating output buffer. values stored output buried registers then observed pins. Without this feature, thorough functional test would impossible designs with buried registers. While implementation testability features fairly straightforward, care must taken certain instances insure valid testing. case involves asynchronous reset preset. MACH registers drive asynchronous reset preset lines preloaded such that reset preset asserted, reset preset remove preloaded data. This illustrated Figure Care should taken when planning functional tests, that states that will cause unexpected resets presets preloaded. Another case aware arises testing combinatorial logic. When output configured combinatorial, observability feature forces output into registered mode. When this happens, product terms forced zero, which eliminates combinatorial data. straight combinatorial output, correct value will restored after preload observe function, there will problem. function implements combinatorial latch, however, relies feedback hold correct value, shown Figure this value change during preload observe operation, cannot count data being correct after operation. insure valid testing these cases, outputs that combinatorial latches should tested immediately following preload observe sequence, should first restored known state. MACH devices support both preload observability. Contact individual programming vendors order verify programmer support.
Reset Figure Combinatorial Latch
17470D-27
Preloaded HIGH
Preloaded HIGH
Preload Mode
Figure Preload/Reset Conflict
17470D-26
MACH465-12/15/20
DEVELOPMENT SYSTEMS (subject change)
more information products listed below, please consult FusionPLD Catalog.
MANUFACTURER
Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Cadence Design Systems River Oaks Pkwy Jose, 95134 (408)943-1234 Capilano Computing Quayside Dr., Suite Westminster, B.C. Canada (800) 444-9064 (604) 552-6200 CINA, Inc. P.O. 4872 Mountain View, 94040 (415)940-1723 Data Corporation 10525 Willows Road N.E. P.O. 97046 Redmond, WA98073-9746 (800) 332-8246 (206) 881-6444 GmbH Busenstrasse D-8033 Martinsried, Munich, Germany (89)857-6667 ISDATA GmbH Daimlerstr. D7500 Karlsruhe Germany Germany: 0721/75 U.S.: (510) 531-8553 Logic Modeling 19500 Gibbs P.O. Beaverton, 97075 (503)690-6900 Logical Devices, Inc. Military Trail Deerfield Beach, 33442 (800) 331-7766 (305) 428-6868
SOFTWARE DEVELOPMENT SYSTEMS
MACHXL ®Software Ver.
Design Center/AMD Software
AMD-ABEL Software Data MACH Fitters
PROdeveloper/AMD Software PROsynthesis/AMD Software ComposerPIC Designer (Requires MACH Fitter) Verilog, LeapFrog, RapidSim Simulators (Models also available from Logic Modeling) Ver.
MacABEL Software (Requires SmartPart MACH Fitter)
SmartCAT Circuit Analyzer
ABEL -5Software (Requires MACH Fitter) Synario TMSoftware
PLDSim
LOG/iC Software (Requires MACH Fitter)
SmartModel
Library
CUPL Software
MACH465-12/15/20
DEVELOPMENT SYSTEMS (subject change) (continued)
MANUFACTURER
Mentor Graphics Corp. 8005 S.W. Boeckman Wilsonville, 97070-7777 (800) 547-3000 (503) 685-7000 MicroSim Corp. Fairbanks Irvine, 92718 (714)770-3022 MINCIncorporated 6755 Earl Drive, Suite Colorado Springs, 80918 (800) 755-FPGA (719) 590-1155 OrCAD 3175 N.W. Aloclek Hillsboro, 97124 (503)690-9881 SUSIE-CAD 10000 Nevada Highway, Suite Boulder City, 89005 (702)293-2271 Teradyne Harrison Ave. Boston, 02118 (800) 777-2432 (617) 422-2793 Viewlogic Systems, Inc. Boston Post Road West Marlboro, 01752 (800) 442-4660 (508) 480-0881
SOFTWARE DEVELOPMENT SYSTEMS
PLDSynthesis (Requires MACH Fitter) QuickSim Simulator (Models also available from Logic Modeling)
Design Center Software (Requires MACH Fitter)
PLDesigner Software (Requires MACH Fitter)
Programmable Logic Design Tools 386+ Schematic Design Tool 386+ Digital Simulation Tools
SUSIE TMSimulator
MultiSIM InteractiveSimulator LASAR
ViewPLD PROPLD (Requires PROSim Simulator MACH Fitter) ViewSim Simulator (Models ViewSim also available from Logic Modeling)
MANUFACTURER
Acugen Software, Inc. 427-3 Amherst St., Suite Nashua, 03063 (603)891-1995 GmbH Busenstrasse D-8033 Martinsried, Munich, Germany (87)857-6667
TEST GENERATION SYSTEM
ATGEN Test Generation Software
PLDCheck
Advanced Micro Devices responsible information relating products third parties. inclusion such information representation endorsement these products.
MACH465-12/15/20
APPROVED PROGRAMMERS (subject change)
more information products listed below, please consult FusionPLD Catalog.
MANUFACTURER
Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, 94086 (408)243-7000 Microsystems Post Houston, 77055-7237 (800) 225-2102 (713) 688-4600 Data Corporation 10525 Willows Road N.E. P.O. 97046 Redmond, 98073-9746 (800) 332-8246 (206) 881-6444 Logical Devices Inc./Digelec Military Trail Deerfield Beach, 33442 (800) 331-7766 (305) 428-6868 North America, Inc. 16522 135th Place Redmond, 98052 (800)722-4122 Grund D-7988 Vangen Allgau, Germany 07522-5018 Stag Microsystems Inc. 1600 Wyatt Suite Santa Clara, 95054 (408)988-1118 Stag House Martinfield, Welwyn Garden City Herfordshire 707-332148 System General Park Victoria Milpitas, 95035 (408)263-6667 Alley Lane Shing Rd., Shin Diau Taipei, Taiwan 2-917-3005
PROGRAMMER CONFIGURATION
Pilot
BP1200
UniSite
Model 3900
AutoSite
ALLPRO
Sprint/Expert
Stag Quazar
Turpro-1
APPROVED ON-BOARDPROGRAMMERS
MANUFACTURER
Corelis, Inc. 12607 Hidden Creek Way, Suite Cerritos, California 70703 (310)926-6727 Advanced Micro Devices P.O. 3453, MS-1028 Sunnyvale, CA94088-3453 (800)222-9323
PROGRAMMER CONFIGURATION
JTAG PROG
MACHpro
MACH465-12/15/20
PROGRAMMER SOCKET ADAPTERS (subject change)
MANUFACTURER
Corporation P.O. Patterson, 95363 (209)892-3270 Emulation Technology 2344 Walsh Ave., Bldg. Santa Clara, 95051 (408)982-0660 Logical Systems Corp. P.O. 6184 Syracuse, 13217-6184 (315)478-0722 Procon Technologies, Inc. 1333 Lawrence Expwy, Suite Santa Clara, 95051 (408)246-4456
PART NUMBER
ContactManufacturer
ContactManufacturer
ContactManufacturer
ContactManufacturer
MACH465-12/15/20
PHYSICAL DIMENSIONS* PQR208 208-Pin Plastic Quad Flat Pack; Trimmed Formed (measured millimeters)
27.90 28.10 30.40 30.80
25.50
I.D.
25.50 27.90 28.10 30.40 30.80
3.20 3.60 0.25
0.50 BASIC
3.95
SEATING PLANE
16-038-PQR-2 PQR208 DA92 7-20-94
*For reference only. ANSI standard Basic Space Centering.
Trademarks Copyright 1994 Advanced Micro Devices, Inc. rights reserved. AMD, logo, MACH, registered trademarks Advanced Micro Devices, Inc. MACHXL trademark Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.

MACH465-12/15/20 High-Density CMOS Programmable Logic DISTIN

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