IND: -10/-12/14/18/24 MACH221 Family High-Density CMOS Progr

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IND: -10/-12/14/18/24 MACH221 Family High-Density CMOS Progr

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COM'L: -7/10/12/15/20
IND: -10/-12/14/18/24
MACH221 Family
High-Density CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
Pins Macrocells fCNT Bus-FriendlyInputs I/Os Programmable power-down mode Peripheral Component Interconnect (PCI) compliant Outputs Flip-flops; clock choices "PAL26V12" blocks with buried macrocells Pin-compatible with MACH120 MACH220
GENERAL DESCRIPTION
MACH221 member AMD's CMOS MACH Performance Plus device family. This device approximately nine times logic macrocell capability popular PAL22V10 without loss speed. MACH221 consists eight PAL® blocks interconnected programmable switch matrix. blocks essentially "PAL26V12" structures complete with product-term arrays, programmable macrocells, which programmed high speed power, buried macrocells. switch matrix connects blocks each other input pins, providing high degree connectivity between fullyconnected blocks. This allows designs placed routed efficiently. MACH221 kinds macrocell: output buried. output macrocell provides registered, BLOCK DIAGRAM latched, combinatorial outputs with programmable polarity. registered configuration chosen, register configured D-type T-type help reduce number product terms. register type decision made designer software. output macrocells connected cell. buried macrocell desired, internal feedback path from macrocell used, which frees input. MACH221 dedicated buried macrocells which, addition capabilities output macrocell, also provide input registers synchronizing signals reducing setup time requirements.
BLOCK DIAGRAM
would like view Block Diagram full size, please click box.
Publication# 20157 Rev. Amendment Issue Date: December 1995
I/O0 I/O5 I/O6 I/O11 I/O12 I/O17 I/O18 I/O23
Cells Macrocells Macrocells Cells Macrocells
Macrocells Cells Macrocells
Macrocells Cells Macrocells
Macrocells
Logic Array Logic Allocator
Logic Array Logic Allocator Switch Matrix
Logic Array Logic Allocator
Logic Array Logic Allocator
Logic Array Logic Allocator
Logic Array Logic Allocator
Logic Array Logic Allocator
Logic Array Logic Allocator
Macrocells Cells
Macrocells
Macrocells Cells
Macrocells
Macrocells Cells
Macrocells
Macrocells Cells
Macrocells
I/O42 I/O47
I/O36 I/O41
I/O30 I/O35
I/O24 I/O29
CLK0/I0, CLK1/I1 CLK2/I4, CLK3/I5
CONNECTION DIAGRAMS View PLCC
I/O47 I/O46
I/O5 I/O4 I/O3
I/O7 I/O8 I/O9 I/O10 I/O11 CLK0/I0 CLK1/I1 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17
I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 CLK3/I5 CLK2/I4 I/O35 I/O34 I/O33 I/O32 I/O31
I/O18 I/O26 I/O27 I/O28 I/O29 I/O30 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25
I/O45
I/O2 I/O1
I/O44 I/O43
I/O0
I/O42
14130D-001A 20157B-2
Note: Pin-compatible with MACH120 MACH220.
DESIGNATIONS
CLK/I Clock Input Ground Input Input/Output
Supply Voltage
I/O6
MACH221 Family
ORDERING INFORMATION Commercial Products
programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank Standard Processing OPERATING CONDITIONS Commercial (0°C +70°C)
DEVICE NUMBER Macrocells, Pins SPEED
PACKAGE TYPE 68-Pin Plastic Leaded Chip Carrier 068)
Valid Combinations MACH221-7 MACH221-10 MACH221-12 MACH221-15 MACH221-20
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
MACH221-7/10/12/15/20 (Com'l)
ORDERING INFORMATION Industrial Products
programmable logic products industrial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank Standard Processing OPERATING CONDITIONS Industrial (-40°C +85°C)
DEVICE NUMBER Macrocells, Pins SPEED
PACKAGE TYPE 68-Pin Plastic Leaded Chip Carrier 068)
Valid Combinations MACH221-10 MACH221-12 MACH221-14 MACH221-18 MACH221-24
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
MACH221-10/12/14/18/24 (Ind)
FUNCTIONAL DESCRIPTION
MACH221 consists eight blocks connected switch matrix. There pins dedicated input pins feeding switch matrix. These signals distributed four blocks efficient design implementation. There clock pins that also used dedicated inputs.
Table Logic Allocation Macrocell Output Buried Available Clusters C10, C10, C10,
Blocks
Each block MACH221 (Figure contains 48-product-term logic array, logic allocator, output macrocells, buried macrocells, cells. switch matrix feeds each block with inputs. This makes block look effectively like independent "PAL26V12" with buried macrocells. addition logic product terms, output enable product terms, asynchronous reset product term, asynchronous preset product term provided. output enable product terms chosen within each cell block. flip-flops within block initialized together.
Macrocell
MACH221 types macrocell: output buried. output macrocells configured either registered, latched, combinatorial, with programmable polarity. macrocell provides internal feedback whether configured with without flipflop. registers configured D-type T-type, allowing product-term optimization. flip-flops individually select four clock/gate pins, which also available data inputs. registers clocked LOW-to-HIGH transition clock signal. latch holds data when gate input HIGH, transparent when gate input LOW. flip-flops also asynchronously initialized with common asynchronous reset preset product terms. buried macrocells same output macrocells they used generating logic. that case, only thing that distinguishes them from output macrocells fact that there cell connection, signal only used internally. buried macrocell also configured input register latch.
Switch Matrix
MACH221 switch matrix inputs feedback signals from blocks. Each block provides internal feedback signals feedback signals. switch matrix distributes these signals back blocks efficient manner that also provides high performance. design software automatically configures switch matrix when fitting design into device.
Product-Term Array
MACH221 product-term array consists product terms logic use, special-purpose product terms. special-purpose product terms provide programmable output enable, provides asynchronous reset, provides asynchronous preset.
Logic Allocator
logic allocator MACH221 takes logic product terms allocates them macrocells needed. Each macrocell driven product terms. design software automatically configures logic allocator when fitting design into device. Table illustrates which product term clusters available each macrocell within block. Refer Figure cluster macrocell numbers.
Cell
cell MACH221 consists three-state output buffer. three-state buffer configured three ways: always enabled, always disabled, controlled product term. product term control chosen, product terms used provide control. product terms that available common cells block.
MACH221 Family
These choices make possible macrocell output, input, bidirectional pin, three-state output driving bus.
Power-Down Mode
MACH221 features programmable low-power mode which individual signal paths programmed power. These low-power speed paths will slightly slower than non-low-power paths. This feature allows speed critical paths maximum frequency while rest paths operate low-power mode, resulting power savings 50%.
voltage away from input threshold voltage. Unlike pull-up, this configuration cannot cause contention bus. illustration this configuration, please turn input output equivalent schematics this data book.
Compliance
MACH221-7/10/12 fully compliant with Local Specification published Special Interest Group. MACH221-7/10/12's predictable timing ensures compliance with specifications independent design. other hand, CPLD FPGA architectures without predictable timing, compliance dependent upon routing product term distribution.
Bus-Friendly Inputs I/Os
MACH221 inputs I/Os include inverters series which loop back input. This double inversion reinforces state input pulls
MACH221 Family
Output Enable Output Enable Asynchronous Reset Asynchronous Preset
Output Macro Cell
Cell
Buried Macro Cell
Logic Allocator
Output Macro Cell
Cell
Buried Macro Cell
Output Macro Cell
Cell
Switch Matrix
Buried Macro Cell
Output Macro Cell
Cell
Buried Macro Cell
Output Macro Cell
Cell
Buried Macro Cell
Output Macro Cell
Cell
Buried Macro Cell
20157B-3
Figure MACH221 Block
MACH221 Family
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature With Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 70°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions -3.2 Guaranteed Input Logical HIGH Voltage Inputs (Notes Guaranteed Input Logical Voltage Inputs (Notes 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note 25°C, (Note 25°C, (Note -160 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter measured low-power mode with 12-bit up/down counter pattern. This pattern programmed each block capable being enabled reset. This parameter 100% tested, evaluated initial characterization time design modified where capacitance affected.
MACH221-7/10 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C Unit
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output (Note D-type Setup Time from Input, I/O, Feedback Clock (Note Register Data Hold Time Clock Output (Note Clock Width External Feedback fMAX Maximum Frequency (Note HIGH D-type T-type D-type Internal Feedback (fCNT) Feedback tGWL tPDL tSIR tHIR tICO tICS Setup Time from Input, I/O, Feedback Gate Latch Data Hold Time Gate Output Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output Input Register Clock Output Register Setup D-type T-type tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Latch Gate HIGH 166.7 T-type 166.7 T-type Unit
MACH221-7/10 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol tIGS tWIGL tPDLL tARW tARR tAPW tAPR tLPS tLPCO tLPEA Parameter Description Input Latch Gate Output Latch Setup Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable Input, I/O, Feedback Output Disable Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note 12.5 Unit
Notes: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected. Switching Test Circuit, test conditions. signal powered-down, this parameter must added respective high-speed parameter.
MACH221-7/10 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature With Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 70°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions -3.2 Guaranteed Input Logical HIGH Voltage Inputs (Notes Guaranteed Input Logical Voltage Inputs (Notes 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Notes 25°C, (Note 25°C, (Note -160 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter measured low-power mode with 12-bit up/down counter pattern. This pattern programmed each block capable being enabled reset. This parameter 100% tested, evaluated initial characterization time design modified where capacitance affected.
MACH221-12/15/20 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Clock Register Data Hold Time Clock Output (Note Clock Width External Feedback fMAX Maximum Frequency (Note 1/(tS tCO) HIGH D-type T-type D-type Internal Feedback (fCNT) Feedback tGWL tPDL tSIR tHIR tICO tICS 1/(tWL tWH) T-type 66.7 62.5 83.3 76.9 83.3 D-type T-type tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL tIGS Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Latch Gate Input Latch Gate Output Latch Setup HIGH 1/(tWICL tWICH) 83.3 83.3 62.5 D-type T-type 47.6 66.6 62.5 83.3 38.5 47.6 62.5 Unit
Setup Time from Input, I/O, Feedback Gate Latch Data Hold Time Gate Output (Note Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output Input Register Clock Output Register Setup
MACH221-12/15/20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol Parameter Description tWIGL tPDLL tARW tARR tAPW tAPR tLPS tLPCO tLPEA Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable Input, I/O, Feedback Output Disable Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Unit
Notes: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected. Switching Test Circuit, test conditions. signal powered down, this parameter must added respective high-speed parameter.
MACH221-12/15/20 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature 65°C +150°C Ambient Temperature With Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
INDUSTRIAL OPERATING RANGES
Ambient Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions -3.2 Guaranteed Input Logical HIGH Voltage Inputs (Notes Guaranteed Input Logical Voltage Inputs (Notes 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Notes 25°C, (Note 25°C, (Note -130 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter measured low-power mode with 12-bit up/down counter pattern. This pattern programmed each block capable being enabled reset. This parameter 100% tested, evaluated initial characterization time design modified where capacitance affected.
MACH221-10/12/14/18/24 (Ind)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Clock Register Data Hold Time Clock Output (Note Clock Width HIGH D-type External 1/(tS tCO) Feedback T-type Internal Feedback (fCNT) D-type T-type 83.3 19.5 14.5 66.5 20.5 19.5 66.5 26.5 D-type T-type 83.3 76.9 83.3 25.5 32.5 61.5 66.5 20.5 66.5 13.5 26.5 14.5 13.5 30.5 34.5 14.5 14.5 Unit
fMAX
Maximum Frequency (Note
Feedback 1/(tWL tWH) tGWL tPDL tSIR tHIR tICO tICS Setup Time from Input, I/O, Feedback Gate Latch Data Hold Time Gate Output (Note Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output Input Register Clock Output Register Setup Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Latch Gate Input Latch Gate Output Latch Setup Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches D-type T-type HIGH 1/(tWICL tWICH)
tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL
11.5
10.5 13.5
19.5
14.5 19.5
25.5
tIGS tWIGL tPDLL
MACH221-10/12/14/18/24 (Ind)
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note (continued)
Parameter Symbol Parameter Description tARW tARR tAPW tAPR tLPS tLPCO tLPEA Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note tPDIncrease Powered-Down Macrocell Increase Powered-Down Macrocell (Note tCOIncrease Powered-Down Macrocell (Note tEAIncrease Powered-Down Macrocell (Note 19.5 14.5 19.5 14.5 19.5 19.5 Unit
Notes: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected. Switching Test Circuit, test conditions. signal powered-down, this parameter must added respective high-speed parameter.
MACH221-10/12/14/18/24 (Ind)
TYPICAL CHARACTERISTICS
High Speed
(mA) Power
Frequency (MHz)
20157B-4
selected "typical" pattern 12-bit up/down counter. This pattern programmed each block capable being loaded, enabled, reset. Maximum frequency shown uses internal feedback D-type register.
MACH221 Family
SWITCHING WAVEFORMS
Input, I/O, Feedback
Combinatorial Output
20157B-5
Combinatorial Output
Input, I/O, Feedback Clock Registered Output
Input, I/O, Feedback Gate tPDL
20157B-6
20157B-7
Latched
Registered Output
Latched Output
Clock
20157B-8
Gate tGWS
20157B-9
Clock Width
Gate Width
Registered Input tSIR Input Register Clock Combinatorial Output tICO
tHIR
Registered Input Input Register Clock Output Register Clock
tICS
20157B-11
20157B-10
Registered Input
Input Register Output Register Setup
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH221 Family
SWITCHING WAVEFORMS
Latched tSIL Gate
tHIL tIGO
Combinatorial Output
20157B-12
Latched Input
tPDLL Latched Latched Input Latch Gate tIGOL
tIGS Output Latch Gate
tSLL
20157B-13
Latched Input Output
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH221 Family
SWITCHING WAVEFORMS
tWICH Clock tWICL
20157B-14
Input Latch Gate tWIGL
20157B-15
Input Register Clock Width
Input Latch Gate Width
tARW Input, I/O, Feedback Registered Output tARR Clock
20157B-16
tAPW Input, I/O, Feedback Registered Output tAPR Clock
20157B-17
Asynchronous Reset
Asynchronous Preset
Input, I/O, Feedback Outputs 0.5V 0.5V
20157B-18
Output Disable/Enable
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH221 Family
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
20157B-19
Commercial Specification tPD, Closed Open Closed Open Closed
Measured Output Value
*Switching several outputs simultaneously should avoided accurate measurement.
MACH221 Family
fMAX PARAMETERS
parameter fMAX maximum clock rate which device guaranteed operate. Because flexibility inherent programmable logic devices offers choice clocked flip-flop designs, fMAX specified three types synchronous designs. first type design state machine with feedback signals sent off-chip. This external feedback could back device inputs, second device multi-chip state machine. slowest path defining period clock-to-output time input setup time external signals tCO). reciprocal, fMAX, maximum frequency with external feedback conjunction with equivalent speed device. This fMAX designated "fMAX external." second type design single-chip state machine with internal feedback only. this case, flip-flop inputs defined device inputs flip-flop outputs. Under these conditions, period limited internal delay from flip-flop outputs through internal feedback logic flip-flop inputs. This fMAX designated "fMAX internal". simple internal counter good example this type design; therefore, this parameter sometimes called "fCNT." third type design simple data path application. this case, input data presented flip-flop clocked through; feedback employed. Under these conditions, period limited data setup time data hold time tH). However, lower limit period each fMAX type minimum clock period (tWH tWL). Usually, this minimum clock period determines period third fMAX, designated "fMAX feedback." devices with input registers, additional fMAX parameter specified: fMAXIR. Because this involves feedback, calculated same fMAX feedback. minimum period will limited either setup hold times (tSIR tHIR) clock widths (tWICL tWICH). clock widths normally limiting parameters, that fMAXIR specified 1/(tWICL tWICH). Note that both input output registers same path, overall frequency will limited tICS. frequencies except fMAX internal calculated from other measured parameters. fMAX internal measured directly.
(SECOND CHIP) LOGIC REGISTER LOGIC REGISTER
fMAX External; 1/(tS tCO)
fMAX Internal (fCNT)
LOGIC
REGISTER
REGISTER
LOGIC
tSIR
tHIR fMAXIR 1/(tSIR tHIR) 1/(tWICL tWICH)
20157B-20
fMAX Feedback; 1/(tS 1/(tWH tWL)
MACH221 Family
ENDURANCE CHARACTERISTICS
MACH families manufactured using AMD's advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar parts. result, device erased reprogrammed, feature which allows 100% testing factory.
Endurance Characteristics
Parameter Symbol Parameter Description Pattern Data Retention Time Reprogramming Cycles Units Years Years Cycles Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions
MACH221 Family
INPUT/OUTPUT EQUIVALENT SCHEMATICS (For MACH111, MACH131, MACH211, MACH221, MACH231)
Protection
Input
Preload Circuitry
Feedback Input
20157B-21
MACH221 Family
POWER-UP RESET
MACH devices have been designed with capability reset during system power-up. Following powerup, flip-flops will reset LOW. output state will depend logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset
Parameter Symbol
wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
Parameter Descriptions Power-Up Reset Time Input Feedback Setup Time Clock Width
Switching Characteristics
Unit
Power
Registered Output
Clock
20157B-22
Power-Up Reset Waveform
MACH221 Family
USING PRELOAD OBSERVABILITY
order testable, circuit must both controllable observable. achieve this, MACH devices incorporate register preload observability. preload mode, each flip-flop MACH device loaded from pins, order perform functional testing complex state machines. Register preload makes possible series tests from known starting state, load illegal states test proper recovery. This ability control MACH device's internal state shorten test sequences, since easier reach state interest. observability function makes possible internal state buried registers during test overriding each register's output enable activating output buffer. values stored output buried registers then observed pins. Without this feature, thorough functional test would impossible designs with buried registers. While implementation testability features fairly straightforward, care must taken certain instances insure valid testing. case involves asynchronous reset preset. MACH registers drive asynchronous reset preset lines preloaded such that reset preset asserted, reset preset remove preloaded data. This illustrated Figure Care should taken when planning functional tests, that states that will cause unexpected resets presets preloaded. Another case aware arises testing combinatorial logic. When output configured combinatorial, observability feature forces output into registered mode. When this happens, product terms forced zero, which eliminates combinatorial data. straight combinatorial output, correct value will restored after preload observe function, there will problem. function implements combinatorial latch, however, relies feedback hold correct value, shown Figure this value change during preload observe operation, cannot count data being correct after operation. insure valid testing these cases, outputs that combinatorial latches should tested immediately following preload observe sequence, should first restored known state. MACH devices support preload MACH devices support both preload observability. Contact individual programming vendors order verify programmer support.
Reset Figure Combinatorial Latch
20157B-24
Preloaded HIGH
Preloaded HIGH
Preload Mode
Figure Preload/Reset Conflict
20157B-23
MACH221 Family
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm PLCC Units °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations
data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
MACH221 Family
DEVELOPMENT SYSTEMS (subject change) more information products listed below, please consult FusionPLD Catalog.
MANUFACTURER
Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Cadence Design Systems River Oaks Pkwy Jose, 95134 (408) 943-1234 Data Corporation 10525 Willows Road N.E. P.O. 97046 Redmond, 98073-9746 (800) 332-8246 (206) 881-6444 Mentor Graphics Corp. 8005 S.W. Boeckman Wilsonville, 97070-7777 (800) 547-3000 (503) 685-7000 MicroSim Corp. Fairbanks Irvine, 92718 (714) 770-3022 MINC Incorporated 6755 Earl Drive, Suite Colorado Springs, 80918 (800) 755-FPGA (719) 590-1155 SUSIE-CAD 10000 Nevada Highway, Suite Boulder City, 89005 (702) 293-2271 Synopsys Logic Modeling 19500 Gibbs P.O. Beaverton, 97075 (503) 690-6900 Teradyne Harrison Ave. Boston, 02118 (800) 777-2432 (617) 422-2793
SOFTWARE DEVELOPMENT SYSTEMS
MACHXL® Software Ver.
Design Center/AMD Software
AMD-ABEL Software Data MACH Fitters
PROdeveloper/AMD Software PROsynthesis/AMD Software
PLDDesigner Verilog, LeapFrog, RapidSim Simulators Ver. 9504
ABELSoftware SynarioSoftware
PLDSynthesisII QuickSim Simulator
Design Center Software
PLDesignerTM-XL Software
SUSIESimulator
SmartModel® Library
MultiSIM Interactive Simulator LASAR
MACH221 Family
DEVELOPMENT SYSTEMS (subject change) (continued)
MANUFACTURER
Viewlogic Systems, Inc. Boston Post Road West Marlboro, 01752 (800) 442-4660 (508) 480-0881
SOFTWARE DEVELOPMENT SYSTEMS
ViewPLD PROPLD (Requires PROSim Simulator MACH Fitter) ViewSim Simulator
MANUFACTURER
Acugen Software, Inc. 427-3 Amherst St., Suite Nashua, 03063 (603) 891-1995 GmbH Busenstrasse D-8033 Martinsried, Munich, Germany (87) 857-6667
TEST GENERATION SYSTEM
ATGENTest Generation Software
PLDCheck
Advanced Micro Devices responsible information relating products third parties. inclusion such information representation endorsement these products.
MACH221 Family
APPROVED PROGRAMMERS (subject change)
more information products listed below, please consult FusionPLD Catalog.
MANUFACTURER
Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, 94086 (408) 243-7000 Microsystems Post Houston, 77055-7237 (800) 225-2102 (713) 688-4600 Data Corporation 10525 Willows Road N.E. P.O. 97046 Redmond, 98073-9746 (800) 332-8246 (206) 881-6444 HI-LO/Tribal Sec. Ming Shoh Taipei, Taiwan Logical Devices Inc./Digelec Military Trail Deerfield Beach, 33442 (800) 331-7766 (305) 428-6868 North America, Inc. 16522 135th Place Redmond, 98052 (800) 722-4122 Grund D-7988 Vangen Allgau, Germany 07522-5018 Stag Microsystems Inc. 1600 Wyatt Suite Santa Clara, 95054 (408) 988-1118 Stag House Martinfield, Welwyn Garden City Herfordshire 707-332148 System General Park Victoria Milpitas, 95035 (408) 263-6667 Alley Lane Shing Rd., Shin Diau Taipei, Taiwan 2-917-3005
PROGRAMMER CONFIGURATION
Pilot
BP1148
BP1200
BP2100
UniSite
Model 2900
Model 3900
AutoSite
ALL-07
FLEX-700
ALLPROTM-88
Sprint
Expert
MultiSite
Stag Quazar Stag Eclipse
Turpro-1
APPROVED ON-BOARD PROGRAMMERS
MANUFACTURER
Corelis, Inc. 12607 Hidden Creek Way, Suite Cerritos, California 70703 (310) 926-6727 Advanced Micro Devices P.O. 3453, MS-1028 Sunnyvale, 94088-3453 (800) 222-9323
PROGRAMMER CONFIGURATION
JTAG PROG
MACHpro
MACH221 Family
PROGRAMMER SOCKET ADAPTERS (subject change)
MANUFACTURER
California Integration Coordinators, Inc. Main Street Placerville, 95667 (916) 626-6168 Corporation P.O. Patterson, 95363 (209) 892-3270 Emulation Technology 2344 Walsh Ave., Bldg. Santa Clara, 95051 (408) 982-0660 Logical Systems Corp. P.O. 6184 Syracuse, 13217-6184 (315) 478-0722 Procon Technologies, Inc. 1333 Lawrence Expwy, Suite Santa Clara, 95051 (408) 246-4456
PART NUMBER
Contact Manufacturer
Contact Manufacturer
Contact Manufacturer
Contact Manufacturer
Contact Manufacturer
MACH221 Family
PHYSICAL DIMENSIONS* 68-Pin Plastic Leaded Chip Carrier
.985 .995 .042 .056 .062 .083
.950 .956
I.D. .985 .995 .950 .956 .800 .890 .930
.013 .021
.026 .032
.050
.007 .013
.090 .130 .165 .180
SEATING PLANE
VIEW
SIDE VIEW
16-038-SQ DA78 6-28-94
*For reference only, drawn scale. ANSI standard Basic Space Centering.
Trademarks Copyright 1995 Advanced Micro Devices, Inc. rights reserved. AMD, logo, MACH, registered trademarks Advanced Micro Devices, Inc. Bus-Friendly trademark Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
MACH221 Family

IND: -10/-12/14/18/24 MACH221 Family High-Density CMOS Progr

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