MACH131-7/10/12/15/20 High-Density CMOS Programmable Logic D
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COM'L: -7.5/10/12/15/20
MACH131-7/10/12/15/20
High-Density CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
Pins Macrocells fCNT Bus-friendly inputs Peripheral Component Interconnect (PCI) Compliant
Advanced Micro Devices
Programmable power-down mode Outputs Flip-flops; clock choices "PAL26V16" Blocks Pin-compatible with MACH130, MACH230, MACH231, MACH435 JEDEC compatible with MACH130
GENERAL DESCRIPTION
MACH131 member AMD's CMOS Performance Plus MACH family. This device approximately times logic macrocell capability popular PAL22V10 without loss speed. MACH131 consists four blocks interconnected programmable switch matrix. four blocks essentially "PAL26V12" structures complete with product-term arrays programmable macrocells, including additional buried macrocells. switch matrix connects blocks each other input pins, providing high degree connectivity between fully-connected blocks. This allows designs placed routed efficiently. MACH131 macrocell provides either registered combinatorial outputs with programmable polarity. registered configuration chosen, register configured D-type T-type help reduce number product terms. register type decision made designer software. macrocells connected cell.
Publication# 18889 Rev. Issue Date: April 1995
Amendment
BLOCK DIAGRAM
I/O0 I/OI5 Cells Macrocells
I/O16 I/O31
Cells Macrocells Logic Array Logic Allocator
Logic Array Logic Allocator Logic Array Logic Allocator
Switch Matrix
Logic Array Logic Allocator
Macrocells
Macrocells Cells I/O48 I/O63
Cells I/O32 I/O47 CLK0/I0, CLK1/I1 CLK2/I3, CLK3/I4
18889C-1
MACH131-7/10/12/15/20
CONNECTION DIAGRAM View PLCC
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I4 CLK2/I3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39
I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I0 CLK1/I1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23
I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
18889C-2
Note: Pin-compatible with MACH130, MACH230, MACH231, MACH435.
DESIGNATIONS
CLK/I Clock Input Ground Input Input/Output Supply Voltage
MACH131-7/10/12/15/20
ORDERING INFORMATION Commercial Products
programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed DEVICE NUMBER Macrocells, Pins, Power-Down Option SPEED
OPTIONAL PROCESSING Blank Standard Processing OPERATING CONDITIONS Commercial (0°C +70°C) PACKAGE TYPE 84-Pin Plastic Leaded Chip Carrier 084)
Valid Combinations MACH131-7 MACH131-10 MACH131-12 MACH131-15 MACH131-20
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
MACH131-7/10/12/15/20 (Com'l)
FUNCTIONAL DESCRIPTION
MACH131 consists four blocks connected switch matrix. There pins dedicated input pins feeding switch matrix. These signals distributed four blocks efficient design implementation. There clock pins that also used dedicated inputs.
asynchronous preset. output enable product terms used first eight cells; other control last eight macrocells.
Logic Allocator
logic allocator MACH131 takes logic product terms allocates them macrocells needed. Each macrocell driven product terms. design software automatically configures logic allocator when fitting design into device. Table illustrates which product term clusters available each macrocell within block. Refer Figure cluster macrocell numbers. Table Logic Allocation
Output Macrocell Available Clusters C10, C10, C11, C11, C12, C12, C13, C13, C14, C14,
Blocks
Each block MACH131 (Figure contains 64-product-term logic array, logic allocator, macrocells cells. switch matrix feeds each block with inputs. This makes block look effectively like independent "PAL26V16". There four additional output enable product terms each block. purposes output enable, cells divided into banks macrocells. Each bank allocated output enable product terms. asynchronous reset product term asynchronous preset product term provided flip-flop initialization. flip-flops within block initialized together.
Switch Matrix
MACH131 switch matrix inputs feedback signals from blocks. Each block provides internal feedback signals feedback signals. switch matrix distributes these signals back blocks efficient manner that also provides high performance. design software automatically configures switch matrix when fitting design into device.
Product-Term Array
MACH131 product-term array consists product terms logic use, special-purpose product terms. Four special-purpose product terms provide programmable output enable, provides asynchronous reset, provides
MACH131-7/10/12/15/20
Macrocell
MACH131 macrocells configured either registered combinatorial, with programmable polarity. macrocell provides internal feedback whether configured registered combinatorial. flip-flops configured D-type T-type, allowing product-term optimization. flip-flops individually select four global clock pins, which also available logic inputs. registers clocked LOW-to-HIGH transition clock signal. flip-flops also asynchronously initialized with common asynchronous reset preset product terms.
provide control. product terms that available common eight cells. Within each block, product terms available selection first eight three-state outputs; other product terms available selection last eight three-state outputs. These choices make possible macrocell output, input, bidirectional pin, three-state output driving bus.
Bus-Friendly Inputs I/Os
MACH131 inputs I/Os include inverters series which loop back input. This double inversion reinforces state pulls voltage away from input threshold voltage. Unlike pull-up, this configuration cannot cause contention bus. illustration this configuration, please turn Input Output equivalent schematics this data book.
Power-Down Mode
MACH131 features programmable low-power mode which individual signal paths programmed power. These low-power speed paths will slightly slower than non-low-power paths. This feature allows speed critical paths maximum frequency while rest paths operate low-power mode, resulting power savings 50%.
Compliance
MACH131-7/10 fully compliant with Local Specification published Special Interest Group. MACH231-7/10's predictable timing ensures compliance with specifications independent design. other hand, CPLD FPGA architectures without predictable timing, compliance dependent upon routing product term distribution.
Cell
cell MACH131 consists three-state output buffer. three-state buffer configured three ways: always enabled, always disabled, controlled product term. product term control chosen, product terms used
MACH131-7/10/12/15/20
Output Enable Output Enable Asynchronous Reset Asynchronous Preset
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Logic Allocator
Cell
Output Macro Cell
Output Macro Cell
Cell
Cell
Output Macro Cell
Switch Matrix
Cell
Output Macro Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Cell
Output Macro Cell
Cell Output Macro Cell Cell Output Macro Cell
Output Enable Output Enable
18889C-3
Figure MACH131 Block
MACH131-7/10/12/15/20
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 70°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions -3.2 Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT 25°C, (Note 25°C, (Note -130 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter measured low-power mode with 16-bit up/down counter pattern. This pattern programmed each block capable being enabled reset.
MACH131-7/10 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions -0.5 VOUT 25°C Unit
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Clock Hold Time Clock Output (Note Clock Width HIGH D-type External Feedback 1/(tS tCO) fMAX Maximum Frequency (Note Internal Feedback (fCNT) Feedback tARW tARR tAPW tAPR tLPS tLPCO tLPEA 1/(tWL tWH) T-type D-type T-type 166.7 D-type T-type Unit
Asynchronous Reset Registered Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable Input, I/O, Feedback Output Disable Increase Powered-Down Macrocell (Note Increase Powered-Down Macrocell (Note Increase Powered-Down Macrocell (Note Increase Powered-Down Macrocell (Note
Notes: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected. Switching Test Conditions. signal powered down, this parameter must added respective high-speed parameter.
MACH131-7/10 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 70°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions -3.2 Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note 25°C, (Note 25°C, (Note -130 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter measured low-power mode with 16-bit up/down counter pattern. This pattern programmed each block capable being enabled reset.
MACH131-12/15/20 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions -0.5 VOUT 25°C Unit
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description External Feedback 1/(tS tCO) fMAX Maximum Frequency (Note Internal Feedback (fCNT) Feedback tARW tARR tAPW tAPR tLPS tLPCO tLPEA 1/(tWL tWH) Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Clock Hold Time Clock Output (Note Clock Width HIGH D-type T-type D-type T-type 66.7 62.5 76.8 71.4 83.3 D-type T-type 47.6 66.6 55.5 83.3 38.5 47.6 43.5 62.5 Unit
Asynchronous Reset Registered Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable Input, I/O, Feedback Output Disable Increase Powered-Down Macrocell (Note Increase Powered-Down Macrocell (Note Increase Powered-Down Macrocell (Note Increase Powered-Down Macrocell (Note
Notes: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected. Switching Test Conditions. signal powered down, this parameter must added respective high-speed parameter.
MACH131-12/15/20 (Com'l)
TYPICAL CHARACTERISTICS 25°C
High Speed
Power (mA)
Frequency (MHz)
18889C-4
selected "typical" pattern 16-bit up/down counter. This pattern programmed each block capable being loaded, enabled, reset. Maximum frequency shown uses internal feedback D-type register.
MACH131-7/10/12/15/20
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm PLCC 28.1 Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations
data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
MACH131-7/10/12/15/20
SWITCHING WAVEFORMS
Input, I/O, Feedback
Combinatorial Output
18889C-5
Combinatorial Output
Input, I/O, Feedback Clock Registered Output
Input, I/O, Feedback Gate tPDL
18889C-6
18889C-7
Latched
Registered Output
Latched Output (MACH
Clock
18889C-8
Gate tGWS
18889C-9
Clock Width
Gate Width (MACH
Registered Input tSIR Input Register Clock Combinatorial Output tICO
tHIR
Registered Input Input Register Clock Output Register Clock
tICS
18889C-11
18889C-10
Registered Input (MACH
Input Register Output Register Setup (MACH
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH131-7/10/12/15/20
SWITCHING WAVEFORMS
Latched tSIL Gate
tHIL tIGO
Combinatorial Output
18889C-12
Latched Input (MACH
tPDLL Latched Latched Input Latch Gate tIGOL
tIGS Output Latch Gate
tSLL
18889C-13
Latched Input Output (MACH
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH131-7/10/12/15/20
SWITCHING WAVEFORMS
tWICH Clock tWICL
18889C-14
Input Latch Gate tWIGL
18889C-15
Input Register Clock Width (MACH
Input Latch Gate Width (MACH
tARW Input, I/O, Feedback Registered Output tARR Clock
18889C-16
tAPW Input, I/O, Feedback Registered Output tAPR Clock
18889C-17
Asynchronous Reset
Asynchronous Preset
Input, I/O, Feedback Outputs 0.5V 0.5V
18889C-18
Output Disable/Enable
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH131-7/10/12/15/20
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
18889C-19
Commercial Specification tPD, Closed Open Closed Open Closed
Measured Output Value
*Switching several outputs simultaneously should avoided accurate measurement.
MACH131-7/10/12/15/20
fMAX PARAMETERS
parameter fMAX maximum clock rate which device guaranteed operate. Because flexibility inherent programmable logic devices offers choice clocked flip-flop designs, fMAX specified three types synchronous designs. first type design state machine with feedback signals sent off-chip. This external feedback could back device inputs, second device multi-chip state machine. slowest path defining period clock-to-output time input setup time external signals tCO). reciprocal, fMAX, maximum frequency with external feedback conjunction with equivalent speed device. This fMAX designated "fMAX external." second type design single-chip state machine with internal feedback only. this case, flip-flop inputs defined device inputs flip-flop outputs. Under these conditions, period limited internal delay from flip-flop outputs through internal feedback logic flip-flop inputs. This fMAX designated "fMAX internal". simple internal counter good example this type design; therefore, this parameter sometimes called "fCNT." third type design simple data path application. this case, input data presented flip-flop clocked through; feedback employed. Under these conditions, period limited data setup time data hold time tH). However, lower limit period each fMAX type minimum clock period (tWH tWL). Usually, this minimum clock period determines period third fMAX, designated "fMAX feedback." devices with input registers, additional fMAX parameter specified: fMAXIR. Because this involves feedback, calculated same fMAX feedback. minimum period will limited either setup hold times (tSIR tHIR) clock widths (tWICL tWICH). clock widths normally limiting parameters, that fMAXIR specified 1/(tWICL tWICH). Note that both input output registers same path, overall frequency will limited tICS. frequencies except fMAX internal calculated from other measured parameters. fMAX internal measured directly.
(SECOND CHIP) LOGIC REGISTER LOGIC REGISTER
fMAX External; 1/(tS tCO)
fMAX Internal (fCNT)
LOGIC
REGISTER
REGISTER
LOGIC
tSIR
tHIR fMAXIR 1/(tSIR tHIR) 1/(tWICL tWICH)
18889C-20
fMAX Feedback; 1/(tS 1/(tWH tWL)
MACH131-7/10/12/15/20
ENDURANCE CHARACTERISTICS
MACH families manufactured using AMD's advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar parts. result, device erased reprogrammed, feature which allows 100% testing factory.
Endurance Characteristics
Parameter Symbol Parameter Description Pattern Data Retention Time Reprogramming Cycles Units Years Years Cycles Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions
MACH131-7/10/12/15/20
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Protection
Input
Preload Circuitry
Feedback Input
18889C-21
MACH131-7/10/12/15/20
POWER-UP RESET
MACH devices have been designed with capability reset during system power-up. Following powerup, flip-flops will reset LOW. output state will depend logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset
Parameter Symbol
wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
Parameter Descriptions Power-Up Reset Time Input Feedback Setup Time Clock Width
Switching Characteristics
Unit
Power
Registered Output
Clock
18889C-22
Power-Up Reset Waveform
MACH131-7/10/12/15/20
USING PRELOAD OBSERVABILITY
order testable, circuit must both controllable observable. achieve this, MACH devices incorporate register preload observability. preload mode, each flip-flop MACH device loaded from pins, order perform functional testing complex state machines. Register preload makes possible series tests from known starting state, load illegal states test proper recovery. This ability control MACH device's internal state shorten test sequences, since easier reach state interest. observability function makes possible internal state buried registers during test overriding each register's output enable activating output buffer. values stored output buried registers then observed pins. Without this feature, thorough functional test would impossible designs with buried registers. While implementation testability features fairly straightforward, care must taken certain instances insure valid testing. case involves asynchronous reset preset. MACH registers drive asynchronous reset preset lines preloaded such that reset preset asserted, reset preset remove preloaded data. This illustrated Figure Care should taken when planning functional tests, that states that will cause unexpected resets presets preloaded. Another case aware arises testing combinatorial logic. When output configured combinatorial, observability feature forces output into registered mode. When this happens, product terms forced zero, which eliminates combinatorial data. straight combinatorial output, correct value will restored after preload observe function, there will problem. function implements combinatorial latch, however, relies feedback hold correct value, shown Figure this value change during preload observe operation, cannot count data being correct after operation. insure valid testing these cases, outputs that combinatorial latches should tested immediately following preload observe sequence, should first restored known state. MACH devices support both preload observability. Contact individual programming vendors order verify programmer support.
Reset Figure Combinatorial Latch
18889C-24
Preloaded HIGH
Preloaded HIGH
Preload Mode
Figure Preload/Reset Conflict
18889C-23
MACH131-7/10/12/15/20
DEVELOPMENT SYSTEMS (subject change) more information products listed below, please consult FusionPLD Catalog.
MANUFACTURER
Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Cadence Design Systems River Oaks Pkwy Jose, 95134 (408) 943-1234 Capilano Computing Quayside Dr., Suite Westminster, B.C. Canada (800) 444-9064 (604) 552-6200 CINA, Inc. P.O. 4872 Mountain View, 94040 (415) 940-1723 Data Corporation 10525 Willows Road N.E. P.O. 97046 Redmond, 98073-9746 (800) 332-8246 (206) 881-6444 GmbH Busenstrasse D-8033 Martinsried, Munich, Germany (89) 857-6667 ISDATA GmbH Daimlerstr. D7500 Karlsruhe Germany Germany: 0721/75 U.S.: (510) 531-8553 Logic Modeling 19500 Gibbs P.O. Beaverton, 97075 (503) 690-6900 Logical Devices, Inc. Military Trail Deerfield Beach, 33442 (800) 331-7766 (305) 428-6868
SOFTWARE DEVELOPMENT SYSTEMS
MACHXL® Software Ver.
Design Center/AMD Software
AMD-ABEL Software Data MACH Fitters
PROdeveloper/AMD Software PROsynthesis/AMD Software ComposerPICDesigner (Requires MACH Fitter) Verilog, LeapFrog, RapidSim Simulators (Models also available from Logic Modeling) Ver.
MacABELSoftware (Requires SmartPart MACH Fitter)
SmartCAT Circuit Analyzer
ABELTM-5 Software (Requires MACH Fitter) SynarioSoftware
PLDSim
LOG/iCSoftware (Requires MACH Fitter)
SmartModel® Library
CUPLSoftware
MACH131-7/10/12/15/20
DEVELOPMENT SYSTEMS (subject change) (continued)
MANUFACTURER
Mentor Graphics Corp. 8005 S.W. Boeckman Wilsonville, 97070-7777 (800) 547-3000 (503) 685-7000 MicroSim Corp. Fairbanks Irvine, 92718 (714) 770-3022 MINC Incorporated 6755 Earl Drive, Suite Colorado Springs, 80918 (800) 755-FPGA (719) 590-1155 OrCAD 3175 N.W. Aloclek Hillsboro, 97124 (503) 690-9881 SUSIE-CAD 10000 Nevada Highway, Suite Boulder City, 89005 (702) 293-2271 Teradyne Harrison Ave. Boston, 02118 (800) 777-2432 (617) 422-2793 Viewlogic Systems, Inc. Boston Post Road West Marlboro, 01752 (800) 442-4660 (508) 480-0881
SOFTWARE DEVELOPMENT SYSTEMS
PLDSynthesis(Requires MACH Fitter) QuickSim Simulator (Models also available from Logic Modeling)
Design Center Software (Requires MACH Fitter)
PLDesignerTM-XL Software (Requires MACH Fitter)
Programmable Logic Design Tools 386+ Schematic Design Tool 386+ Digital Simulation Tools
SUSIESimulator
MultiSIM Interactive Simulator LASAR
ViewPLD PROPLD (Requires PROSim Simulator MACH Fitter) ViewSim Simulator (Models ViewSim also available from Logic Modeling)
MANUFACTURER
Acugen Software, Inc. 427-3 Amherst St., Suite Nashua, 03063 (603) 891-1995 GmbH Busenstrasse D-8033 Martinsried, Munich, Germany (87) 857-6667
TEST GENERATION SYSTEM
ATGENTest Generation Software
PLDCheck
Advanced Micro Devices responsible information relating products third parties. inclusion such information representation endorsement these products.
MACH131-7/10/12/15/20
APPROVED PROGRAMMERS (subject change)
more information products listed below, please consult FusionPLD Catalog.
MANUFACTURER
Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, 94086 (408) 243-7000 Microsystems Post Houston, 77055-7237 (800) 225-2102 (713) 688-4600 Data Corporation 10525 Willows Road N.E. P.O. 97046 Redmond, 98073-9746 (800) 332-8246 (206) 881-6444 Logical Devices Inc./Digelec Military Trail Deerfield Beach, 33442 (800) 331-7766 (305) 428-6868 North America, Inc. 16522 135th Place Redmond, 98052 (800) 722-4122 Grund D-7988 Vangen Allgau, Germany 07522-5018 Stag Microsystems Inc. 1600 Wyatt Suite Santa Clara, 95054 (408) 988-1118 Stag House Martinfield, Welwyn Garden City Herfordshire 707-332148 System General Park Victoria Milpitas, 95035 (408) 263-6667 Alley Lane Shing Rd., Shin Diau Taipei, Taiwan 2-917-3005
PROGRAMMER CONFIGURATION
Pilot
BP1200
UniSite
Model 3900
AutoSite
ALLPROTM-88
Sprint/Expert
Stag Quazar
Turpro-1
APPROVED ON-BOARD PROGRAMMERS
MANUFACTURER
Corelis, Inc. 12607 Hidden Creek Way, Suite Cerritos, California 70703 (310) 926-6727 Advanced Micro Devices P.O. 3453, MS-1028 Sunnyvale, 94088-3453 (800) 222-9323
PROGRAMMER CONFIGURATION
JTAG PROG
MACHpro
MACH131-7/10/12/15/20
PROGRAMMER SOCKET ADAPTERS (subject change)
MANUFACTURER
Corporation P.O. Patterson, 95363 (209) 892-3270 Emulation Technology 2344 Walsh Ave., Bldg. Santa Clara, 95051 (408) 982-0660 Logical Systems Corp. P.O. 6184 Syracuse, 13217-6184 (315) 478-0722 Procon Technologies, Inc. 1333 Lawrence Expwy, Suite Santa Clara, 95051 (408) 246-4456
PART NUMBER
Contact Manufacturer
Contact Manufacturer
Contact Manufacturer
Contact Manufacturer
MACH131-7/10/12/15/20
PHYSICAL DIMENSIONS* 84-Pin Plastic Leaded Chip Carrier (measured inches)
1.185 1.195
1.150 1.156
.042 .056
.062 .083
1.185 1.195 1.150 1.156
I.D.
1.090 1.130 1.000
.013 .021
.026 .032
.050
.007 .013
.090 .130 .165 .180
SEATING PLANE
VIEW
SIDE VIEW
16-038-SQ DF79 8-1-95
*For reference only. ANSI standard Basic Space Centering.
Trademarks Copyright 1995 Advanced Micro Devices, Inc. rights reserved. AMD, logo, MACH, registered trademarks Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
MACH131-7/10/12/15/20
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