HM5117805B Series 2,097,152-word 8-bit Dynamic Random Access Memo
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ADE-203-457A
HM5117805B Series
2,097,152-word 8-bit Dynamic Random Access Memory
Rev. Dec. 1995
Hitachi HM5117805B CMOS dynamic organized 2,097,152-word 8-bit. employs most advanced CMOS technology high performance power. HM5117805B offers Extended Data (EDO) Page Mode high speed access mode.
Ordering Information
Type HM5117805BJ-6 HM5117805BJ-7 HM5117805BJ-8 HM5117805BLJ-6 HM5117805BLJ-7 HM5117805BLJ-8 HM5117805BTT-6 HM5117805BTT-7 HM5117805BTT-8 HM5117805BLTT-6 HM5117805BLTT-7 HM5117805BLTT-8 Access time 28-pin plastic TSOP (TTP-28DA) Package 400-mil 28-pin plastic (CP-28DA)
Feature
Single (±10%) High speed Access time: ns/70 ns/80 (max) power dissipation Active mode: mW/605 mW/550 mW(max) Standby mode: (max) 0.83 (max) (L-version) page mode capability Long refresh period 2048 refresh cycles: (L-version) variations refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) Battery backup operation (L-version)
This specification fully compatible with 16-Mbit DRAM specifications from TEXAS INSTRUMENTS.
HM5117805B Series
Arrangement
HM5117805BJ/BLJ Series
I/O0 I/O1 I/O2 I/O3 I/O7 I/O6 I/O5 I/O4
HM5117805BTT/BLTT Series I/O0 I/O1 I/O2 I/O3 (Top view) I/O7 I/O6 I/O5 I/O4
(Top view)
Description
name I/O0 I/O7 Function Address input Refresh address input Data input/data output address strobe Column address strobe Write enable Output enable Power supply Ground connection
HM5117805B Series
Block Diagram
control circuit
control circuit
control circuit
control circuit
I/O7
I/O7 buffer
I/O6
I/O6 buffer
Sense amp.
circuit
Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array
Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp.
I/O5 buffer
I/O5
decoder driver
decoder driver
I/O4 buffer
I/O4
Column decoder driver
Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp.
Peripheral
Column decoder driver
Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp. 256k memory cell array Sense amp.
decoder driver
I/O3
I/O3 buffer
decoder driver
I/O1 buffer
I/O1
I/O2
I/O2 buffer
I/O0 buffer
I/O0
Column address buffer
address buffer
Address
HM5117805B Series
Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature Symbol Iout Topr Tstg Value -1.0 +7.0 -1.0 +7.0 +125 Unit
Recommended Operating Conditions +70°C)
Parameter Supply voltage Input high voltage Input voltage Note: Symbol -1.0 Unit Note
voltage referred VSS.
HM5117805B Series
Characteristics +70°C, 10%,
HM5117805B Parameter Operating current*1, Symbol ICC1 ICC2
Unit Test conditions interface RAS, Dout High-Z CMOS interface RAS, 0.2V Dout High-Z CMOS interface RAS, 0.2V Dout High-Z Dout enable tHPC CMOS interface Dout High-Z refresh: 62.5 tRAS CMOS interface RAS, 0.2V Dout High-Z Vout Dout disable High Iout Iout
Standby current
Standby current (L-version)
ICC2
RAS-only refresh current*2 ICC3 Standby current*1 ICC5
CAS-before-RAS refresh current page mode current*1, Battery back current*4 (Standby with refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output voltage
ICC6 ICC7 ICC10
ICC11
Notes: depends output load condition when device selected. specified output open condition. Address changed once less while VIL. Address changed once less while VIH. (0.2 while (0.2
HM5117805B Series
Capacitance 25°C, 10%)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI/O Unit Notes
Notes: Capacitance measured with Boonton Meter effective capacitance measuring method. disable Dout.
Characteristics +70°C, ±10%,
Test Conditions Input rise fall time: Input levels: Input timing reference levels: Output timing reference levels: Output load: gate (100 (Including scope jig)
HM5117805B Series
Read, Write, Read-Modify-Write Refresh Cycles (Common parameters)
HM5117805B Parameter Random read write cycle time precharge time precharge time pulse width pulse width Symbol tRAS tCAS 10000 10000 10000 10000 10000 10000 Unit Notes
address setup time tASR address hold time tRAH Column address setup time Column address hold time tASC tCAH
delay time tRCD column address tRAD delay time hold time hold time tRSH tCSH
precharge tCRP time delay time delay time from Transition time (rise fall) tOED tDZC delay time from tDZO
HM5117805B Series
Read Cycle
HM5117805B Parameter Access time from Access time from Access time from address Access time from Read command setup time Read command hold time Read command hold time from Read command hold time Column address lead time Column address lead time output low-Z Output data hold time Output data hold time from Output buffer turn-off time Output buffer turn-off delay time Output data hold time from Output buffer turn-off Output buffer turn-off delay time delay time Symbol tRAC tCAC tOEA tRCS tRCH tRCHR tRRH tRAL tCAL tCLZ tOHO tOFF tOEZ tCDD tOHR tOFR tWEZ tWED tRDD Unit Notes
HM5117805B Series
Write Cycle
HM5117805B Parameter Write command setup time Write command hold time Write command pulse width Write command lead time Write command lead time Data-in setup time Data-in hold time Symbol tWCS tWCH tRWL tCWL Unit Notes
Read-Modify-Write Cycle
HM5117805B Parameter Read-modify-write cycle time delay time delay time Column address delay time hold time from Symbol tRWC tRWD tCWD tAWD tOEH Unit Notes
HM5117805B Series
Refresh Cycle
HM5117805B Parameter setup time (CBR refresh cycle) hold time (CBR refresh cycle) setup time (CBR refresh cycle) hold time (CBR refresh cycle) precharge hold time Symbol tCSR tCHR tWRP tWRH tRPC Unit Notes
Page Mode Cycle
HM5117805B Parameter page mode cycle time page mode pulse width Access time from precharge hold time from precharge Output data hold time from Symbol tHPC tRASP tCPA tCPRH tDOH Unit Notes
100000
100000
100000
hold time referred tCOL setup time tCOP
Read command hold tRCHC time from precharge
HM5117805B Series
Page Mode Read-Modify-Write Cycle
HM5117805B Parameter Symbol Unit Notes
page mode read- tHPRWC modify-write cycle time delay time from precharge tCPW
Refresh
Parameter Refresh period Refresh period (L-version) Symbol tREF tREF Unit Note 2048 cycles 2048 cycles
Self-Refresh Mode (L-version)
HM5117805BL Parameter pulse width (self-refresh) precharge time (self-refresh) hold time (self-refresh) Symbol tRASS tRPS tCHS Unit Notes
HM5117805B Series
Notes: measurements assume initial pause required after power followed minimum eight initialization cycles (any combination cycles containing RAS-only refresh CAS-before-RAS refresh). internal refresh counter used, minimum eight CAS-before-RAS refresh cycles required. Operation with tRCD (max) limit insures that tRAC (max) met, tRCD (max) specified reference point only; tRCD greater than specified tRCD (max) limit, then access time controlled exclusively tCAC. Operation with tRAD (max) limit insures that tRAC (max) met, tRAD (max) specified reference point only; tRAD greater than specified tRAD (max) limit, then access time controlled exclusively tAA. Either tOED tCDD must satisfied. Either tDZO tDZC must satisfied. (min) (max) reference levels measuring timing input signals. Also, transition times measured between (min) (max). Assumes that tRCD tRCD (max) tRAD tRAD (max). tRCD tRAD greater than maximum recommended value shown this table, tRAC exceeds value shown. Measured with load circuit equivalent loads Assumes that tRCD tRCD (max) tRAD tRAD (max). Assumes that tRCD tRCD (max) tRAD tRAD (max). Either tRCH tRRH must satisfied read cycles. tOFF (max) tOEZ (max) define time which outputs achieve open circuit condition referred output voltage levels. tWCS, tRWD, tCWD, tAWD tCPW restrictive operating parameters. They included data sheet electrical characteristics only; tWCS tWCS (min), cycle early write cycle data will remain open circuit (high impedance) throughout entire cycle; tRWD tRWD (min), tCWD tCWD (min), tAWD tAWD (min), tCWD tCWD (min), tAWD tAWD (min) tCPW tCPW (min), cycle read-modify-write data output will contain data read from selected cell; neither above sets conditions satisfied, condition data access time) indeterminate. These parameters referred leading edge early write cycles leading edge delayed write read-modify-write cycles. tRASP defines pulse width page mode cycles. Access time determined longest among tAA, tCAC tCPA. delayed write read-modify-write cycles, must disable output buffer prior applying data device. After reset, tOEH tCWL, will remain open circuit (high impedance); tOEH tCWL, invalid data will each I/O. tHPC (min) achieved during series page mode write cycles page mode read cycles. both write read operation mixed page mode cycle (EDO page mode cycle (1), (2)), minimum value cycle (tCAS becomes greater than specified tHPC (min) value.The value cycle time mixed page mode shown page mode cycle (2).
HM5117805B Series
Timing Waveforms*20
Read Cycle
Address
Column RCHR
High-Z
Dout Dout
Notes:
(min) (max), (min) (max))
Invalid Dout
HM5117805B Series
Early Write Cycle
Address
Column
Dout
High-Z** (min)
HM5117805B Series
Delayed Write Cycle
Address
Column
High-Z
Dout High-Z* Invalid Dout
HM5117805B Series
Read-Modify-Write Cycle
Address
Column tCWL
High-Z
High-Z*
Dout
Dout
HM5117805B Series
RAS-Only Refresh Cycle
Address Dout
High-Z
Refresh Address (RA0 RA10)
HM5117805B Series
CAS-Before-RAS Refresh Cycle
Address Dout High-Z
HM5117805B Series
Hidden Refresh Cycle
Address
Column
High-Z Dout Dout
tWRH
HM5117805B Series
Page Mode Read Cycle
RASP RCHR tCAS RCHC
CPRH
tCAS
tASR
Address
tRAH tASC tCAH Column tDZC
Column
Column
tASC
Column
tRDD tCDD
High-Z tDZO tCOL tCOP tOED
tOEA tCAC tRAC
tCPA tCAC tWEZ tOEZ tOHO tOEA
tCPA tCPA tCAC tDOH tOEZ tCAC tOEA
tOFR tOHR tOEZ tOHO tOFF Dout
tOHO Dout
Dout
Dout
Dout
Dout
HM5117805B Series
Page Mode Early Write Cycle
RASP
tCAH
Address
Column
Column
Column
Dout
High-Z** (min)
HM5117805B Series
Page Mode Delayed Write Cycle
RASP
Address Column Column Column
Dout
High-Z*
Invalid Dout Invalid Dout Invalid Dout
HM5117805B Series
Page Mode Read-Modify-Write Cycle
RASP
HPRWC
Column Column Column
Address
High-Z*
Dout
Dout
Dout
Dout
HM5117805B Series
Page Mode Cycle
RASP tCAS tRSH tCPW tAWD tRAH tCAH Column tASC Column High-Z tOED tWED Column tRDD tCDD
tCAS
tASR
Address
tASC
Column
tCPA tOEA
tCPA
tCPA
tOFR tWEZ tOEZ
tCAC
tOHO tOFF
tCAC
tCAC
tOEA
Dout
Dout
Dout
Dout
HM5117805B Series
Page Mode Cycle
RASP
RCHR
tCAS
tCAS tCPW tASC Column tOED tCOP tRSH
tWCS
tASR
Address
tRAH
tCAH
Column tOED tCOL
Column
Column
tRDD tCDD
High-Z
tWED
tOEA tCAC tRAC
Dout
tOEZ tCPA tCAC tOEZ
Dout
tCPA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF Dout
Dout
HM5117805B Series
Self Refresh Cycle (L-version)
RASS
Dout High-Z
Address,
self refresh current achieved introducing extremely long internal refresh cycle. Therefore some care needs taken refresh. Please tRASS timing, tRASS During this period, device transition state from normal operation mode self refresh mode. tRASS then precharge time should tRPS instead tRP. only refresh burst refresh mode normal read/write cycle, 2048 cycles distributed refresh with 15.6 interval should executed within immediately after exitng from before entering into self refresh mode. distributed refresh mode with 15.6 interval normal read/write cycle, refresh should executed within 15.6 immediately after exiting from before entering into self refresh mode. Repetitive self refresh mode without refreshing memory allowed. Once exit from self refresh mode, memory cells need refreshed before re-entering self refresh mode again.
HM5117805B Series
Package Dimensions
HM5117805BJ/BLJ Series (CP-28DA)
18.17 18.54
Unit:
10.16 0.13 11.18 0.13
0.74
3.50 0.26 2.85 0.12
0.63
0.43 0.10
1.27 0.10
9.40 0.25
HM5117805BTT/BLTT Series (TTP-28DA)
Unit:
18.41 18.81
0.40 0.10
1.27 0.21
10.16
11.76 1.20 0.10 1.15 0.08 0.18
+0.075 -0.025
0.145
0.68 0.50 0.10
HM5117805B Series
When using this document, keep following mind: This document may, wholly partially, subject change without notice. rights reserved: permitted reproduce duplicate, form, whole part this document without Hitachi's permission.
Hitachi will held responsible damage user that result from accidents other reasons during operation user's unit according this document. Circuitry other examples described herein meant merely indicate characteristics performance Hitachi's semiconductor product. Hitachi assumes responsibility intellectual property claims other problems that result from applications based examples described herein. license granted implication otherwise under patents other rights third party Hitachi, Ltd. MEDICAL APPLICATIONS: Hitachi's products authorized MEDICAL APPLICATIONS without written consent appropriate officer Hitachi's sales company. Such includes, limited life support systems. Buyers Hitachi's products requested notify relevant Hitachi sales office when planning products MEDICAL APPLICATIONS.
Semiconductor Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tokyo (03) 3270-2111 (03) 3270-5109
further information write Hitachi America, Ltd. Semiconductor Div. 2000 Sierra Point Parkway Brisbane, 94005-1835 415-589-8300 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher StraBe D-85622 Feldkirchen Munchen 089-9 80-0 089-9 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Wihtebrook Park Lower Cookham Road Maidenhead Berkshire United Kingdom 0628-585000 0628-778322 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Habour City, Canton Road, Tsim Tsui, Kowloon, Hong Kong 27359218 27306071 Hitachi Asia Pte. Ltd. Collyer Quay #20-00 Hitachi Tower Singapore 0104 535-2100 535-1533
HM5117805B Series
Revision Record
Rev. Date Sep. 1995 Dec. 1995 Contents Modification Initial issue Deletion preliminary Timing waveforms Deletion note: tOEH tCWE Drawn Approved Takahashi Hayakawa
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