HM5117400B Series 4,194,304-word 4-bit Dynamic Random Access Memo
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ADE-203-369A
HM5117400B Series
4,194,304-word 4-bit Dynamic Random Access Memory
Rev. Mar. 1996
Hitachi HM5117400B CMOS dynamic organized 4,194,304-word 4-bit. employs most advanced CMOS technology high performance power. HM5117400B offers Fast Page Mode high speed access mode.
Ordering Information
Type HM5117400BS-6 HM5117400BS-7 HM5117400BS-8 HM5117400BLS-6 HM5117400BLS-7 HM5117400BLS-8 HM5117400BTS-6 HM5117400BTS-7 HM5117400BTS-8 HM5117400BLTS-6 HM5117400BLTS-7 HM5117400BLTS-8 Access time Package 300-mil 26-pin plastic TSOP (TTP-26/24DA) 300-mil 26-pin plastic (CP-26/24DB)
Feature
Single (±10%) High speed Access time: ns/70 ns/80 (max) power dissipation Active mode: mW/550 mW/495 (max) Standby mode: (max) 0.83 (max) (L-version) Fast page mode capability Long refresh period 2048 refresh cycles: (L-version) variations refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Battery backup operation (L-version) Test function 16-bit parallel test mode
This specification fully compatible with 16-Mbit DRAM specifications from TEXAS INSTRUMENTS.
HM5117400B Series
Arrangement
HM5117400BS/BLS Series HM5117400BTS/BLTS Series
I/O1 I/O2
I/O4 I/O3
I/O1 I/O2
I/O4 I/O3
(Top view)
(Top view)
Description
name I/O1 I/O4 Function Address input Refresh address input Data input/data output address strobe Column address strobe Write enable Output enable Power supply Ground connection
HM5117400B Series
Block Diagram
Buffer Buffer
Column decoder driver
Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. cell cell cell cell cell cell cell cell cell cell cell cell cell cell cell cell array array array array array array array array array array array array array array array array
Peripheral Circuit
Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp.
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array array array array array array array array array array array array array array array array
Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp.
cell cell cell cell cell cell cell cell cell cell cell cell cell cell cell cell
array array array array array array array array array array array array array array array array
Selector
Selector Selector decoder driver
decoder driver
Selector
Column decoder driver
Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. 256k memory Sense amp. cell cell cell cell cell cell cell cell cell cell cell cell cell cell cell cell array array array array array array array array array array array array array array array array
Selector
Selector Buffer Selector decoder driver
decoder driver
Buffer
Selector Address
HM5117400B Series
Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature Symbol Iout Topr Tstg Value -1.0 +7.0 -1.0 +7.0 +125 Unit
Recommended Operating Conditions +70°C)
Parameter Supply voltage Input high voltage Input voltage Note: Symbol -1.0 Unit Note
voltage referred VSS.
HM5117400B Series
Characteristics +70°C, 10%,
HM5117400B Parameter Operating current*1, Symbol ICC1 ICC2
Unit Test conditions interface RAS, Dout High-Z CMOS interface RAS, -0.2V Dout High-Z CMOS interface RAS, -0.2V Dout High-Z Dout enable CMOS interface Dout High-Z refresh: 62.5 tRAS Vout Dout disable High Iout Iout
Standby current
Standby current (L-version)
ICC2
RAS-only refresh current*2 ICC3 Standby current*1 ICC5
CAS-before-RAS refresh current Fast page mode current*1, Battery back current
ICC6 ICC7 ICC10
Input leakage current Output leakage current Output high voltage Output voltage
Notes: depends output load condition when device selected. specified output open condition. Address changed once less while VIL. Address changed once less while VIH.
HM5117400B Series
Capacitance 25°C, 10%)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI/O Unit Notes
Notes: Capacitance measured with Boonton Meter effective capacitance measuring method. disable Dout.
Characteristics +70°C, ±10%, *18,
Test Conditions Input rise fall time: Input timing reference levels: Output load: gate (100 (Including scope jig)
HM5117400B Series
Read, Write, Read-Modify-Write Refresh Cycles (Common parameters)
HM5117400B Parameter Random read write cycle time precharge time precharge time pulse width pulse width address setup time Symbol tRAS tCAS tASR 10000 10000 10000 10000 10000 10000 Unit Notes
address hold time tRAH Column address setup time Column address hold time tASC tCAH
delay time tRCD column address tRAD delay time hold time hold time tRSH tCSH
precharge tCRP time delay time delay time from Transition time (rise fall) tOED tDZC delay time from tDZO
HM5117400B Series
Read Cycle
HM5117400B Parameter Access time from Access time from Access time from address Access time from Read command setup time Read command hold time Read command hold time Column address lead time Column address lead time output low-Z Output data hold time Output data hold time from Output buffer turn-off time Output buffer turn-off delay time Symbol tRAC tCAC tOEA tRCS tRCH tRRH tRAL tCAL tCLZ tOHO tOFF tOEZ tCDD Unit Notes
HM5117400B Series
Write Cycle
HM5117400B Parameter Write command setup time Write command hold time Write command pulse width Write command lead time Write command lead time Data-in setup time Data-in hold time Symbol tWCS tWCH tRWL tCWL Unit Notes
Read-Modify-Write Cycle
HM5117400B Parameter Read-modify-write cycle time delay time delay time Column address delay time hold time from Symbol tRWC tRWD tCWD tAWD tOEH Unit Notes
HM5117400B Series
Refresh Cycle
HM5117400B Parameter setup time (CBR refresh cycle) hold time (CBR refresh cycle) setup time (CBR refresh cycle) hold time (CBR refresh cycle) precharge hold time Symbol tCSR tCHR tWRP tWRH tRPC Unit Notes
Fast Page Mode Cycle
HM5117400B Parameter Fast page mode cycle time Fast page mode pulse width Access time from precharge hold time from precharge Symbol tRASP tCPA tCPRH Unit Notes
100000
100000
100000
Fast Page Mode Read-Modify-Write Cycle
HM5117400B Parameter Symbol Unit Notes
Fast page mode read- tPRWC modify-write cycle time delay time from precharge tCPW
HM5117400B Series
Test Mode Cycle
HM5117400B Parameter Test mode setup time Test mode hold time Symbol tWTS tWTH Unit Notes
Refresh
Parameter Refresh period Refresh period (L-version) Symbol tREF tREF Unit Notes 2048 cycles 2048 cycles
HM5117400B Series
Notes: measurements assume initial pause required after power followed minimum eight initialization cycles (any combination cycles containing RAS-only refresh CAS-before-RAS refresh). internal refresh counter used, minimum eight CAS-before-RAS refresh cycles required. Operation with tRCD (max) limit insures that tRAC (max) met, tRCD (max) specified reference point only; tRCD greater than specified tRCD (max) limit, then access time controlled exclusively tCAC. Operation with tRAD (max) limit insures that tRAC (max) met, tRAD (max) specified reference point only; tRAD greater than specified tRAD (max) limit, then access time controlled exclusively tAA. Either tOED tCDD must satisfied. Either tDZO tDZC must satisfied. (min) (max) reference levels measuring timing input signals. Also, transition times measured between (min) (max). Assumes that tRCD tRCD (max) tRAD tRAD (max). tRCD tRAD greater than maximum recommended value shown this table, tRAC exceeds value shown. Measured with load circuit equivalent loads Assumes that tRCD tRCD (max) tRCD tCAC (max) tRAD (max). Assumes that tRAD tRAD (max) tRCD tCAC (max) tRAD (max). Either tRCH tRRH must satisfied read cycles. tOFF (max) tOEZ (max) define time which outputs achieve open circuit condition referred output voltage levels. tWCS, tRWD, tCWD, tAWD tCPW restrictive operating parameters. They included data sheet electrical characteristics only; tWCS tWCS (min), cycle early write cycle data will remain open circuit (high impedance) throughout entire cycle; tRWD tRWD (min), tCWD tCWD (min), tAWD tAWD (min), tCWD tCWD (min), tAWD tAWD (min) tCPW tCPW (min), cycle read-modify-write data output will contain data read from selected cell; neither above sets conditions satisfied, condition data access time) indeterminate. These parameters referred leading edge early write cycles leading edge delayed write read-modify-write cycles. tRASP defines pulse width fast page mode cycles. Access time determined longest among tAA, tCAC tCPA. delayed write read-modify-write cycles, must disable output buffer prior applying data device. After reset, tOEH tCWL, will remain open circuit (high impedance); tOEH tCWL, invalid data will each I/O. DRAM offers 16-bit time saving parallel test mode. Address don't care during test mode. Test mode performing WE-and-CAS-before-RAS (WCBR) cycle. 16-bit parallel test mode, data written into bits parallel each (I/O1 I/O4) read from each I/O. bits each equal (all 0s), data output high state during test mode read cycle, then device passed. they equal, data output state, then device failed. Refresh during test mode operation performed normal read cycles WCBR refresh cycles. test mode enter normal operation mode, perform either regular CASbefore-RAS refresh cycle RAS-only refresh cycle. test mode read cycle, value tRAC, tAA, tCAC tCPA delayed specified value. These parameters should specified test mode cycles adding above value specified value this data sheet.
HM5117400B Series
Timing Waveforms*21
Read Cycle
Address
Column
High-Z
Dout Dout
Notes:
(min) (max), (min) (max))
Invalid Dout
HM5117400B Series
Early Write Cycle
Address
Column
Dout
High-Z** (min)
HM5117400B Series
Delayed Write Cycle
Address
Column
High-Z
Dout High-Z* Invalid Dout
HM5117400B Series
Read-Modify-Write Cycle
tRAH
Address
Column tCWL
High-Z
High-Z*
Dout
Dout
HM5117400B Series
RAS-Only Refresh Cycle
Address Dout High-Z
Refresh Address (RA0 RA10)
CAS-Before-RAS Refresh Cycle
Address
Dout
High-Z
HM5117400B Series
Hidden Refresh Cycle
Address
Column
High-Z Dout Dout
HM5117400B Series
Fast Page Mode Read Cycle
RASP CPRH
Address Column Column Column
tRCS High-Z High-Z tRCH tRCH
High-Z
Dout Dout Dout Dout
HM5117400B Series
Fast Page Mode Early Write Cycle
RASP
Address
Column
Column
Column
Dout
High-Z** (min)
HM5117400B Series
Fast Page Mode Delayed Write Cycle
RASP
Address Column Column Column
Dout
High-Z*
Invalid Dout Invalid Dout Invalid Dout
HM5117400B Series
Fast Page Mode Read-Modify-Write Cycle
RASP
PRWC
Column Column Column
Address
High-Z*
Dout
Dout
Dout
Dout
HM5117400B Series
Test Mode Cycle
Cycle**
Test Mode Cycle
*,** Reset Cycle
Normal Mode
RAS-only refresh Address, Din,
Test Mode Cycle
Address High-Z
Dout
HM5117400B Series
Package Dimensions
HM5117400BS/BLS Series (CP-26/24DB) Unit:
16.90 17.27
7.62 0.13 8.51 0.13
0.74
2.65 0.12 6.71 0.25
3.50 0.26
0.43 0.10 0.10
1.27
HM5117400BTS/BLTS Series (TTP-26/24DA)
0.63
Unit:
17.14 17.54
7.62
1.27 0.21
9.22
0.40 0.10
1.20
0.10 1.15
0.145 -0.025
0.08 0.18 0.68 0.50 0.10
+0.075
HM5117400B Series
When using this document, keep following mind: This document may, wholly partially, subject change without notice. rights reserved: permitted reproduce duplicate, form, whole part this document without Hitachi's permission.
Hitachi will held responsible damage user that result from accidents other reasons during operation user's unit according this document. Circuitry other examples described herein meant merely indicate characteristics performance Hitachi's semiconductor product. Hitachi assumes responsibility intellectual property claims other problems that result from applications based examples described herein. license granted implication otherwise under patents other rights third party Hitachi, Ltd. MEDICAL APPLICATIONS: Hitachi's products authorized MEDICAL APPLICATIONS without written consent appropriate officer Hitachi's sales company. Such includes, limited life support systems. Buyers Hitachi's products requested notify relevant Hitachi sales office when planning products MEDICAL APPLICATIONS.
Semiconductor Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tokyo (03) 3270-2111 (03) 3270-5109
further information write Hitachi America, Ltd. Semiconductor Div. 2000 Sierra Point Parkway Brisbane, 94005-1835 415-589-8300 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher StraBe D-85622 Feldkirchen Munchen 089-9 80-0 089-9 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Wihtebrook Park Lower Cookham Road Maidenhead Berkshire United Kingdom 0628-585000 0628-778322 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Habour City, Canton Road, Tsim Tsui, Kowloon, Hong Kong 27359218 27306071 Hitachi Asia Pte. Ltd. Collyer Quay #20-00 Hitachi Tower Singapore 0104 535-2100 535-1533
HM5117400B Series
Revision Record
Rev. Date Mar. 1995 Mar. 1996 Contents Modification Initial issue Change format Characteristics Change notes 10,11 Timing Waveforms Change RAS-only refresh cycle CAS-before-RAS refresh cycle Deletion note: tOEH tCWE Deletion Test mode reset cycle Drawn Approved Takahashi Hayakawa
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