Programming Manual ADE-602-083B Rev. 7/14/2000 Hitachi, Ltd.
|
|
|
Top Searches for this datasheet
H8S/2600 Series, H8S/2000 Series
Programming Manual
ADE-602-083B Rev. 7/14/2000 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
H8S/2600 Series H8S/2000 Series built around H8S/2000 core. H8S/2600 H8S/2000 CPUs have same internal 32-bit architecture. Both CPUs execute basic instructions state, have sixteen 16-bit registers, have concise, optimized instruction set. They address 16-Mbyte linear address space.Programs coded highlevel language compiled high-speed executable code. easy migration, instruction upward-compatible with H8/300H, H8/300, H8/300L Series object-code level. H8S/2600 upward-compatible with H8S/2000 object-code level, supports products instructions. This manual gives details H8S/2600 H8S/2000 instructions sued with microcontrollers H8S/2600 Series H8S/2000 Series. hardware details, refer relevant microcontroller hardware manuals.
Rev. 3.0, 07/00, page
Rev. 3.0, 07/00, page
Main Revisions Additions this Edition
Page Item Revisions (See Manual Details) Notes Instruction added Only register ER0, ER1, ER4, should used when using instruction.
Rev. 3.0, 07/00, page
Rev. 3.0, 07/00, page
Contents
Section
Overview 1.1.1 Features 1.1.2 Differences between H8S/2600 H8S/2000 CPU. 1.1.3 Differences from H8/300 CPU. 1.1.4 Differences from H8/300H Operating Modes Address Space Register Configuration 1.4.1 Overview 1.4.2 General Registers 1.4.3 Control Registers. 1.4.4 Initial Register Values Data Formats 1.5.1 General Register Data Formats 1.5.2 Memory Data Formats Instruction 1.6.1 Overview 1.6.2 Instructions Addressing Modes 1.6.3 Table Instructions Classified Function. 1.6.4 Basic Instruction Formats. Addressing Modes Effective Address Calculation
Section
Instruction Descriptions Tables Symbols. 2.1.1 Assembly-Language Format 2.1.2 Operation. 2.1.3 Condition Code 2.1.4 Instruction Format 2.1.5 Register Specification. 2.1.6 Data Access Manipulation Instructions Instruction Descriptions 2.2.1 2.2.1 2.2.1 2.2.2 ADDS 2.2.3 ADDX 2.2.4 2.2.4
Rev. 3.0, 07/00, page
2.2.4 2.2.5 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13 2.2.14 2.2.15 2.2.16 2.2.17 2.2.18 2.2.19 2.2.20 2.2.21 2.2.22 2.2.23 2.2.23 2.2.23 2.2.24 2.2.25 2.2.26 2.2.26 2.2.26 2.2.27 2.2.27 2.2.28 2.2.28 2.2.29 2.2.29 2.2.30 2.2.30 2.2.31 2.2.31 2.2.32 2.2.32 2.2.32 2.2.33 2.2.34
ANDC. ANDC. BAND. Bcc. BCLR. BIAND BILD. BIOR BIST BIXOR. BNOT BOR. BSET BST. BTST BXOR. CLRMAC (B). (W). DIVXS (B). DIVXS DIVXU (B). DIVXU (W). EEPMOV EEPMOV EXTS (W). EXTS EXTU EXTU (B). (W). JMP. JSR.
Rev. 3.0, 07/00, page viii
2.2.35 2.2.35 2.2.35 2.2.35 2.2.36 2.2.37 2.2.38 2.2.39 2.2.39 2.2.39 2.2.39 2.2.39 2.2.39 2.2.39 2.2.39 2.2.39 2.2.40 2.2.41 2.2.42 2.2.42 2.2.43 2.2.43 2.2.44 2.2.44 2.2.44 2.2.45 2.2.46 2.2.46 2.2.46 2.2.47 2.2.47 2.2.47 2.2.48 2.2.48 2.2.49 2.2.49 2.2.50 2.2.50 2.2.51 2.2.51 2.2.51 2.2.51 2.2.51
(B). (B). (W). (W). LDMAC. MAC. (L). (L). (L). MOVFPE. MOVTPE. MULXS (B). MULXS (W). MULXU MULXU (L). (L). ORC. ORC. (L). PUSH PUSH (L). ROTL ROTL ROTL ROTL ROTL
Rev. 3.0, 07/00, page
2.2.51 2.2.52 2.2.52 2.2.52 2.2.52 2.2.52 2.2.52 2.2.53 2.2.53 2.2.53 2.2.53 2.2.53 2.2.53 2.2.54 2.2.54 2.2.54 2.2.54 2.2.54 2.2.54 2.2.55 2.2.56 2.2.57 2.2.57 2.2.57 2.2.57 2.2.57 2.2.57 2.2.58 2.2.58 2.2.58 2.2.58 2.2.58 2.2.58 2.2.59 2.2.59 2.2.59 2.2.59 2.2.59 2.2.59 2.2.60 2.2.60 2.2.60 2.2.60
ROTL ROTR ROTR ROTR ROTR ROTR ROTR ROTXL ROTXL ROTXL ROTXL ROTXL (L). ROTXL (L). ROTXR ROTXR ROTXR ROTXR ROTXR ROTXR RTS. SHAL SHAL SHAL SHAL SHAL SHAL SHAR SHAR SHAR SHAR SHAR SHAR SHLL (B). SHLL (B). SHLL (W). SHLL (W). SHLL SHLL SHLR (B). SHLR (B). SHLR SHLR
Rev. 3.0, 07/00, page
2.2.60 SHLR (L). 2.2.60 SHLR (L). 2.2.61 SLEEP 2.2.62 2.2.62 2.2.62 2.2.62 2.2.63 STM. 2.2.64 STMAC 2.2.65 2.2.65 (W). 2.2.65 2.2.66 SUBS 2.2.67 SUBX 2.2.68 2.2.69 TRAPA 2.2.70 2.2.70 2.2.70 2.2.71 XORC. 2.2.71 XORC. Instruction Instruction Code Operation Code Number States Required Instruction Execution. States During Instruction Execution. Condition Code Modification.
Section
Processing States
Overview Reset State Exception-Handling State. 3.3.1 Types Exception Handling Their Priority 3.3.2 Reset Exception Handling 3.3.3 Trace. 3.3.4 Interrupt Exception Handling Trap Instruction Exception Handling. Program Execution State Bus-Released State Power-Down State. 3.6.1 Sleep Mode. 3.6.2 Software Standby Mode 3.6.3 Hardware Standby Mode.
Rev. 3.0, 07/00, page
Section
Basic Timing
Overview On-Chip Memory (ROM, RAM). On-Chip Supporting Module Access Timing External Address Space Access Timing
Rev. 3.0, 07/00, page
Section
Overview
H8S/2600 H8S/2000 high-speed central processing units with common internal 32-bit architecture. Each upward-compatible with H8/300 H8/300H CPUs. H8S/2600 H8S/2000 have sixteen 16-bit general registers, address 4-Gbyte linear address space, ideal realtime control. 1.1.1 Features
H8S/2600 H8S/2000 have following features.
Upward-compatible with H8/300 H8/300H CPUs
execute H8/300 H8/300H object programs
General-register architecture
Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit
registers)
Sixty-nine basic instructions (H8S/2000 sixty-five)
8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction (H8S/2600 only)
Eight addressing modes
Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) @(d:32,ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, @aa:32] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8,PC) @(d:16,PC)] Memory indirect [@@aa:8]
4-Gbyte address space
Program: Mbytes Data:
Gbytes
Rev. 3.0, 07/00, page
High-speed operation
frequently-used instructions execute states Maximum clock frequency: 8/16/32-bit register-register add/subtract: 8-bit register-register multiply: 8-bit register-register divide: 16-bit register-register multiply: 16-bit register-register divide:
(H8S/2000 CPU: (H8S/2000 CPU: 1000 1000
operating modes
Normal mode Advanced mode
Power-down modes
Transition power-down state SLEEP instruction clock speed selection
1.1.2
Differences between H8S/2600 H8S/2000
Differences between H8S/2600 H8S/2000 follows.
Register configuration
register supported only H8S/2600 CPU.
details, section 1.4, Register Configuration.
Basic instructions
MAC, CLRMAC, LDMAC, STMAC instructions supported only
H8S/2600 CPU. details, section 1.6, Instruction Set, Section Instruction Descriptions.
Number states required execution
number states required execution MULXU MULXS instructions.
details, section 2.6, Number States Required Execution. addition, there defferences address spaces, register functions, power-down states, details, refer relevant microcontroller hardware manual.
Rev. 3.0, 07/00, page
1.1.3
Differences from H8/300
comparison with H8/300 CPU, H8S/2600 H8S/2000 have following enhancements.
More general registers control registers
Eight 16-bit registers, 8-bit 32-bit control registers have been added.
Expanded address space
Normal mode supports same 64-kbyte address space H8/300 CPU. Advanced mode supports maximum 4-Gbyte address space.
Enhanced addressing
addressing modes have been enhanced make effective 4-Gbyte address
space.
Enhanced instructions
Addressing modes bit-manipulation instructions have been enhanced. Signed multiply divide instructions have been added. multiply-and-accumulate instruction been added. (H8S/2600CPU only) Two-bit shift rotate instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added.
Higher speed
Basic instructions execute twice fast.
Rev. 3.0, 07/00, page
1.1.4
Differences from H8/300H
comparison with H8/300H CPU, H8S/2600 H8S/2000 have following enhancements.
Additional control register
8-bit 32-bit control registers have been added.
Expanded address space
Advanced mode supports maximum 4-Gbyte data address space.
Enhanced instructions
Addressing modes bit-manipulation instructions have been enhanced. multiply-and-accumulate instruction been added (H8S/2600 only). Two-bit shift rotate instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added.
Higher speed
Basic instructions execute twice fast.
Rev. 3.0, 07/00, page
Operating Modes
Like H8/300H CPU, H8S/2600 operating modes: normal advanced. Normal mode supports maximum 64-kbyte address space. Advanced mode supports maximum 4-Gbyte total address space, which Mbytes used program code Gbytes data. mode selected with mode pins microcontroller. further information, refer relevant microcontroller hardware manual.
Maximum kbytes, program data areas combined
Normal mode
operating modes
Advanced mode
Maximum 16-Mbyte program area 4-Gbyte data area, maximum Gbytes program data areas combined
Figure Operating Modes Normal Mode exception vector table stack have same structure H8/300 CPU. Address Space: maximum address space kbytes accessed, H8/300 CPU. Extended Registers (En): extended registers used 16-bit registers, upper 16-bit segments 32-bit registers. When used 16-bit register contain value, even when corresponding general register used address register. general register referenced register indirect addressing mode with pre-decrement (@-Rn) post-increment (@Rn+) carry borrow occurs, however, value corresponding extended register will affected. Instruction Set: additional instructions addressing modes found H8/300 used. Only lower bits effective addresses (EA) valid.
Rev. 3.0, 07/00, page
Exception Vector Table Memory Indirect Branch Addresses: normal mode area starting H'0000 allocated exception vector table. branch address stored bits (figure 1.2). exception vector table differs depending microcontroller. Refer relevant microcontroller hardware manual further information.
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Power-on reset exception vector Manual reset exception vector
(Reserved system use)
Exception vector table
Exception vector Exception vector
Figure Exception Vector Table (Normal Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. normal mode operand 16-bit word operand, providing 16-bit branch address. Branch addresses stored area from H'0000 H'00FF. Note that this area also used exception vector table.
Rev. 3.0, 07/00, page
Stack Structure: When program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 1.3. When invalid, pushed onto stack. details, relevant hardware manual.
bits)
EXR*1 Reserved*1,*3 CCR*3 bits)
Subroutine Branch
Exception Handling
Notes: When used stored stack. when used. Ignored return.
Figure Stack Structure Normal Mode Advanced Mode advanced mode data address space larger than H8/300H CPU. Address Space: 4-Gbyte maximum address space provides linear access maximum Mbytes program code maximum Gbytes data. Extended Registers (En): extended registers used 16-bit registers, upper 16-bit segments 32-bit registers address registers. Instruction Set: instructions addressing modes used.
Rev. 3.0, 07/00, page
Exception Vector Table Memory Indirect Branch Addresses: advanced mode area starting H'00000000 allocated exception vector table units bits. each bits, upper bits ignored branch address stored lower bits (figure 1.4). exception vector table differs depending microcontroller. Refer relevant microcontroller hardware manual further information.
H'00000000
Reserved Power-on reset exception vector
H'00000003 H'00000004 Reserved Manual reset exception vector H'00000007 H'00000008 Exception vector table
H'0000000B H'0000000C
(Reserved system use)
H'00000010
Reserved Exception vector
Figure Exception Vector Table (Advanced Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. advanced mode operand 32-bit longword operand, providing 32-bit branch address. upper bits these bits reserved area that regarded H'00. Branch addresses stored area from H'00000000 H'000000FF. Note that this area also used exception vector table.
Rev. 3.0, 07/00, page
Stack Structure: advanced mode, when program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 1.5. When invalid, pushed onto stack. details, relevant hardware manual.
Reserved bits)
EXR*1 Reserved*1,*3 bits)
Subroutine Branch
Exception Handling
Notes: When used stored stack. when used. Ignored return.
Figure Stack Structure Advanced Mode
Rev. 3.0, 07/00, page
Address Space
Figure shows memory H8S/2600 CPU. H8S/2600 provides linear access maximum 64-kbyte address space normal mode, maximum 4-Gbyte address space advanced mode. address space differs depending operating mode. details, refer relevant microcontroller hardware manual.
H'0000 H'00000000
H'FFFF
Program area
H'00FFFFFF
Data area
H'FFFFFFFF Normal Mode Advanced Mode
Figure Memory
Rev. 3.0, 07/00, page
1.4.1
Register Configuration
Overview
CPUs have internal registers shown figure 1.7. There types registers: general registers control registers. H8S/2000 does support register.
General Registers (Rn) Extended Registers (En) (SP) Control Registers (CR) Legend EXR: CCR: Sign extension MACL MACH
Stack pointer Program counter Extended control register Trace Interrupt mask bits Condition-code register Interrupt mask User interrupt mask
MAC:
Half-carry flag User Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register
Figure Registers
Rev. 3.0, 07/00, page
1.4.2
General Registers
CPUs have eight 32-bit general registers. These general registers functionally alike used both address registers data registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. Figure illustrates usage general registers. usage each register selected independently.
Address registers 32-bit registers
16-bit registers registers (extended registers)
8-bit registers
registers (ER0 ER7) registers
registers (R0H R7H)
registers (R0L R7L)
Figure Usage General Registers
Rev. 3.0, 07/00, page
General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Free area
(ER7)
Stack area
Figure Stack 1.4.3 Control Registers
control registers 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), 64-bit multiply-accumulate register (MAC: H8S/2600 only). Program Counter (PC) This 24-bit counter indicates address next instruction will execute. length instructions bits (one word) multiple bits, least significant ignored. When instruction fetched, least significant regarded Extended Control Register (EXR) This 8-bit register contains trace three interrupt mask bits I0). 7-Trace (T): Selects trace mode. When this cleared instructions executed sequence. When this trace exception generated each time instruction executed. Bits 3-Reserved: These bits reserved, always read Bits 0-Interrupt Mask Bits I0): These bits designate interrupt mask level details refer relevant microcontroller hardware manual.
Rev. 3.0, 07/00, page
Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. interrupts, including NMI, disabled three states after these instructions executed, except STC. Condition-Code Register (CCR) This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. 7-Interrupt Mask (I): Masks interrupts other than when (NMI accepted regardless setting.) hardware start exceptionhandling sequence. 6-User Interrupt Mask (UI): written read software using LDC, STC, ANDC, ORC, XORC instructions. This also used interrupt mask bit. details refer relevant microcontroller hardware manual. 5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise. 4-User (U): written read software using LDC, STC, ANDC, ORC, XORC instructions. 3-Negative Flag (N): Stores value most significant (sign bit) data. 2-Zero Flag (Z): indicate zero data, cleared indicate non-zero data. 1-Overflow Flag (V): when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): when carry occurs, cleared otherwise. Used
instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, store value shifted
carry flag also used accumulator manipulation instructions. Some instructions leave some flag bits unchanged. action each instruction flag bits, refer detailed descriptions instructions starting section 2.2.1.
Rev. 3.0, 07/00, page
Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. flags used branching conditions conditional branch (Bcc) instructions. Multiply-Accumulate Register (MAC) register supported only H8S/2600 CPU. This 64-bit register stores results multiply-and-accumulate operations. consists 32-bit registers denoted MACH MACL. lower bits MACH valid; upper bits sign extension. 1.4.4 Initial Register Values
Reset exception handling loads CPU's program counter (PC) from vector table, clears trace sets interrupt mask bits other bits general registers initialized. particular, stack pointer (ER7) initialized. stack pointer should therefore initialized MOV.L instruction executed immediately after reset.
Rev. 3.0, 07/00, page
Data Formats
CPUs process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data. 1.5.1 General Register Data Formats
Figure 1.10 shows data formats general registers.
Data Type Register Number Data Format
1-bit data
Don't care
1-bit data
Don't care
4-bit data
Upper
Lower
Don't care
4-bit data
Don't care
Upper
Lower
Byte data
Don't care Don't care
Byte data
Figure 1.10 General Register Data Formats
Rev. 3.0, 07/00, page
Word data
Word data Longword data
Legend ERn: General register General register General register RnH: General register RnL: General register MSB: Most significant LSB: Least significant
Figure 1.10 General Register Data Formats (cont)
Rev. 3.0, 07/00, page
1.5.2
Memory Data Formats
Figure 1.11 shows data formats memory. access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches.
Data Type Address 1-bit data Address Data Format
Byte data
Address
Word data
Address Address
Longword data
Address Address Address Address
Figure 1.11 Memory Data Formats When stack pointer (ER7) used address register access stack, operand size should word size longword size.
Rev. 3.0, 07/00, page
1.6.1
Instruction
Overview
H8S/2600 69types instructions, while H8S/2000 types. instructions classified function shown table 1.1. detailed description each instruction, section 2.2, Instruction Descriptions. Table
Function Data transfer
Instruction Classification
Instructions POP* PUSH* LDM, SMOVFPE, MOVTPE
Size
Types
Arithmetic operations
ADD, SUB, CMP, ADDX, SUBX, DAA, INC, ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*
MAC, LDMAC, STMAC, CLRMAC* Logic operations Shift manipulation Branch System control AND, XOR,
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* JMP, BSR, JSR,
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
Block data transfer EEPMOV H8S/2600 CPU: Total types
H8S/2000 CPU: Total types
Notes: B-byte size; W-word size; L-longword size. MAC, LDMAC, STMAC, CLRMAC instructions supported only H8S/2600 CPU. POP.W PUSH.W identical MOV.W @SP+, MOV.W POP.L PUSH.L identical MOV.L @SP+, MOV.L ERn, @-SP. generic designation conditional branch instruction. Only register ER0, ER1, ER4, should used when using instruction.
Rev. 3.0, 07/00, page
1.6.2
Addressing Modes
Table
Function
Instruction
@ERn
@(d:16,ERn)
@(d:32,ERn)
@-ERn/@ERn+
@aa:8
@aa:16
@aa:24
@aa:32
@(d:8,PC)
@(d:16,PC)
@@aa:8
Data transfer
POP, PUSH
LDM, S
MOVEPE, MOVTPE
Rev. 3.0, 07/00, page
Arithmetic operations
ADD,
ADDX, SUBX
ADDS, SUBS
INC,
DAA,
Instructions Addressing Modes
MULXU, DIVXU
MULXS, DIVXS
EXTU, EXTS
TAS*2
MAC*1
Combinations Instructions Addressing Modes
CLRMAC*1
Table indicates combinations instructions addressing modes that H8S/2600 H8S/2000 use.
LDMAC*1, STMAC*1
Addressing Modes
Function
Instruction
@ERn
@(d:16,ERn)
@(d:32,ERn)
@-ERn/@ERn+
@aa:8
@aa:16
@aa:24
@aa:32
@(d:8,PC)
@(d:16,PC)
@@aa:8
Logic operations
AND,
Shift
manipulation
Branch
Bcc,
JMP,
System control
TRAPA
SLEEP
ANDC, ORC, XORC
Block data transfer
Legend Byte Word Longword
Rev. 3.0, 07/00, page
Notes: Supported only H8S/2600 Only register ER0, ER1, ER4, should used when using instruction.
1.6.3
Table Instructions Classified Function
Table summarizes instructions each functional category. notation used table defined next.
Operation Notation (EAd) (EAs) #IMM disp General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical Logical Logical exclusive Move Logical (logical complement) 16-, 24-, 32-bit length
:8/:16/:24/:32
Note: General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit registers (ER0 ER7).
Rev. 3.0, 07/00, page
Table
Type Data transfer
Instructions Classified Function
Instruction Size*
Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register.
B/W/L
MOVFPE
(EAs) Moves external memory contents (addressed @aa:16) general register synchronization with clock.
MOVTPE
(EAs) Moves general register contents external memory location (addressed @aa:16) synchronization with clock.
@SP+ Pops register from stack. POP.W identical MOV.W @SP+, POP.L identical MOV.L @SP+, ERn.
PUSH
@-SP Pushes register onto stack. PUSH.W identical MOV.W @-SP. PUSH.L identical MOV.L ERn, @-SP.
S
@SP+ (register list) Pops more general registers from stack. (register list) @-SP Pushes more general registers onto stack.
Rev. 3.0, 07/00, page
Type Arithmetic operations
Instruction
Size*
Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from byte data general register. SUBX instruction.)
B/W/L
ADDX SUBX
#IMM Performs addition subtraction with carry borrow byte data general registers, immediate data data general register.
B/W/L
Increments decrements general register (Byte operands incremented decremented only.)
ADDS SUBS
Adds subtracts value from data 32-bit register.
decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4bit data.
MULXU
Performs unsigned multiplication data general registers: either bits bits bits bits bits bits.
MULXS
Performs signed multiplication data general registers: either bits bits bits bits bits bits.
DIVXU
Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder.
DIVXS
Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder.
Rev. 3.0, 07/00, page
Type Arithmetic operations
Instruction
Size*
Function #IMM Compares data general register with data another general register with immediate data, sets bits according result.
B/W/L
B/W/L
Takes two's complement (arithmetic complement) data general register.
EXTU
(zero extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, padding with zeros left.
EXTS
(sign extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, extending sign bit.
@ERd (<bit @ERd)*
Tests memory contents, sets most significant (bit (EAs) (EAd) Performs signed multiplication memory contents adds result multiply-accumulate register. following operations performed: bits bits bits bits, saturating bits bits bits bits, non-saturating Supported H8S/2600 only. CLRMAC Clears multiply-accumulate register zero. Supported H8S/2600 only. LDMAC STMAC MAC, Transfers data between general register multiply-accumulate register. Supported H8S/2600 only.
Rev. 3.0, 07/00, page
Type Logic operations
Instruction
Size*
Function #IMM Performs logical operation general register another general register immediate data.
B/W/L
B/W/L
#IMM Performs logical operation general register another general register immediate data.
B/W/L
#IMM Performs logical exclusive operation general register another general register immediate data.
B/W/L
(Rd) (Rd)
Takes one's complement general register contents.
Shift operations
SHAL SHAR
B/W/L
(shift) Performs arithmetic shift general register contents. 1-bit 2-bit shift possible.
SHLL SHLR ROTL ROTR ROTXL ROTXR
B/W/L
(shift) Performs logical shift general register contents. 1-bit 2-bit shift possible.
B/W/L
(rotate) Rotates general register contents. 1-bit 2-bit rotation possible.
B/W/L
(rotate) Rotates general register contents through carry bit. 1-bit 2-bit rotation possible.
Rev. 3.0, 07/00, page
Type Bit-manipulation instructions
Instruction BSET
Size*
Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower three bits general register.
BCLR
(<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower three bits general register.
BNOT
(<bit-No.> <EAd>) (<bit-No.> <EAd>)
Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register.
BTST
(<bit-No.> <EAd>)
Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register.
BAND
(<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag.
BIAND
(<bit-No.> <EAd>) ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
(<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag.
BIOR
(<bit-No.> <EAd>) carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
Rev. 3.0, 07/00, page
Type Bit-manipulation instructions
Instruction BXOR
Size*
Function (<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag.
BIXOR
(<bit-No.> <EAd>) Exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
(<bit-No.> <EAd>) Transfers specified general register memory operand carry flag.
BILD
(<bit-No.> <EAd>)
Transfers inverse specified general register memory operand carry flag. number specified 3-bit immediate data.
(<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand.
BIST
(<bit-No.> <EAd>)
Transfers inverse carry flag value specified general register memory operand. number specified 3-bit immediate data.
Rev. 3.0, 07/00, page
Type Branch instructions
Instruction
Size*
Function Branches specified address specified condition true. branching conditions listed below. Mnemonic BRA(BT) BRN(BF) BCC(BHS) BCS(BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=1
Greater equal
Branches unconditionally specified address. Branches subroutine specified address. Branches subroutine specified address. Returns from subroutine
Rev. 3.0, 07/00, page
Type System control instructions
Instruction TRAPA SLEEP
Size*
Function Starts trap-instruction exception handling. Returns from exception-handling routine. Causes transition power-down state. (EAs) CCR, (EAs) Moves source operand contents immediate data EXR. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid.
(EAd), (EAd) Transfers contents general register memory. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid.
ANDC
#IMM CCR, #IMM Logically ANDs contents with immediate data.
#IMM CCR, #IMM Logically contents with immediate data.
XORC
#IMM CCR, #IMM Logically exclusive-ORs contents with immediate data.
Only increments program counter.
Rev. 3.0, 07/00, page
Type Block data transfer instruction
Instruction EEPMOV.B
Size*
Function
then Repeat @ER5+ @ER6+ Until else next;
then Repeat @ER5+ @ER6+ Until else next; Transfers data block according parameters general registers ER5, ER6. size block (bytes) ER5: starting source address ER6: starting destination address Execution next instruction begins soon transfer completed.
EEPMOV.W
Notes: Size refers operand size. Byte Word Longword Only register ER0, ER1, ER4, should used when using instruction.
Rev. 3.0, 07/00, page
1.6.4
Basic Instruction Formats
H8S/2600 H8S/2000 instructions consist 2-byte (1-word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Operation Field: Indicates function instruction, addressing mode, operation carried operand. operation field always includes first four bits instruction. Some instructions have operation fields. Register Field: Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension: Eight, bits specifying immediate data, absolute address, displacement. Condition Field: Specifies branching condition instructions. Figure 1.12 shows examples instruction formats.
Operation field only NOP, RTS, etc.
Operation field register fields ADD.B etc.
Operation field, register fields, effective address extension (disp) Operation field, effective address extension, condition field (disp) d:8, MOV.B @(d:16, Rn), etc.
Figure 1.12 Instruction Formats
Rev. 3.0, 07/00, page
Addressing Modes Effective Address Calculation
Addressing Modes CPUs support eight addressing modes listed table 1.4. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except program-counter relative memory indirect. manipulation instructions register direct, register indirect, absolute addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table
Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
Register Direct-Rn: register field instruction specifies 16-, 32-bit general register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32-bit registers. Register Indirect-@ERn: register field instruction code specifies address register (ERn) which contains address operand memory. address program instruction address, lower bits valid upper bits assumed (H'00). Register Indirect with Displacement-@(d:16, ERn) @(d:32, ERn): 16-bit 32-bit displacement contained instruction added address register (ERn) specified register field instruction, gives address memory operand. 16-bit displacement sign-extended when added.
Rev. 3.0, 07/00, page
Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn:
Register indirect with post-increment-@ERn+ register field instruction code specifies address register (ERn) which contains address memory operand. After operand accessed, added address register contents stored address register. value added byte access, word access, longword access. word longword access, register value should even.
Register indirect with pre-decrement-@-ERn value subtracted from address register (ERn) specified register field instruction code, result becomes address memory operand. result also stored address register. value subtracted byte access, word access, longword access. word longword access, register value should even.
Absolute Address-@aa:8, @aa:16, @aa:24, @aa:32: instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24), bits long (@aa:32). access data, absolute address should bits (@aa:8), bits (@aa:16), bits (@aa:32) long. 8-bit absolute address, upper bits assumed (H'FFFFFF). 16-bit absolute address upper bits sign extension. 32-bit absolute address access entire address space. 24-bit absolute address (@aa:24) indicates address program instruction. upper bits assumed (H'00). Table indicates accessible absolute address ranges. Table Absolute Address Access Ranges
Normal Mode bits (@aa:8) bits (@aa:16) bits (@aa:32) Program instruction address bits (@aa:24) H'FF00 H'FFFF H'0000 H'FFFF Advanced Mode H'FFFFFF00 H'FFFFFFFF H'00000000 H'00007FFF, H'FFFF8000 H'FFFFFFFF H'00000000 H'FFFFFFFF H'00000000 H'00FFFFFF
Absolute Address Data address
further details accessible range, refer relevant microcontroller hardware manual.
Rev. 3.0, 07/00, page
Immediate-#xx:8, #xx:16, #xx:32: instruction contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. ADDS, SUBS, INC, instructions contain immediate data implicitly. Some manipulation instructions contain 3-bit immediate data instruction code, specifying number. TRAPA instruction contains 2-bit immediate data instruction code, specifying vector address. Program-Counter Relative-@(d:8, @(d:16, PC): This mode used instructions. 8-bit 16-bit displacement contained instruction sign-extended added 24-bit contents generate branch address. Only lower bits this branch address valid; upper bits assumed (H'00). value which displacement added address first byte next instruction, possible branching range -126 +128 bytes (-63 words) -32766 +32768 bytes (-16383 +16384 words) from branch instruction. resulting value should even number. Memory Indirect-@@aa:8: This mode used instructions. second byte instruction specifies memory operand 8-bit absolute address. This memory operand contains branch address. upper bits absolute address assumed address range (H'0000 H'00FF normal mode, H'00000000 H'000000FF advanced mode). normal mode memory operand word operand branch address bits long. advanced mode memory operand longword operand, first byte which assumed (H'00). Note that first part address range also exception vector area. further details refer relevant microcontroller hardware manual.
Specified @aa:8
Branch address
Specified @aa:8
Reserved Branch address
Normal Mode
Advanced Mode
Figure 1.13 Branch Address Specification Memory Indirect Mode
Rev. 3.0, 07/00, page
address specified word longword memory access, branch address, least significant regarded causing data accessed instruction code fetched address preceding specified address. (For further information, section 1.5.2, Memory Data Formats.) Effective Address Calculation Table indicates effective addresses calculated each addressing mode. normal mode upper bits effective address ignored order generate 16-bit address.
Rev. 3.0, 07/00, page
Effective Address Calculation
Addressing Mode Instruction Format
Effective Address (EA)
Operand general register contents.
Table
Register direct (Rn)
General register contents
Register indirect (@ERn)
General register contents disp Sign extension disp
Register indirect with displacement @(d:16, ERn) @(d:32, ERn)
Effective Address Calculation
General register contents
Register indirect with post-increment pre-decrement Register indirect with post-increment @ERn+
General register contents
Register indirect with pre-decrement @-ERn
Operand Size Value added Byte Word Longword
Rev. 3.0, 07/00, page
Effective Address Calculation
Addressing Mode Instruction Format
Effective Address (EA)
H'FFFFFF
Absolute address
@aa:8
@aa:16 Sign extension
Rev. 3.0, 07/00, page
H'00 Operand immediate data.
@aa:24
@aa:32
Immediate #xx:8/#xx:16/#xx:32
Effective Address Calculation contents
Addressing Mode Instruction Format
Effective Address (EA)
Program-counter relative
@(d:8, PC)/@(d:16,
Sign extension disp H'00
disp
Memory indirect @@aa:8
Normal mode
H'000000
H'0000
Memory contents
Advanced mode
H'000000 Reserved Memory contents H'00
Rev. 3.0, 07/00, page
Rev. 3.0, 07/00, page
Section Instruction Descriptions
Tables Symbols
This section explains read tables section 2.2, describing each instruction. Note that descriptions some instructions extend over more than page. Mnemonic (Full Name)
Operation Assembly-Language Format Operand Size Description Available Registers Operand Format Number States Required Execution Condition Code
Type
[10] Notes
Mnemonic (Full Name): Gives full mnemonic names instruction. Type: Indicates type instruction. Operation: Describes instruction symbolic notation. (See section 2.1.2, Operation.) Assembly-Language Format: Indicates assembly-language format instruction. (See section 2.1.1, Assembler Format.) Operand Size: Indicates available operand sizes. Condition Code: Indicates effect instruction execution flag bits CCR. (See section 2.1.3, Condition Code.) Description: Describes operation instruction detail. Available Registers: Indicates which registers specified register field instruction. Operand Format Number States Required Execution: Shows addressing modes instruction format together with number states required execution. [10] Notes: Gives notes concerning execution instruction.
Rev. 3.0, 07/00, page
2.1.1
Assembly-Language Format
Example: ADD. <EAs>,
Destination operand Source operand Size Mnemonic
operand size byte (B), word (W), longword (L). Some instructions restricted limited operand sizes. symbol <EA> indicates that more addressing modes used. H8S/2600 supports eight addressing modes listed next. Effective address calculation described section 1.7, Addressing Modes Effective Address Calculation.
Symbol @ERn @(d:16, ERn)/@(d:32, ERn) @ERn+/@-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8, PC)/@(d:16, @@aa:8 Addressing Mode Register direct Register indirect Register indirect with displacement (16-bit 32-bit) Register indirect with post-increment pre-decrement Absolute address (8-bit, 16-bit, 24-bit, 32-bit) Immediate (8-bit, 16-bit, 32-bit) Program-counter relative (8-bit 16-bit) Memory indirect
suffixes :16, :24, omitted. particular, :16, :24, designation omitted absolute address displacement, assembler will optimize length according value range. details, refer H8S, H8/300 Series cross assembler user's manual. Note: ":2" ":3" "#xx (:2)" "#xx (:3)" indicate specifiable length. include (:2) (:3) assembler notation. Example: TRAPA
Rev. 3.0, 07/00, page
2.1.2
Operation
symbols used operation descriptions defined follows.
(EAd) (EAs) #IMM disp General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Subtract Multiply Divide Logical Logical Logical exclusive Transfer from operand left operand right, transition from state left state right Logical (logical complement) Contents effective address operand 16-, 24-, 32-bit length
:8/:16/ :24/:32
Note: General registers include 8-bit registers (R0H R7L), 16-bit registers E7), 32-bit registers (ER0 ER7).
Rev. 3.0, 07/00, page
2.1.3
Condition Code
symbols used condition-code description defined follows.
Symbol
Meaning Changes according result instruction execution Undetermined guaranteed value) Always cleared Always affected execution instruction Varies depending conditions; notes
details changes condition code, section 2.8, Condition Code Modification. 2.1.4 Instruction Format
symbols used instruction format descriptions listed below.
Symbol disp ers, erd, Meaning Immediate data bits) Absolute address bits) Displacement bits) Register field bits). symbols correspond operand symbols Register field bits). symbols ers, erd, correspond operand symbols ERs, ERd, ERn.
Rev. 3.0, 07/00, page
2.1.5
Register Specification
Address Register Specification: When general register used address register [@ERn, @(d:16, ERn), @(d:32, ERn), @ERn+, @-ERn], register specified 3-bit register field (ers erd). Data Register Specification: general register used 32-bit, 16-bit, 8-bit data register. When used 32-bit register, specified 3-bit register field (ers, erd, ern). When used 16-bit register, specified 4-bit register field (rs, rn). lower bits specify register number. upper specify extended register (En) cleared specify general register (Rn). When used 8-bit register, specified 4-bit register field (rs, rn). lower bits specify register number. upper specify register (RnL) cleared specify high register (RnH). This shown next.
Address Register 32-Bit Register Register Field General Register
16-Bit Register Register Field 0000 0001 0111 1000 1001 1111 General Register
8-Bit Register Register Field 0000 0001 0111 1000 1001 1111 General Register
Rev. 3.0, 07/00, page
2.1.6
Data Access Manipulation Instructions
data accessed n-th byte operand general register memory. number given 3-bit immediate data, lower bits general register value. Example
BSET R1L, Don't care
number
Example load address H'FFFF02 into accumulator
@H'FFFF02
H'FFFF02
Load
operand size addressing mode indicated register memory operand data.
Rev. 3.0, 07/00, page
Instruction Descriptions
instructions described starting section 2.2.1.
Rev. 3.0, 07/00, page
2.2.1
Binary Condition Code
(ADD Binary) Operation (EAs)
Assembly-Language Format ADD.B <EAs>,
Operand Size Byte
there carry otherwise cleared result negative; otherwise cleared result zero; otherwise cleared overflow occurs; otherwise cleared there carry otherwise cleared
Description This instruction adds source operand contents 8-bit register (destination operand) stores result 8-bit register
Available Registers R7L, R7L,
Operand Format Number States Required Execution
Addressing Mode Immediate Register direct Mnemonic ADD.B ADD.B Operands #xx:8, Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.1
Binary Condition Code
(ADD Binary) Operation (EAs)
Assembly-Language Format ADD.W <EAs>,
Operand Size Word
there carry otherwise cleared result negative; otherwise cleared result zero; otherwise cleared overflow occurs; otherwise cleared there carry otherwise cleared
Description This instruction adds source operand contents 16-bit register (destination operand) stores result 16-bit register
Available Registers
Operand Format Number States Required Execution
Addressing Mode Immediate Register direct Mnemonic ADD.W ADD.W Operands #xx:16, Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.1
Binary Condition Code
(ADD Binary) Operation (EAs)
Assembly-Language Format ADD.L <EAs>,
Operand Size Longword
there carry otherwise cleared result negative; otherwise cleared result zero; otherwise cleared overflow occurs; otherwise cleared there carry otherwise cleared
Description This instruction adds source operand contents 32-bit register (destination operand) stores result 32-bit register ERd.
Available Registers ERd: ERs:
Operand Format Number States Required Execution
Addressing Mode Immediate Register direct Instruction Format Mnemonic ADD.L ADD.L Operands byte #xx:32, ERs, byte byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.2
ADDS Binary Address Data Condition Code
ADDS (ADD with Sign extension) Operation
Assembly-Language Format ADDS ADDS ADDS Operand Size Longword
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Description This instruction adds immediate value contents 32-bit register (destination operand). Unlike instruction, does affect condition code flags.
Available Registers ERd:
Operand Format Number States Required Execution
Addressing Mode Register direct Register direct Register direct Mnemonic ADDS ADDS ADDS Operands Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.3
ADDX with Carry Condition Code
ADDX (ADD with eXtend carry) Operation (EAs)
Assembly-Language Format ADDX <EAs>,
Operand Size Byte
there carry otherwise cleared result negative; otherwise cleared result zero; otherwise cleared overflow occurs; otherwise cleared there carry otherwise cleared
Description This instruction adds source operand carry flag contents 8-bit register (destination operand) stores result 8-bit register
Available Registers R7L, R7L,
Operand Format Number States Required Execution
Addressing Mode Immediate Register direct Mnemonic ADDX ADDX Operands #xx:8, Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.4
Logical Condition Code
(AND logical) Operation
(EAs)
Assembly-Language Format AND.B <EAs>,
Operand Size Byte
Previous value remains unchanged. result negative; otherwise cleared result zero; otherwise cleared Always cleared Previous value remains unchanged.
Description This instruction ANDs source operand with contents 8-bit register (destination operand) stores result 8-bit register
Available Registers R7L, R7L,
Operand Format Number States Required Execution
Addressing Mode Immediate Register direct Mnemonic AND.B AND.B Operands #xx:8, Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.4
Logical Condition Code
(AND logical) Operation
(EAs)
Assembly-Language Format AND.W <EAs>,
Operand Size Word
Previous value remains unchanged. result negative; otherwise cleared result zero; otherwise cleared Always cleared Previous value remains unchanged.
Description This instruction ANDs source operand with contents 16-bit register (destination operand) stores result 16-bit register
Available Registers
Operand Format Number States Required Execution
Addressing Mode Immediate Register direct Mnemonic AND.W AND.W Operands #xx:16, Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.4
Logical Condition Code
(AND logical) Operation
(EAs)
Assembly-Language Format AND.L <EAs>,
Operand Size Longword
Previous value remains unchanged. result negative; otherwise cleared result zero; otherwise cleared Always cleared Previous value remains unchanged.
Description This instruction ANDs source operand with contents 32-bit register (destination operand) stores result 32-bit register ERd.
Available Registers ERd: ERs:
Operand Format Number States Required Execution
Addressing Mode Immediate Register direct Instruction Format Mnemonic AND.L AND.L Operands byte #xx:32, ERs, byte byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.5
ANDC Logical with Condition Code
ANDC (AND Control register) Operation
#IMM
Assembly-Language Format ANDC #xx:8,
Operand Size Byte
Stores corresponding result. Stores corresponding result. Stores corresponding result. Stores corresponding result. Stores corresponding result. Stores corresponding result. Stores corresponding result. Stores corresponding result.
Description This instruction ANDs contents condition-code register (CCR) with immediate data stores result condition-code register. interrupt requests, including NMI, accepted immediately after execution this instruction.
Operand Format Number States Required Execution
Addressing Mode Immediate Mnemonic ANDC Operands #xx:8, Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.5
ANDC Logical with Condition Code
ANDC (AND Control register) Operation
#IMM
Assembly-Language Format ANDC #xx:8,
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size Byte
Description This instruction ANDs contents extended control register (EXR) with immediate data stores result extended control register. interrupt requests, including NMI, accepted three states after execution this instruction.
Operand Format Number States Required Execution
Addressing Mode Immediate Mnemonic ANDC Operands #xx:8, Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.6
BAND Logical Condition Code
BAND (Bit AND) Operation
(<bit No.> <EAd>)
Assembly-Language Format BAND #xx:3, <EAd>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores result operation.
Operand Size Byte
Description This instruction ANDs specified destination operand with carry flag stores result carry flag. number specified 3-bit immediate data. destination operand contents remain unchanged.
Specified #xx:3 <EAd>
Available Registers R7L, ERd:
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
BAND (Bit AND)
Register direct
BAND
#xx:3,
Register indirect
BAND
#xx:3, @ERd
Absolute address
BAND
#xx:3, @aa:8
Absolute address
BAND
#xx:3, @aa:16
Absolute address
BAND
#xx:3, @aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
Rev. 3.0, 07/00, page
Logical
2.2.7
Conditional Branch Condition Code
(Branch conditionally) Operation condition true, then disp else next;
Assembly-Language Format
disp Condition field
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size
Description condition specified condition field (cc) true, displacement added program counter (PC) execution branches resulting address. condition false, next instruction executed. value used address calculation starting address instruction immediately following instruction. displacement signed 8-bit 16-bit value. branch destination address located range from -126 +128 bytes 32766 +32768 bytes from instruction.
Mnemonic (BT) (BF) (BHS) (BLO) Meaning Always (true) Never (false) HIgh Same Carry Clear (High Same) Carry (LOw) Equal EQual oVerflow Clear oVerflow PLus MInus Greater Equal Less Than Greater Than Less Equal 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Condition True False Z(NV) Z(NV) Signed/Unsigned*
(unsigned) (unsigned) (unsigned) (unsigned) (unsigned signed) (unsigned signed)
(signed) (signed) (signed) (signed)
Note: immediately preceding instruction instruction, general register contents (destination operand) source operand.
Rev. 3.0, 07/00, page
(Branch conditionally) Operand Format Number States Required Execution
Addressing Mode Mnemonic Operands d:16 d:16 d:16 d:16 d:16 d:16 d:16 d:16 d:16 d:16 d:16 d:16 d:16 d:16 d:16 d:16 byte
Conditional Branch
Program-counter (BT) relative Program-counter (BF) relative Program-counter relative Program-counter relative Program-counter (BHS) relative Program-counter (BLO) relative Program-counter relative Program-counter relative Program-counter relative Program-counter relative Program-counter relative Program-counter relative Program-counter relative Program-counter relative Program-counter relative Program-counter relative
Instruction Format byte byte byte disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp
States
Notes branch destination address must even. machine language BRA, BRN, BCC, identical BHS, BLO, respectively.
Rev. 3.0, 07/00, page
2.2.8
BCLR Clear Condition Code
BCLR (Bit CLeaR) Operation
(<bit No.> <EAd>)
Assembly-Language Format BCLR #xx:3, <EAd> BCLR <EAd>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size Byte
Description This instruction clears specified destination operand number specified 3-bit immediate data, lower three bits 8-bit register specified tested. condition-code flags altered.
Specified #xx:3 <EAd>
Available Registers R7L, ERd: R7L,
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
Register direct
BCLR
#xx:3,
BCLR (Bit CLeaR)
Register indirect
BCLR
#xx:3, @ERd
Absolute address
BCLR
#xx:3, @aa:8
Absolute address
BCLR
#xx:3, @aa:16
Absolute address
BCLR
#xx:3, @aa:32
Register direct
BCLR
Register indirect
BCLR
@ERd
Absolute address
BCLR
@aa:8
Absolute address
BCLR
@aa:16
Absolute address
BCLR
@aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
Rev. 3.0, 07/00, page
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
Clear
2.2.9
BIAND Logical Condition Code
BIAND (Bit Invert AND) Operation
(<bit No.> <EAd>)]
Assembly-Language Format BIAND #xx:3, <EAd>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores result operation.
Operand Size Byte
Description This instruction ANDs inverse specified destination operand with carry flag stores result carry flag. number specified 3-bit immediate data. destination operand contents remain unchanged.
Specified #xx:3 <EAd> Invert
Available Registers R7L, ERd:
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
Register direct
BIAND
#xx:3,
Register indirect
BIAND
#xx:3, @ERd
BIAND (Bit Invert AND)
Absolute address
BIAND
#xx:3, @aa:8
Absolute address
BIAND
#xx:3, @aa:16
Absolute address
BIAND
#xx:3, @aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
Rev. 3.0, 07/00, page
Logical
2.2.10
BILD Load Condition Code
BILD (Bit Invert LoaD) Operation
(<bit No.> <EAd>)
Assembly-Language Format BILD #xx:3, <EAd>
Operand Size Byte
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Loaded with inverse specified bit.
Description This instruction loads inverse specified from destination operand into carry flag. number specified 3-bit immediate data. destination operand contents remain unchanged.
Specified #xx:3 <EAd>
Invert
Available Registers R7L, ERd:
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
Register direct
BILD
#xx:3,
Register indirect
BILD
#xx:3, @ERd
BILD (Bit Invert LoaD)
Absolute address
BILD
#xx:3, @aa:8
Absolute address
BILD
#xx:3, @aa:16
Absolute address
BILD
#xx:3, @aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
Load
Rev. 3.0, 07/00, page
2.2.11
BIOR Logical Condition Code
BIOR (Bit Invert inclusive Operation
(<bit No.> <EAd>)]
Assembly-Language Format BIOR #xx:3, <EAd>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores result operation.
Operand Size Byte
Description This instruction inverse specified destination operand with carry flag stores result carry flag. number specified 3-bit immediate data. destination operand contents remain unchanged.
Specified #xx:3 <EAd> Invert
Available Registers R7L, ERd:
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
Register direct
BIOR
#xx:3,
Register indirect
BIOR
#xx:3, @ERd
Absolute address
BIOR
#xx:3, @aa:8
BIOR (Bit Invert inclusive
Absolute address
BIOR
#xx:3, @aa:16
Absolute address
BIOR
#xx:3, @aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
Logical
Rev. 3.0, 07/00, page
2.2.12
BIST Store Condition Code
BIST (Bit Invert STore) Operation
(<bit No.> <EAd>)
Assembly-Language Format BIST #xx:3, <EAd>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size Byte
Description This instruction stores inverse carry flag specified location destination operand. number specified 3-bit immediate data. Other bits destination operand remain unchanged.
Specified #xx:3 <EAd>
Invert
Available Registers R7L, ERd:
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
Register direct
BIST
#xx:3,
Register indirect
BIST
#xx:3, @ERd
BIST (Bit Invert STore)
Absolute address
BIST
#xx:3, @aa:8
Absolute address
BIST
#xx:3, @aa:16
Absolute address
BIST
#xx:3, @aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
Rev. 3.0, 07/00, page
Store
2.2.13
BIXOR Exclusive Logical Condition Code
BIXOR (Bit Invert eXclusive Operation
(<bit No.> <EAd>)]
Assembly-Language Format BIXOR #xx:3, <EAd>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores result operation.
Operand Size Byte
Description This instruction exclusively inverse specified destination operand with carry flag stores result carry flag. number specified 3-bit immediate data. destination operand contents remain unchanged.
Specified #xx:3 <EAd> Invert
Available Registers R7L, ERd:
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
Register direct
BIXOR
#xx:3,
Register indirect
BIXOR
#xx:3, @ERd
Absolute address
BIXOR
#xx:3, @aa:8
Absolute address
BIXOR
#xx:3, @aa:16
BIXOR (Bit Invert eXclusive
Absolute address
BIXOR
#xx:3, @aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
Rev. 3.0, 07/00, page
Exclusive Logical
2.2.14
Load
(Bit LoaD) Operation (<Bit No.> <EAd>)
Condition Code
Assembly-Language Format #xx:3, <EAd>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Loaded from specified bit.
Operand Size Byte
Description This instruction loads specified from destination operand into carry flag. number specified 3-bit immediate data. destination operand contents remain unchanged.
Specified #xx:3 <EAd>
Available Registers R7L, ERd:
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
(Bit LoaD)
Register direct
#xx:3,
Register indirect
#xx:3, @ERd
Absolute address
#xx:3, @aa:8
Absolute address
#xx:3, @aa:16
Absolute address
#xx:3, @aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
Load
Rev. 3.0, 07/00, page
2.2.15
BNOT
BNOT (Bit NOT) Operation
(<bit No.> <EAd>) <EAd>)
(bit
Condition Code
Assembly-Language Format BNOT #xx:3, <EAd> BNOT <EAd>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size Byte
Description This instruction inverts specified destination operand. number specified 3bit immediate data lower bits 8-bit register specified tested. condition code remains unchanged.
Specified #xx:3 <EAd>
Invert
Available Registers R7L, ERd: R7L,
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
BNOT (Bit NOT)
Register direct
BNOT
#xx:3,
Register indirect
BNOT
#xx:3, @ERd
Absolute address
BNOT
#xx:3, @aa:8
Absolute address
BNOT
#xx:3, @aa:16
Absolute address
BNOT
#xx:3, @aa:32
Register direct
BNOT
Register indirect
BNOT
@ERd
Absolute address
BNOT
@aa:8
Absolute address
BNOT
@aa:16
Absolute address
BNOT
@aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
Rev. 3.0, 07/00, page
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
2.2.16
Logical Condition Code
(Bit inclusive Operation
(<bit No.> <EAd>)
Assembly-Language Format #xx:3, <EAd>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores result operation.
Operand Size Byte
Description This instruction specified destination operand with carry flag stores result carry flag. number specified 3-bit immediate data. destination operand contents remain unchanged.
Specified #xx:3 <EAd>
Available Registers R7L, ERd:
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
Register direct
#xx:3,
(Bit inclusive
Register indirect
#xx:3, @ERd
Absolute address
#xx:3, @aa:8
Absolute address
#xx:3, @aa:16
Absolute address
#xx:3, @aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
Rev. 3.0, 07/00, page
Logical
2.2.17
BSET Condition Code
BSET (Bit SET) Operation
(<bit No.> <EAd>)
Assembly-Language Format BSET #xx:3, <EAd> BSET <EAd>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size Byte
Description This instruction sets specified destination operand number specified 3-bit immediate data, lower three bits 8-bit register specified tested. condition code flags altered.
Specified #xx:3 <EAd>
Available Registers R7L, ERd: R7L,
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
BSET (Bit SET)
Register direct
BSET
#xx:3,
Register indirect
BSET
#xx:3, @ERd
Absolute address
BSET
#xx:3, @aa:8
Absolute address
BSET
#xx:3, @aa:16
Absolute address
BSET
#xx:3, @aa:32
Register direct
BSET
Register indirect
BSET
@ERd
Absolute address
BSET
@aa:8
Absolute address
BSET
@aa:16
Absolute address
BSET
@aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
Rev. 3.0, 07/00, page
2.2.18
Branch Subroutine Condition Code
(Branch SubRoutine) Operation @-SP disp
Assembly-Language Format disp
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size
Description This instruction branches subroutine specified address. pushes program counter (PC) value onto stack restart address, then adds specified displacement value branches resulting address. value pushed onto stack address instruction following instruction. displacement signed 8-bit 16-bit value, possible branching range -126 +128 bytes -32766 +32768 bytes from address instruction.
Operand Format Number States Required Execution
Addressing Mode Program-counter relative Mnemonic Operands d:16 Instruction Format byte byte byte byte disp disp States Normal Advanced
Rev. 3.0, 07/00, page
(Branch SubRoutine) Notes
Branch Subroutine
stack structure differs between normal mode advanced mode. normal mode only lower bits program counter pushed onto stack. Ensure that branch destination address even.
Reserved
Normal mode
Advanced mode
Rev. 3.0, 07/00, page
2.2.19
Store Condition Code
(Bit STore) Operation
(<bit No.> <EAd>)
Assembly-Language Format #xx:3, <EAd>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size Byte
Description This instruction stores carry flag specified location destination operand. number specified 3-bit immediate data.
Specified #xx:3 <EAd>
Available Registers R7L, ERd:
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
(Bit STore)
Register direct
#xx:3,
Register indirect
#xx:3, @ERd
Absolute address
#xx:3, @aa:8
Absolute address
#xx:3, @aa:16
Absolute address
#xx:3, @aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
Store
Rev. 3.0, 07/00, page
2.2.20
BTST Test
BTST (Bit TeST) Operation
(<Bit No.> <EAd>)
Condition Code
Assembly-Language Format BTST #xx:3, <EAd> BTST <EAd>
Operand Size Byte
Previous value remains unchanged. Previous value remains unchanged. specified zero; otherwise cleared Previous value remains unchanged. Previous value remains unchanged.
Description This instruction tests specified destination operand sets clears zero flag according result. number specified 3-bit immediate data, lower three bits 8-bit register destination operand contents remain unchanged.
Specified #xx:3 <EAd> Test
Available Registers R7L, ERd: R7L,
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
BTST (Bit TeST)
Register direct
BTST
#xx:3,
Register indirect
BTST
#xx:3, @ERd
Absolute address
BTST
#xx:3, @aa:8
Absolute address
BTST
#xx:3, @aa:16
Absolute address
BTST
#xx:3, @aa:32
Register direct
BTST
Register indirect
BTST
@ERd
Absolute address
BTST
@aa:8
Absolute address
BTST
@aa:16
Absolute address
BTST
@aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
Test
Rev. 3.0, 07/00, page
2.2.21
BXOR Exclusive Logical Condition Code
BXOR (Bit eXclusive Operation (<bit No.> <EAd>)
Assembly-Language Format BXOR #xx:3, <EAd>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores result operation.
Operand Size Byte
Description This instruction exclusively specified destination operand with carry flag stores result carry flag. number specified 3-bit immediate data. destination operand contents remain unchanged.
Specified #xx:3 <EAd>
Available Registers R7L, ERd:
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte byte byte byte byte byte byte byte States
Addressing Mnemonic Mode*
Operands
Register direct
BXOR
#xx:3,
Register indirect
BXOR
#xx:3, @ERd
BXOR (Bit eXclusive
Absolute address
BXOR
#xx:3, @aa:8
Absolute address
BXOR
#xx:3, @aa:16
Absolute address
BXOR
#xx:3, @aa:32
Note: addressing mode addressing mode destination operand <EAd>.
Notes
@aa:8/@aa:16 access range, refer relevant microcontroller hardware manual.
Exclusive Logical
Rev. 3.0, 07/00, page
2.2.22
CLRMAC Initialize Multiply-Accumulate Register Condition Code
CLRMAC (CLeaR register) Operation MACH, MACL
Assembly-Language Format CLRMAC
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size
Description This instruction simultaneously clears registers MACH MACL. supported only H8S/2600 CPU.
Operand Format Number States Required Execution
Addressing Mode Mnemonic CLRMAC Operands Instruction Format byte byte byte byte States
Note: maximum three additional states required execution this instruction within three states after execution instruction. example, there one-state instruction (such NOP) between instruction this instruction, this instruction will states longer.
Notes Execution this instruction also clears overflow flag multiplier
Rev. 3.0, 07/00, page
2.2.23
Compare Condition Code
(CoMPare) Operation (EAs), set/clear
Assembly-Language Format CMP.B <EAs>,
Operand Size Byte
there borrow otherwise cleared result negative; otherwise cleared result zero; otherwise cleared overflow occurs; otherwise cleared there borrow otherwise cleared
Description This instruction subtracts source operand from contents 8-bit register (destination operand) sets clears condition code bits according result. contents 8-bit register remain unchanged. Available Registers R7L, R7L,
Operand Format Number States Required Execution
Addressing Mode Immediate Register direct Mnemonic CMP.B CMP.B Operands #xx:8, Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.23
Compare Condition Code
(CoMPare) Operation (EAs), set/clear
Assembly-Language Format CMP.W <EAs>,
Operand Size Word
there borrow otherwise cleared result negative; otherwise cleared result zero; otherwise cleared overflow occurs; otherwise cleared there borrow otherwise cleared
Description This instruction subtracts source operand from contents 16-bit register (destination operand) sets clears condition code bits according result. contents 16bit register remain unchanged. Available Registers
Operand Format Number States Required Execution
Addressing Mode Immediate Register direct Mnemonic CMP.W CMP.W Operands #xx:16, Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.23
Compare Condition Code
(CoMPare) Operation (EAs), set/clear
Assembly-Language Format CMP.L <EAs>,
Operand Size Longword
there borrow otherwise cleared result negative; otherwise cleared result zero; otherwise cleared overflow occurs; otherwise cleared there borrow otherwise cleared
Description This instruction subtracts source operand from contents 32-bit register (destination operand) sets clears condition code bits according result. contents 32-bit register remain unchanged. Available Registers ERd: ERs:
Operand Format Number States Required Execution
Addressing Mode Immediate Register direct Instruction Format Mnemonic CMP.L CMP.L Operands byte #xx:32, ERs, byte byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.24
Decimal Adjust Condition Code
(Decimal Adjust Add) Operation (decimal adjust)
Assembly-Language Format
Operand Size Byte
Undetermined guaranteed value). adjusted result negative; otherwise cleared adjusted result zero; otherwise cleared Undetermined guaranteed value). there carry otherwise left unchanged.
Description Given that result addition operation performed ADD.B ADDX instruction 4-bit data contained 8-bit register carry half-carry flags, instruction adjusts contents 8-bit register (destination operand) adding H'00, H'06, H'60, H'66 according table below.
Flag before Adjustment Upper Bits before Adjustment Flag before Adjustment Lower Bits Value before Added Adjustment (Hexadecimal) Flag after Adjustment
Rev. 3.0, 07/00, page
(Decimal Adjust Add) Available Registers R7L,
Decimal Adjust
Operand Format Number States Required Execution
Addressing Mode Register direct Mnemonic Operands Instruction Format byte byte byte byte States
Notes Valid results (8-bit register contents flags) assured this instruction executed under conditions other than those described above.
Rev. 3.0, 07/00, page
2.2.25
Decimal Adjust Condition Code
(Decimal Adjust Subtract) Operation (decimal adjust)
Assembly-Language Format
Operand Size Byte
Undetermined guaranteed value). adjusted result negative; otherwise cleared adjusted result zero; otherwise cleared Undetermined guaranteed value). Previous value remains unchanged.
Description Given that result subtraction operation performed SUB.B, SUBX.B, NEG.B instruction 4-bit data contained 8-bit register carry half-carry flags, instruction adjusts contents 8-bit register (destination operand) adding H'00, H'FA, H'A0, H'9A according table below.
Flag before Adjustment Upper Bits before Adjustment Flag before Adjustment Lower Bits Value before Added Adjustment (Hexadecimal) Flag after Adjustment
Available Registers R7L,
Rev. 3.0, 07/00, page
(Decimal Adjust Subtract) Operand Format Number States Required Execution
Addressing Mode Register direct Mnemonic Operands Instruction Format byte byte byte
Decimal Adjust
byte
States
Notes Valid results (8-bit register contents flags) assured this instruction executed under conditions other than those described above.
Rev. 3.0, 07/00, page
2.2.26
Decrement Condition Code
(DECrement) Operation
Assembly-Language Format DEC.B
Operand Size Byte
Previous value remains unchanged. result negative; otherwise cleared result zero; otherwise cleared overflow occurs; otherwise cleared Previous value remains unchanged.
Description This instruction decrements 8-bit register (destination operand) stores result 8-bit register
Available Registers R7L,
Operand Format Number States Required Execution
Addressing Mode Register direct Mnemonic DEC.B Operands Instruction Format byte byte byte byte States
Notes
overflow caused operation H'80 H'7F.
Rev. 3.0, 07/00, page
2.2.26
Decrement Condition Code
(DECrement) Operation Assembly-Language Format DEC.W DEC.W
Operand Size Word
Previous value remains unchanged. result negative; otherwise cleared result zero; otherwise cleared overflow occurs; otherwise cleared Previous value remains unchanged.
Description This instruction subtracts immediate value from contents 16-bit register (destination operand) stores result 16-bit register
Available Registers
Operand Format Number States Required Execution
Addressing Mode Register direct Register direct Mnemonic DEC.W DEC.W Operands Instruction Format byte byte byte byte States
overflow caused operations H'8000 H'7FFF, H'8000 H'7FFE, H'8001 H'7FFF.
Notes
Rev. 3.0, 07/00, page
2.2.26
Decrement Condition Code
(DECrement) Assembly-Language Format DEC.L DEC.L Operation
Operand Size Longword
Previous value remains unchanged. result negative; otherwise cleared result zero; otherwise cleared overflow occurs; otherwise cleared Previous value remains unchanged.
Description This instruction subtracts immediate value from contents 32-bit register (destination operand) stores result 32-bit register ERd.
Available Registers ERd:
Operand Format Number States Required Execution
Addressing Mode Register direct Register direct Mnemonic DEC.L DEC.L Operands Instruction Format byte byte byte byte States
Notes
overflow caused operations H'80000000 H'7FFFFFFF, H'80000000 H'7FFFFFFE, H'80000001 H'7FFFFFFF.
Rev. 3.0, 07/00, page
2.2.27
DIVXS Divide Signed Condition Code
DIVXS (DIVide eXtend Signed) Operation
Assembly-Language Format DIVXS.B
Operand Size Byte
Previous value remains unchanged. quotient negative; otherwise cleared divisor zero; otherwise cleared Previous value remains unchanged. Previous value remains unchanged.
Description This instruction divides contents 16-bit register (destination operand) contents 8-bit register (source operand) stores result 16-bit register division signed. operation performed bits bits 8-bit quotient 8-bit remainder. quotient placed lower bits remainder placed upper bits sign remainder matches sign dividend.
Dividend bits
Divisor bits
Remainder bits
Quotient bits
Valid results assured division zero attempted overflow occurs.
Available Registers R7L,
Rev. 3.0, 07/00, page
DIVXS (DIVide eXtend Signed) Operand Format Number States Required Execution
Addressing Mode Register direct Mnemonic DIVXS.B Operands Instruction Format byte byte byte
Divide Signed
byte
States
Notes flag dividend divisor have different signs, cleared they have same sign. flag therefore when quotient zero.
Rev. 3.0, 07/00, page
2.2.27
DIVXS Divide Signed Condition Code
DIVXS (DIVide eXtend Signed) Operation
Assembly-Language Format DIVXS.W
Operand Size Word
Previous value remains unchanged. quotient negative; otherwise cleared divisor zero; otherwise cleared Previous value remains unchanged. Previous value remains unchanged.
Description This instruction divides contents 32-bit register (destination operand) contents 16-bit register (source operand) stores result 32-bit register ERd. division signed. operation performed bits bits 16-bit quotient 16-bit remainder. quotient placed lower bits (Rd) 32-bit register ERd. remainder placed upper bits (Ed). sign remainder matches sign dividend.
Dividend bits
Divisor bits
Remainder bits
Quotient bits
Valid results assured division zero attempted overflow occurs.
Available Registers ERd:
Rev. 3.0, 07/00, page
DIVXS (DIVide eXtend Signed) Operand Format Number States Required Execution
Addressing Mode Register direct Mnemonic DIVXS.W Operands Instruction Format byte byte byte
Divide Signed
byte
States
Notes flag dividend divisor have different signs, cleared they have same sign. flag therefore when quotient zero.
Rev. 3.0, 07/00, page
2.2.28
DIVXU Divide Condition Code
DIVXU (DIVide eXtend Unsigned) Operation
Assembly-Language Format DIVXU.B
Operand Size Byte
Previous value remains unchanged. divisor negative; otherwise cleared divisor zero; otherwise cleared Previous value remains unchanged. Previous value remains unchanged.
Description This instruction divides contents 16-bit register (destination operand) contents 8-bit register (source operand) stores result 16-bit register division unsigned. operation performed bits bits 8-bit quotient 8-bit remainder. quotient placed lower bits remainder placed upper bits
Dividend bits
Divisor bits
Remainder bits
Quotient bits
Valid results assured division zero attempted overflow occurs.
Available Registers R7L,
Rev. 3.0, 07/00, page
DIVXU (DIVide eXtend Unsigned) Operand Format Number States Required Execution
Addressing Mode Register direct Mnemonic DIVXU.B Operands Instruction Format byte byte byte byte
Divide
States
Notes
Rev. 3.0, 07/00, page
2.2.28
DIVXU Divide Condition Code
DIVXU (DIVide eXtend Unsigned) Operation
Assembly-Language Format DIVXU.W
Operand Size Word
Previous value remains unchanged. divisor negative; otherwise cleared divisor zero; otherwise cleared Previous value remains unchanged. Previous value remains unchanged.
Description This instruction divides contents 32-bit register (destination operand) contents 16-bit register (source register) stores result 32-bit register ERd. division unsigned. operation performed bits bits 16-bit quotient 16-bit remainder. quotient placed lower bits (Rd) 32-bit register ERd. remainder placed upper bits (Ed).
Dividend bits
Divisor bits
Remainder bits
Quotient bits
Valid results assured division zero attempted overflow occurs.
Available Registers ERd:
Rev. 3.0, 07/00, page
DIVXU (DIVide eXtend Unsigned) Operand Format Number States Required Execution
Addressing Mode Register direct Mnemonic DIVXU.W Operands Instruction Format byte byte byte byte
Divide
States
Notes
Rev. 3.0, 07/00, page
2.2.29
EEPMOV Block Data Transfer Condition Code
EEPMOV (MOVe data EEPROM) Operation then repeat @ER5+ @ER6+ until else next; Assembly-Language Format EEPMOV.B
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size
Description This instruction performs block data transfer. moves data from memory location specified memory location specified ER6, increments ER6, decrements R4L, repeats these operations until reaches zero. Execution then proceeds next instruction. data transfer performed byte time, with indicating number bytes transferred. byte symbol assembly-language format designates size (and limits maximum number bytes that transferred 255). interrupts detected while block transfer progress. When EEPMOV.B instruction ends, contains (zero), contain last transfer address Operand Format Number States Required Execution
Addressing Mode Mnemonic EEPMOV.B Operands Instruction Format byte byte byte byte States
Note: initial value R4L. Although bytes data transferred, data accesses performed, requiring states. 255).
Notes This instruction first reads memory locations indicated ER6, then carries block data transfer.
Rev. 3.0, 07/00, page
2.2.29
EEPMOV Block Data Transfer Condition Code
EEPMOV (MOVe data EEPROM) Operation then repeat @ER5+ @ER6+ until else next; Assembly-Language Format EEPMOV.W
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size
Description This instruction performs block data transfer. moves data from memory location specified memory location specified ER6, increments ER6, decrements repeats these operations until reaches zero. Execution then proceeds next instruction. data transfer performed byte time, with indicating number bytes transferred. word symbol assembly-language format designates size (allowing maximum 65535 bytes transferred). interrupts detected while block transfer progress. interrupt occurs while EEPMOV.W instruction executing, when EEPMOV.W instruction ends, contains (zero), contain last transfer address interrupt occurs, interrupt exception handling begins after current byte been transferred. indicates number bytes remaining transferred. indicate next transfer addresses. program counter value pushed onto stack interrupt exception handling address next instruction after EEPMOV.W instruction. note EEPMOV.W instruction interrupt.
Rev. 3.0, 07/00, page
EEPMOV (MOVe data EEPROM) Operand Format Number States Required Execution
Addressing Mode Mnemonic EEPMOV.W Operands Instruction Format byte byte byte
Block Data Transfer
byte
States
Note: initial value Although bytes data transferred, data accesses performed, requiring states. 65535).
Notes This instruction first reads memory addresses indicated ER6, then carries block data transfer. EEPMOV.W Instruction Interrupt interrupt request occurs while EEPMOV.W instruction being executed, interrupt exception handling carried after current byte been transferred. Register contents then follows: ER5: address next byte transferred ER6: destination address next byte number bytes remaining transferred program counter value pushed stack interrupt exception handling address next instruction after EEPMOV.W instruction. Programs should coded follows allow interrupts during execution EEPMOV.W instruction. Example:
EEPMOV.W MOV.W R4,R4
Interrupt requests other than accepted they masked CPU. During execution EEPMOV.B instruction interrupts accepted, including NMI.
Rev. 3.0, 07/00, page
2.2.30
EXTS Sign Extension Condition Code
EXTS (EXTend Signed) Operation (<Bit (<bits
Assembly-Language Format EXTS.W
Operand Size Word
Previous value remains unchanged. result negative; otherwise cleared result zero; otherwise cleared Always cleared Previous value remains unchanged.
Description This instruction copies sign lower bits 16-bit register upward direction (copies bits extend data signed word data.
Don't care bits bits Sign Sign extension bits bits
Available Registers
Operand Format Number States Required Execution
Addressing Mode Register direct Mnemonic EXTS.W Operands Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.30
EXTS Sign Extension Condition Code
EXTS (EXTend Signed) Operation (<Bit ERd) (<bits ERd)
Assembly-Language Format EXTS.L
Operand Size Longword
Previous value remains unchanged. result negative; otherwise cleared result zero; otherwise cleared Always cleared Previous value remains unchanged.
Description This instruction copies sign lower bits 32-bit register upward direction (copies bits extend data signed longword data.
Don't care bits bits Sign
Sign extension bits bits
Available Registers ERd:
Operand Format Number States Required Execution
Addressing Mode Register direct Mnemonic EXTS.L Operands Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.31
EXTU Zero Extension Condition Code
EXTU (EXTend Unsigned) Operation (<bits
Assembly-Language Format EXTU.W
Operand Size Word
Previous value remains unchanged. Always cleared result zero; otherwise cleared Always cleared Previous value remains unchanged.
Description This instruction extends lower bits 16-bit register word data padding with zeros. That clears upper bits (bits
Don't care bits bits Zero extension bits bits
Available Registers
Operand Format Number States Required Execution
Addressing Mode Register direct Mnemonic EXTU.W Operands Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.31
EXTU Zero Extension Condition Code
EXTU (EXTend Unsigned) Operation (<bits ERd)
Assembly-Language Format EXTU.L
Operand Size Longword
Previous value remains unchanged. Always cleared result zero; otherwise cleared Always cleared Previous value remains unchanged.
Description This instruction extends lower bits (general register 32-bit register longword data padding with zeros. That clears upper bits (bits
Don't care bits bits
Zero extension bits bits
Available Registers ERd:
Operand Format Number States Required Execution
Addressing Mode Register direct Mnemonic EXTU.L Operands Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.32
Increment Condition Code
(INCrement) Operation
Assembly-Language Format INC.B
Operand Size Byte
Previous value remains unchanged. result negative; otherwise cleared result zero; otherwise cleared overflow occurs; otherwise cleared Previous value remains unchanged.
Description This instruction increments 8-bit register (destination operand) stores result 8-bit register
Available Registers R7L,
Operand Format Number States Required Execution
Addressing Mode Register direct Mnemonic INC.B Operands Instruction Format byte byte byte byte States
Notes
overflow caused operation H'7F H'80.
Rev. 3.0, 07/00, page
2.2.32
Increment Condition Code
(INCrement) Operation Assembly-Language Format INC.W INC.W
Operand Size Word
Previous value remains unchanged. result negative; otherwise cleared result zero; otherwise cleared overflow occurs; otherwise cleared Previous value remains unchanged.
Description This instruction adds immediate value contents 16-bit register (destination operand) stores result 16-bit register
Available Registers
Operand Format Number States Required Execution
Addressing Mode Register direct Register direct Mnemonic INC.W INC.W Operands Instruction Format byte byte byte byte States
overflow caused operations H'7FFF H'8000, H'7FFF H'8001, H'7FFE H'8000.
Notes
Rev. 3.0, 07/00, page
2.2.32
Increment Condition Code
(INCrement) Operation Assembly-Language Format INC.L INC.L
Operand Size Longword
Previous value remains unchanged. result negative; otherwise cleared result zero; otherwise cleared overflow occurs; otherwise cleared Previous value remains unchanged.
Description This instruction adds immediate value contents 32-bit register (destination operand) stores result 32-bit register ERd.
Available Registers ERd:
Operand Format Number States Required Execution
Addressing Mode Register direct Register direct Mnemonic INC.L INC.L Operands Instruction Format byte byte byte byte States
Notes
overflow caused operations H'7FFFFFFF H'80000000, H'7FFFFFFF H'80000001, H'7FFFFFFE H'80000000.
Rev. 3.0, 07/00, page
2.2.33
Unconditional Branch Condition Code
(JuMP) Operation Effective address
Assembly-Language Format <EA>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size
Description This instruction branches unconditionally specified effective address.
Available Registers ERn:
Operand Format Number States Required Execution
Addressing Mode Register indirect Absolute address Memory indirect Instruction Format Mnemonic Operands byte @ERn @aa:24 @@aa:8 byte byte byte Normal Advanced States
Notes structure branch address number states required execution differ between normal mode advanced mode. Ensure that branch destination address even.
Rev. 3.0, 07/00, page
2.2.34
Jump Subroutine Condition Code
(Jump SubRoutine) Operation @-SP Effective address Assembly-Language Format <EA>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size
Description This instruction pushes program counter onto stack return address, then branches specified effective address. program counter value pushed onto stack address instruction following instruction.
Available Registers ERn:
Operand Format Number States Required Execution
Addressing Mode Register indirect Absolute address Memory indirect Instruction Format Mnemonic Operands byte @ERn @aa:24 @@aa:8 byte byte byte Normal Advanced States
Rev. 3.0, 07/00, page
(Jump SubRoutine) Notes
Jump Subroutine
stack structure differs between normal mode advanced mode. normal mode only lower bits program counter pushed onto stack. Ensure that branch destination address even.
Reserved
Normal mode
Advanced mode
Rev. 3.0, 07/00, page
2.2.35
Load Condition Code
(LoaD Control register) Operation <EAs>
Assembly-Language Format LDC.B <EAs>,
Operand Size Byte
Loaded from corresponding source operand. Loaded from corresponding source operand. Loaded from corresponding source operand. Loaded from corresponding source operand. Loaded from corresponding source operand. Loaded from corresponding source operand.
Description This instruction loads source operand contents into condition-code register (CCR). interrupt requests, including NMI, accepted immediately after execution this instruction.
Available Registers R7L,
Operand Format Number States Required Execution
Addressing Mode Immediate Register direct Mnemonic LDC.B LDC.B Operands #xx:8, Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.35
Load Condition Code
(LoaD Control register) Operation <EAs>
Assembly-Language Format LDC.B <EAs>,
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size Byte
Description This instruction loads source operand contents into extended control register (EXR). interrupt requests, including NMI, accepted three states after execution this instruction. Available Registers R7L,
Operand Format Number States Required Execution
Addressing Mode Immediate Register direct Mnemonic LDC.B LDC.B Operands #xx:8, Instruction Format byte byte byte byte States
Notes
Rev. 3.0, 07/00, page
2.2.35
Load Condition Code
(LoaD Control register) Operation (EAs)
Assembly-Language Format LDC.W <EAs>,
Operand Size Word
Loaded from corresponding source operand. Loaded from corresponding source operand. Loaded from corresponding source operand. Loaded from corresponding source operand. Loaded from corresponding source operand. Loaded from corresponding source operand.
Description This instruction loads source operand contents into condition-code register (CCR). Although byte register, source operand word size. contents even address loaded into CCR. interrupt requests, including NMI, accepted immediately after execution this instruction.
Available Registers ERs:
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte disp disp byte byte byte byte byte byte byte 10th byte States
Addressing Mnemonic Mode
Operands
byte
Register indirect
LDC.W
@ERs,
LDC.W
@(d:16, ERs),
Register indirect with displacement
LDC.W
@(d:32, ERs),
(LoaD Control register)
Register indirect with postincrement
LDC.W
@ERs+,
LDC.W
@aa:16,
Absolute address
LDC.W
@aa:32,
Notes
Load
Rev. 3.0, 07/00, page
2.2.35
Load Condition Code
(LoaD Control register) Operation (EAs)
Assembly-Language Format LDC.W <EAs>,
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size Word
Description This instruction loads source operand contents into extended control register (EXR). Although byte register, source operand word size. contents even address loaded into EXR. interrupt requests, including NMI, accepted three states after execution this instruction.
Available Registers ERs:
Rev. 3.0, 07/00, page
Operand Format Number States Required Execution
Instruction Format byte disp disp byte byte byte byte byte byte byte 10th byte States
Addressing Mnemonic Mode
Operands
byte
Register indirect
LDC.W
@ERs,
LDC.W
@(d:16, ERs),
Register indirect with displacement
LDC.W
@(d:32, ERs),
(LoaD Control register)
Register indirect with postincrement
LDC.W
@ERs+,
LDC.W
@aa:16,
Absolute address
LDC.W
@aa:32,
Notes
Rev. 3.0, 07/00, page
Load
2.2.36
Restore Data from Stack Condition Code
(LoaD Multiple registers) Operation @SP+ (register list)
Assembly-Language Format LDM.L @SP+, <register list>
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size Longword
Description This instruction restores data saved stack specified list registers. Registers restored descending order register number. Two, three, four registers restored instruction. following ranges specified register list. registers: ER0-ER1, ER2-ER3, ER4-ER5, ER6-ER7 Three registers: ER0-ER2 ER4-ER6 Four registers: ER0-ER3 ER4-ER7
Available Registers ERn:
Rev. 3.0, 07/00, page
(LoaD Multiple registers) Operand Format Number States Required Execution
Addressing Mnemonic Mode LDM.L LDM.L LDM.L Instruction Format Operands byte @SP+, (ERn-ERn+1) @SP+, (ERn-ERn+2) @SP+, (ERn-ERn+3) byte
Restore Data from Stack
byte
byte ern+1 ern+2 ern+3
States
Notes
Rev. 3.0, 07/00, page
2.2.37
LDMAC Load Register Condition Code
LDMAC (LoaD register) Operation MACH MACL Assembly-Language Format LDMAC ERs, register
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size Longword
Description This instruction moves contents general register multiply-accumulate register (MACH MACL). transfer MACH, only lowest bits general register transferred. Supported only H8S/2600 CPU. Available Registers ERs: Operand Format Number States Required Execution
Addressing Mode Register direct Register direct Mnemonic LDMAC LDMAC Operands ERs, MACH ERs, MACL Instruction Format byte byte byte byte States
Note: maximum three additional states required execution this instruction within three states after execution instruction. example, there one-state instruction (such NOP) between instruction this instruction, this instruction will states longer.
Notes Execution this instruction clears overflow flag multiplier
Rev. 3.0, 07/00, page
2.2.38
Multiply Accumulate Condition Code
(Multiply ACcumulate) Operation (EAn) (EAm) register register Assembly-Language Format @ERn+, @ERm+
Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
Operand Size
Description This instruction performs signed multiplication 16-bit operands addresses given contents general registers ERm, adds 32-bit product contents register, stores register. After this operation, both incremented operation carried saturating non-saturating mode, depending MACS system control register. (SYSCR) relevant hardware manual further information. non-saturating mode, MACH MACL concatenated store 42-bit result. value copied into upper bits MACH sign extension. saturating mode, only MACL valid, result limited range from H'80000000 (minimum value) H'7FFFFFFF (maximum value). result overflows negative direction, H'80000000 (the minimum value) stored MACL. result overflows positive direction, H'7FFFFFFF (the maximum value) stored MACL. MACH register indicates status overflow flag (V-MULT) multiplier. Other bits retain their previous contents. This instruction supported only H8S/2600 CPU.
Rev. 3.0, 07/00, page
(Multiply ACcumulate) Operand Format Number States Required Execution
Addressing Mode Register indirect with post-increment Instruction Format Mnemonic Operands byte @ERn+, @ERm+ byte
Multiply Accumulate
byte
byte
States
Notes Flags indicating result instruction condition-code register (CCR) STMAC instruction. same register, execution addresses After execution, value MACS modified during execution instruction, result cannot guaranteed. essential wait least three states after instruction before modifying MACS.
Further Explanation Instructions Using Multiplier Modification flags multiplier N-MULT, Z-MULT, V-MULT flags that indicate results instructions. These flags separated from condition-code register (CCR). values these flags flags only STMAC instruction. N-MULT Z-MULT modified only instructions. V-MULT retains value indicating whether overflow occurred past, until cleared execution CLRMAC LDMAC instruction. setting clearing conditions these flags given below. N-MULT (negative flag)
Saturating mode when register MACL execution instruction Cleared when register MACL cleared execution instruction Non-saturating mode when register MACH execution instruction Cleared when register MACH cleared execution instruction
Rev. 3.0, 07/00, page
(Multiply ACcumulate) Z-MULT (zero flag)
Saturating mode
Multiply Accumulate
when register MACL cleared
Other recent searches
TLYE50C - TLYE50C TLYE50C Datasheet
RKV502KJ - RKV502KJ RKV502KJ Datasheet
REJ03D0341 - REJ03D0341 REJ03D0341 Datasheet
0300Z - 0300Z 0300Z Datasheet
M85049 - M85049 M85049 Datasheet
LTC1628-SYNC - LTC1628-SYNC LTC1628-SYNC Datasheet
HPFC-6400 - HPFC-6400 HPFC-6400 Datasheet
6440 - 6440 6440 Datasheet
HPFC-64xx - HPFC-64xx HPFC-64xx Datasheet
EP3CLS150 - EP3CLS150 EP3CLS150 Datasheet
DQ2L1 - DQ2L1 DQ2L1 Datasheet
DQ2L2 - DQ2L2 DQ2L2 Datasheet
DQ2L3 - DQ2L3 DQ2L3 Datasheet
DQ2L4 - DQ2L4 DQ2L4 Datasheet
DQ2L5 - DQ2L5 DQ2L5 Datasheet
DQ2L6 - DQ2L6 DQ2L6 Datasheet
DQ2L7 - DQ2L7 DQ2L7 Datasheet
DQ1L6 - DQ1L6 DQ1L6 Datasheet
DQ1L7 - DQ1L7 DQ1L7 Datasheet
DQ1L3 - DQ1L3 DQ1L3 Datasheet
DQ1L4 - DQ1L4 DQ1L4 Datasheet
DQ1L5 - DQ1L5 DQ1L5 Datasheet
DQ1L1 - DQ1L1 DQ1L1 Datasheet
DQ1L2 - DQ1L2 DQ1L2 Datasheet
CLV2300A-LF - CLV2300A-LF CLV2300A-LF Datasheet
CAS-10203 - CAS-10203 CAS-10203 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
