128K (16,384 256K (32,768 Description AT25128/256 provides 1

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128K (16,384 256K (32,768 Description AT25128/256 provides 1

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Serial EEPROMs
128K (16,384 256K (32,768
Description
AT25128/256 provides 131,072/262,144 bits serial electrically-erasable programmable read only memory (EEPROM) organized 16,384/32,768 words bits each. device optimized many industrial commercial applications where low-power low-voltage operation essential. devices available space saving 8-lead PDIP (AT25128/256), 8-lead EIAJ SOIC (AT25128/256), 8-lead
AT25128 AT25256
(continued)
Configurations
Name HOLD Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input Connect Don't Connect
14-lead TSSOP
HOLD
20-lead TSSOP*
HOLD HOLD
8-ball dBGA
HOLD
8-lead Leadless Array
HOLD
16-lead SOIC
HOLD
Bottom View 8-lead PDIP
HOLD
Bottom View 8-lead SOIC
HOLD
*Note: Pins internally connected 14-lead TSSOP socket compatibility.
Rev. 0872J-SEEPR-09/02
16-lead JEDEC SOIC (AT25128), 14-lead TSSOP (AT25128), 20-lead TSSOP (AT25128/256), 8-lead Leadless Array (AT25256), 8-ball dBGA packages. addition, entire family available 2.7V (2.7V 5.5V) 1.8V (1.8V 5.5V) versions. AT25128/256 enabled through Chip Select (CS) accessed 3-wire interface consisting Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK). programming cycles completely self-timed, separate ERASE cycle required before WRITE. BLOCK WRITE protection enabled programming status register with entire array write protection. Separate program enable program disable instructions provided additional data protection. Hardware data protection provided protect against inadvertent write attempts status register. HOLD used suspend serial communication without resetting serial sequence.
Absolute Maximum Ratings*
Operating Temperature. -55°C +125°C Storage Temperature -65°C +150°C Voltage with Respect Ground .-1.0V +7.0V Maximum Operating Voltage 6.25V Output Current. *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Block Diagram
16384/32768
AT25128/256
0872J-SEEPR-09/02
AT25128/256
Capacitance(1)
Applicable over recommended operating range from 25°C, MHz, +5.0V (unless otherwise noted).
Symbol COUT Note: Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, HOLD) This parameter characterized 100% tested. Units Conditions VOUT
Characteristics
Applicable over recommended operating range from -40°C +85°C, +1.8V +5.5V, +70°C, +1.8V +5.5V(unless otherwise noted).
Symbol VCC1 VCC2 VCC3 ICC1 ICC2 ISB1 ISB2 ISB3
Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low-voltage Input High-voltage Output Low-voltage Output High-voltage Output Low-voltage Output High-voltage
Test Condition
Units
5.0V MHz, Open, Read 5.0V MHz, Open, Read, Write 1.8V, 2.7V, 5.0V, VCC, 70°C -3.0 -3.0 -1.0 5.5V 1.8V 3.6V -1.6 0.15 -100
VOL1 VOH1 VOL2 VOH2 Note:
reference only tested.
0872J-SEEPR-09/02
Characteristics
Applicable over recommended operating range from -40°C 85°C, Specified, Gate (unless otherwise noted).
Symbol fSCK Parameter Clock Frequency Voltage 1000 1000 1000 Units
Input Rise Time
Input Fall Time
High Time
Time
High Time
tCSS
Setup Time
tCSH
Hold Time
Data Setup Time
Data Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
Output Hold Time
Hold Output
AT25128/256
0872J-SEEPR-09/02
AT25128/256
Characteristics (Continued)
Applicable over recommended operating range from -40°C 85°C, Specified, Gate (unless otherwise noted).
Symbol Parameter Hold Output High Voltage 100K 1000 Units
tDIS
Output Disable Time
Endurance(1) Note:
Write Cycle Time 5.0V, 25°C, Page Mode
Write Cycles
This parameter characterized 100% tested. Contact Atmel further information.
Serial Interface Description
MASTER:
device that generates serial clock.
SLAVE: Because Serial Clock (SCK) always input, AT25128/256 always operates slave. TRANSMITTER/RECEIVER: AT25128/256 seperate pins designated data transmission (SO) reception (SI). MSB: Most Significant (MSB) first transmitted received.
SERIAL OP-CODE: After device selected with going low, first byte will received. This byte contains op-code that defines operations performed. INVALID OP-CODE: invalid op-code received, data will shifted into AT25128/256, serial output (SO) will remain high impedance state until falling edge detected again. This will reinitialize serial communication. CHIP SELECT: AT25128/256 selected when low. When device selected, data will accepted pin, serial output (SO) will remain high impedance state. HOLD: HOLD used conjunction with select AT25128/256. When device selected serial sequence underway, HOLD used pause serial communication with master device without resetting serial sequence. pause, HOLD must brought while low. resume serial communication, HOLD brought high while (SCK still toggle during HOLD). Inputs will ignored while high impedance state. WRITE PROTECT: write protect (WP) will allow normal read/write operations when held high. When brought WPEN "1", write operations status register inhibited. going while still will interrupt write status register. internal write cycle already been initiated, going will have effect write operation status register. function blocked when WPEN status register "0". This will allow user install AT25128/256 system with tied ground still able write status register. functions enabled when WPEN "1".
0872J-SEEPR-09/02
Serial Interface
AT25128/256
Functional Description
AT25128/256 designed interface directly with synchronous serial peripheral interface (SPI) 6800 type series microcontrollers. AT25128/256 utilizes 8-bit instruction register. list instructions their operation codes contained Table instructions, addresses, data transferred with first start with high-to-low transition. Table Instruction AT25128/256
Instruction Name WREN WRDI RDSR WRSR READ WRITE Instruction Format 0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X010 Operation Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data Memory Array
AT25128/256
0872J-SEEPR-09/02
AT25128/256
WRITE ENABLE (WREN): device will power-up write disable state when applied. programming instructions must therefore preceded Write Enable instruction. WRITE DISABLE (WRDI): protect device against inadvertent writes, Write Disable instruction disables programming modes. WRDI instruction independent status pin. READ STATUS REGISTER (RDSR): Read Status Register instruction provides access status register. READY/BUSY Write Enable status device determined RDSR instruction. Similarly, Block Write Protection bits indicate extent protection employed. These bits using WRSR instruction. Table Status Register Format
WPEN
Table Read Status Register Definition
Definition
(RDY) (WEN) (BP0) (BP1)
(RDY) indicates device READY. indicates write cycle progress. indicates device WRITE ENABLED. indicates device WRITE ENABLED. Table Table
Bits when device internal write cycle. (WPEN) Table
Bits during internal write cycle.
WRITE STATUS REGISTER (WRSR): WRSR instruction allows user select four levels protection. AT25128/256 divided into four array segments. quarter (1/4), half (1/2), memory segments protected. data within selected segment will therefore READ only. block write protection levels corresponding status register control bits shown Table three bits, BP0, BP1, WPEN nonvolatile cells that have same properties functions regular memory cells (e.g. WREN, tWC, RDSR). Table Block Write Protect Bits
Status Register Bits Level 1(1/4) 2(1/2) 3(All) Array Addresses Protected AT25128 None 3000 3FFF 2000 3FFF 0000 3FFF AT25256 None 6000 7FFF 4000 7FFF 0000 7FFF
0872J-SEEPR-09/02
WRSR instruction also allows user enable disable write protect (WP) through Write Protect Enable (WPEN) bit. Hardware write protection enabled when WPEN "1". Hardware write protection disabled when either high WPEN "0." When device hardware write protected, writes Status Register, including Block Protect bits WPEN bit, block-protected sections memory array disabled. Writes only allowed sections memory which block-protected. NOTE: When WPEN hardware write protected, cannot changed back "0", long held low. Table WPEN Operation
WPEN High High Protected Blocks Protected Protected Protected Protected Protected Protected Unprotected Blocks Protected Writable Protected Writable Protected Writable Status Register Protected Writable Protected Protected Protected Writable
READ SEQUENCE (READ): Reading AT25128/256 (Serial Output) requires following sequence. After line pulled select device, READ op-code transmitted line followed byte address read (Refer Table Upon completion, data line will ignored. data specified address then shifted onto line. only byte read, line should driven high after data comes out. READ sequence continued since byte address automatically incremented data will continue shifted out. When highest address reached, address counter will roll over lowest address allowing entire memory read continuous READ cycle. WRITE SEQUENCE (WRITE): order program AT25128/256, separate instructions must executed. First, device must write enabled Write Enable (WREN) Instruction. Then Write (WRITE) Instruction executed. Also, address memory location(s) programmed must outside protected address field location selected Block Write Protection Level. During internal write cycle, commands will ignored except RDSR instruction. Write Instruction requires following sequence. After line pulled select device, WRITE op-code transmitted line followed byte address data programmed (Refer Table Programming will start after brought high. (The LOW-to-High transition must occur during time immediately after clocking (LSB) data bit. READY/BUSY status device determined initiating READ STATUS REGISTER (RDSR) Instruction. WRITE cycle still progress. WRITE cycle ended. Only READ STATUS REGISTER instruction enabled during WRITE programming cycle.
AT25128/256
0872J-SEEPR-09/02
AT25128/256
AT25128/256 capable 64-byte PAGE WRITE operation. After each byte data received, order address bits internally incremented one; high order bits address will remain constant. more than bytes data transmitted, address counter will roll over previously written data will overwritten. AT25128/256 automatically returned write disable state completion WRITE cycle. NOTE: device Write enabled (WREN), device will ignore Write instruction will return standby state, when brought high. falling edge required re-initiate serial communication. Table Address
Address Don't Care Bits AT25128 AT25256
0872J-SEEPR-09/02
Timing Diagrams (for Mode
Synchronous Data Timing
HI-Z HI-Z VALID
WREN Timing
WRDI Timing
AT25128/256
0872J-SEEPR-09/02
AT25128/256
RDSR Timing
INSTRUCTION
HIGH IMPEDANCE
DATA
WRSR Timing
READ Timing
0872J-SEEPR-09/02
WRITE Timing
HOLD Timing
HOLD
AT25128/256
0872J-SEEPR-09/02
AT25128/256
AT25128 Ordering Information
Ordering Code AT25128-10PI-2.7 AT25128N-10SI-2.7 AT25128W-10SI-2.7 AT25128-10UI-2.7 AT25128N1-10SI-2.7 AT25128T1-10TI-2.7 AT25128-10PI-1.8 AT25128N-10SI-1.8 AT25128W-10SI-1.8 AT25128-10UI-1.8 AT25128N1-10SI-1.8 AT25128T1-10TI-1.8 Note: Package 16S1 14A2 16S1 14A2 Operation Range Industrial (-40°C 85°C)
Industrial (-40°C 85°C)
2.7V devices used 4.5V 5.5V range, please refer performance values Characteristics tables.
Package Type
16S1 14A2 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8-ball, Ball Grid Array Package (dBGA) 16-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
-2.7 -1.8 Low-voltage (2.7V 5.5V) Low-voltage (1.8V 5.5V)
0872J-SEEPR-09/02
AT25256 Ordering Information
Ordering Code AT25256-10PI-2.7 AT25256W-10SI-2.7 AT25256-10CI-2.7 AT25256-10UI-2.7 AT25256T2-10TI-2.7 AT25256-10PI-1.8 AT25256W-10SI-1.8 AT25256-10CI-1.8 AT25256-10UI-1.8 AT25256T2-10TI-1.8 Note: Package 8CN3 20A2 8CN3 20A2 Operation Range Industrial (-40°C 85°C)
Industrial (-40°C 85°C)
2.7V devices used 4.5V 5.5V range, please refer performance values Characteristics tables.
Package Type
8CN3 20A2 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8-lead, 0.230" Wide, Leadless Array Package (LAP) 8-ball, Ball Grid Array Package (dBGA) 20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
-2.7 -1.8 Low-voltage (2.7V 5.5V) Low-voltage (1.8V 5.5V)
AT25128/256
0872J-SEEPR-09/02
AT25128/256
Packaging Information
PDIP
View
View
SYMBOL
COMMON DIMENSIONS (Unit Measure inches) NOTE
0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 0.300 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
PLCS
0.325 0.280
Side View
0.150
Notes:
This drawing general information only; refer JEDEC Drawing MS-001, Variation additional information. Dimensions measured with package seated JEDEC seating plane Gauge GS-3. dimensions include mold Flash protrusions. Mold Flash protrusions shall exceed 0.010 inch. measured with leads constrained perpendicular datum. Pointed rounded lead tips preferred ease insertion. maximum dimensions include Dambar protrusions. Dambar protrusions shall exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway Jose, 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING REV.
0872J-SEEPR-09/02
JEDEC SOIC
View
Side View
SYMBOL
COMMON DIMENSIONS (Unit Measure 1.27 6.20 1.27 1.75 0.51 0.25 5.00 4.00 NOTE
View
Note: This drawing general information only. Refer JEDEC Drawing MS-012 proper dimensions, tolerances, datums, etc.
10/10/01 2325 Orchard Parkway Jose, 95131 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING REV.
AT25128/256
0872J-SEEPR-09/02
AT25128/256
EIAJ SOIC
View
Side View
SYMBOL
COMMON DIMENSIONS (Unit Measure NOTE
1.78 0.05 0.35 0.18 5.13 5.13 7.62 0.51 1.27
2.03 0.33 0.51 0.25 5.38 5.41 8.38 0.89
View
Notes:
This drawing general information only; refer EIAJ Drawing EDR-7320 additional information. Mismatch upper lower dies resin burrs aren't included. recommended that upper lower cavities equal. they different, larger dimension shall regarded. Determines true geometric position. Values apply pb/Sn solder plated terminal. standard thickness solder layer shall 0.010 +0.010/-0.005
5/2/02 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING REV.
2325 Orchard Parkway Jose, 95131
0872J-SEEPR-09/02
8CN3
Marked Pin1 Indentifier
View
0.10
Side View
Pin1 Corner
COMMON DIMENSIONS (Unit Measure SYMBOL 0.94 0.30 0.36 5.89 4.83 1.04 0.34 0.41 5.99 4.93 1.27 0.56 0.62 0.92 0.67 0.97 0.72 1.02 1.14 0.38 0.46 6.09 5.03 NOTE
Bottom View
Note: Metal Dimensions.
11/14/01 2325 Orchard Parkway Jose, 95131 TITLE 8CN3, 8-lead, 1.04 Body), Lead Pitch 1.27 Leadless Array Package (LAP) DRAWING 8CN3 REV.
AT25128/256
0872J-SEEPR-09/02
AT25128/256
dBGA
Mark this corner
View
COMMON DIMENSIONS (Unit Measure SYMBOL NOTE
3.86 0.81 2.95 1.10 0.75 0.75 0.90 0.49 0.35 0.47 0.52 0.38 0.50 0.55 0.41 0.53
Bottom View
Side View
Notes: This drawing general information only. JEDEC Drawing refer additional information. Dimension measured maximum solder ball diameter, parallel primary datum
01/09/02 2325 Orchard Parkway Jose, 95131 TITLE 8U3, 8-ball 0.75 pitch, Ball Grid Array Package (dBGA) AT25256 (AT19874) DRAWING REV.
0872J-SEEPR-09/02
dBGA
Mark this corner
View
COMMON DIMENSIONS (Unit Measure SYMBOL NOTE
3.73 0.74 2.21 0.73 0.75 0.75 0.90 0.49 0.35 0.47 0.52 0.38 0.50 0.55 0.41 0.53
Bottom View Side View
Notes: This drawing general information only. JEDEC Drawing refer additional information. Dimension measured maximum solder ball diameter, parallel primary datum
01/09/02 DRAWING REV.
TITLE
2325 Orchard Parkway Jose, 95131
8U4, 8-ball 0.75 pitch, Ball Grid Array Package (dBGA) AT25128 (AT19875)
AT25128/256
0872J-SEEPR-09/02
AT25128/256
16S1 JEDEC SOIC
View
COMMON DIMENSIONS (Unit Measure SYMBOL 1.35 0.33 0.19 9.80 3.80 1.27 5.80 0.40 6.20 1.27 1.75 0.51 0.25 10.00 4.00 NOTE
Side View
View
Notes: This drawing general information only; refer JEDEC Drawing MS-012 proper dimensions, tolerances, datums, etc. Dimension does include mold Flash, protrusions gate burrs. Mold Flash, protrusions gate burrs shall exceed 0.15 (0.006 side. Dimension does include inter-lead Flash protrusions. Inter-lead Flash protrusions shall exceed 0.25 (0.010 side. length terminal soldering substrate. lead width measured 0.36 (0.014 greater above seating plane, shall exceed maximum value 0.61 (0.024 in). 10/15/01
2325 Orchard Parkway Jose, 95131
TITLE 16S1, 16-lead, 0.150" Body, Plastic Gull Wing Small Outline (SOIC
DRAWING 16S1
REV.
0872J-SEEPR-09/02
14A2 TSSOP
View
COMMON DIMENSIONS (Unit Measure SYMBOL 4.90 5.00 6.40 4.30 4.40 4.50 1.20 0.80 0.19 0.65 0.45 0.60 1.00 0.75 1.00 1.05 0.30 5.10 NOTE
View
Side View
Notes:
This drawing general information only. Please refer JEDEC Drawing MO-153, Variation AB-1 additional information. Dimension does include mold Flash, protrusions gate burrs. Mold Flash, protrusions gate burrs shall exceed 0.15 (0.006 side. Dimension "E1" does include inter-lead Flash protrusions. Inter-lead Flash protrusions shall exceed 0.25 (0.010 side. Dimension does include Dambar protrusion. Allowable Dambar protrusion shall 0.08 total excess dimension maximum material condition. Dambar cannot located lower radius foot. Minimum space between protrusion adjacent lead 0.07 Dimension "E1" determined Datum Plane
12/28/01 REV.
2325 Orchard Parkway Jose, 95131
TITLE 14A2,14-lead (4.4 Body), 0.65 Pitch, Thin Shrink Small Outline Package (TSSOP)
DRAWING 14A2
AT25128/256
0872J-SEEPR-09/02
AT25128/256
20A2 TSSOP
View
COMMON DIMENSIONS (Unit Measure SYMBOL 6.40 6.50 6.40 4.30 0.80 0.19 4.40 1.00 0.65 0.45 0.60 1.00 0.75 4.50 1.20 1.05 0.30 6.60 NOTE
View
Side View
Notes:
This drawing general information only. Please refer JEDEC Drawing MO-153, Variation additional information. Dimension does include mold Flash, protrusions gate burrs. Mold Flash, protrusions gate burrs shall exceed 0.15 (0.006 side. Dimension does include inter-lead Flash protrusions. Inter-lead Flash protrusions shall exceed 0.25 (0.010 side. Dimension does include Dambar protrusion. Allowable Dambar protrusion shall 0.08 total excess dimension maximum material condition. Dambar cannot located lower radius foot. Minimum space between protrusion adjacent lead 0.07 Dimension determined Datum Plane
6/3/02 2325 Orchard Parkway Jose, 95131 TITLE 20A2, 20-lead (4.4 Body), 0.65 pitch, Thin Shrink Small Outline Package (TSSOP) DRAWING 20A2 REV.
0872J-SEEPR-09/02
Atmel Headquarters
Corporate Headquarters
2325 Orchard Parkway Jose, 95131 1(408) 441-0311 1(408) 487-2600
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Memory
2325 Orchard Parkway Jose, 95131 1(408) 441-0311 1(408) 436-4314
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Atmel Corporation 2002. Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life support devices systems. ATMEL registered trademark Atmel; dBGA trademark Atmel. Other terms product names trademarks others. Printed recycled paper.
0872J-SEEPR-09/02

128K (16,384 256K (32,768 Description AT25128/256 provides 1

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