BCC918 transceiver reference manual rev. BlueChip Communicat
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BlueChip Communication
BCC918 transceiver
reference manual rev.
BlueChip Communication Hovfaret 0275 Oslo Norway Phone: Fax: post@bluechip.no www.bluechip.no
BCC918 Transceiver
reference manual
Tables contents
Introduction description Programming Application circuit: modulation: Circuit blocks.8 section 5.1.1 Voltage controlled oscillator (VCO) 5.1.2 Crystal oscillator 5.1.2.1 Prestart 5.1.3 Lock detector.9 5.1.4 Charge pump 5.1.5 Tuning 5.1.5.1 tuning 5.1.5.2 tuning 5.1.6 modulation 5.1.7 Loop filter 5.1.7.1 Modulation inside PLL.10 5.1.7.2 Modulation outside (closed loop) 5.1.7.3 Modulation outside PLL, dual loop-filters 5.1.7.4 Modulation outside (open loop) Transmit section.11 5.2.1 Power amplifier (PA) 5.2.2 buffer.11 Receive section.12 5.3.1 Front-end (LNA mixers).12 5.3.2 Sallen-Key filter preamplifier 5.3.3 Gyrator-filter 5.3.4 Cut-off frequency setting.12 5.3.5 Limiter.13 5.3.6 Demodulator.13 5.3.7 Received Signal Strength Indicator (RSSI)
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BCC918 Transceiver
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Introduction
BCC918 single chip radio transmitter receiver intended 900MHz frequency band with data rates kbauds. transmitter consists frequency synthesizer power amplifier. frequency synthesizer consists voltage-controlled oscillator (VCO), crystal oscillator, dual modulus prescaler, programmable frequency dividers phase-detector. loop-filter external flexibility simple passive circuit. Colpitts oscillator needs external resonator varactor. modulation applied externally VCO. synthesizer different frequency dividers. modulation also implemented switching between these dividers (max. 2400bps). lengths registers bits respectively. types modulation, data entered DataIXO (see application circuit). output power power amplifier programmed levels. lock-detect circuit detects when lock. receive mode synthesizer generates local oscillator (LO) signal. values that give frequency stored registers. receiver zero intermediate frequency (IF) type order make channel filtering possible with low-power integrated low-pass filters. receiver consists noise amplifier (LNA) that drives quadrature mixer pair. mixer outputs feed identical signal channels phase quadrature. Each channel include pre-amplifier, third order Quick reference data
Parameter Frequency Modulation output power Sensitivity (19.2kbauds, BER=10-3) Maximum data rate Value 700-1000 -104 Package Type number BCC918 BCC918S Name TQFP44 TQFP48 Description plastic thin quad flat package plastic thin quad flat package1 Ratings +150 Unit
Sallen-Key lowpass filter that protects following gyrator filter from strong adjacent channel signals finally limiter. main channel filter gyrator-capacitor implementation seven-pole elliptic lowpass filter. elliptic filter minimizes total capacitance required given selectivity dynamic range. cut-off frequency Sallen-Key filter programmed four different frequencies: 10kHz, 30kHz, 60kHz 200kHz. external resistor adjusts cut-off frequency gyrator filter. demodulator demodulates channel outputs produces digital data output. detects relative phase channel signal. channel signal lags channel, tone frequency lies above frequency (data `1'). channel leads channel, tone lies below frequency (data `0'). output receiver available DataIXO pin. RSSI circuit (receive signal strength indicator) indicates received signal level. serial interface used program circuit. External components necessary input output impedance matching decoupling power. Other external components resonator varactor, crystal, feedback capacitors components modulation VCO, loop filter, bias resistors power amplifier gyrator filters. switch implemented with diodes. This gives maximum input sensitivity output power.
Unit kbauds
Ordering information:
Absolute Maximum ratings
Parameter Maximum supply voltage Maximum reverse base-emitter voltage Storage temperature range
large volumes only
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Vdd=2.5-3.4V, T=25°C, unless otherwise specified Parameter Conditions Overall Operating frequency Supply voltage Power down current Logic high input, Logic input, DataIXO, logic high output (Voh) Ioh=-500µA DataIXO, logic output (Vol) Iol= 500µA LockDet, logic high output (Voh) Ioh=-100µA LockDet, logic output (Vol) Iol= 100µA Clock/Data frequency Clock/Data duty-cycle Data setup clock (rising edge) Operating temperature range section Prescaler divide ratio Reference frequency lock time (int modulation) 4kHz loop filter bandwidth lock time (ext modulation) 1kHz loop filter bandwidth with switch time 1kHz loop filter bandwidth Charge pump current fOUT=850MHz Transmit section Output power RLOAD=100, Vdd=3.0V Transmit data rate (ext modulation) Transmit data rate (int modulation) Freq. deviation modulation rate ratio unfiltered Current consumption transmit mode dBm, RLOAD=100 fIN=850MHz Receive section Receiver sensitivity BER=10-3 Input compression level Input Input impedance RSSI dynamic range RSSI output voltage -100dBm -30dBm Adjacent channel rejection: fC=10kHz 25kHz channel spacing fC=30kHz 100kHz channel spacing fC=60kHz 200kHz channel spacing fC=200kHz 700kHz channel spacing Blocking immunity (1MHz) filter: fC=10kHz filter: fC=30kHz filter: fC=60kHz filter: fC=200kHz Maximum receiver bandwidth Receiver settling time Current consumption receive mode gyrator filter fC=60kHz Current consumption
Min.
Typ.
Max. 1000
Unit
Vdd-0.3 Vdd-0.25 0.25 64/65 ±125/±500 ±155/±620 19.2 -104 22.5-j28.5
±95/±380
kbauds kbauds
Modulation applied therefore modulation cannot have component. Some kind coding needed ensure that modulation free, e.g. Manchester code block code. With Manchester code bitrate half baudrate, with 3B4B block code bitrate baudrate. Bitrate same baudrate. Measured 19.2kbauds frequency deviation ±25kHz (external modulation), jitter received data: 45%).
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description
Prescaler 32/33
A1/A0
Control
A-counter N1/N0 filters Gyrator filters N-counter
M-counter M1/M0 Phase detector Charge pump
Demod
Figure Transceiver internal blocks
Symbol IFGnd IFVdd IchOut QchOut OscVdd OscIn OscGnd Ground CmpOut CmpR XoscIn XoscOut LD_C LockDet RSSI PuExt DataC DataIXO ClkIn RegIn DigVdd
Description ground power I-channel output Q-channel output Colpitts oscillator power Colpitts oscillator input Colpitts oscillator substrate ground substrate ground charge-pump output charge pump resistor input output modulation crystal oscillator input crystal oscillator output external capacitor lock detector lock detector output received signal strength indicator output power down input (0=power down) data filter capacitor data input/output clock input programming data input programming digital circuitry power
Symbol DigGnd PA_C PAbias RFout RFGnd RFVdd RFin RFGnd2 LNA_C MixGnd MixVdd MixIoutp MixIoutn IFIinp IFIinn MixQoutp MixQoutn IFQinp IFQinn IchC QchC vb_lp
Description digital circuitry ground capacitor slow ramp up/down external bias resistor power amplifier power amplifier output LNA, substrate ground power noise amplifier (LNA) input first stage ground external stabilizing capacitor mixer ground mixer power I-channel mixer positive output I-channel mixer negative output I-channel IF-amplifier positive input I-channel IF-amplifier negative input Q-channel mixer positive output Q-channel mixer negative output Q-channel IF-amplifier positive input Q-channel IF-amplifier negative input I-channel amplifier capacitor Q-channel amplifier capacitor Gyrator filter resistor
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Programming
two-line used program circuit; lines being ClkIn RegIn. 2-line serial interface allows control over frequency dividers selective powering Synthesizer circuit blocks. interface Table allocation
Ref2 OutS1 Ref1 OutS0 Ref0 Mod1 ByLNA Cpmp1 Mod0 Ref6 Cpmp0 Ref5 RxFilt Ref4 Ref3 OutS2
consists 80-bit programming register. Data entered RegIn line with most significant first. first entered called last p80. bits programming register arranged shown table
Table description
Name RxFilt Chapter Description frequency divider bits frequency divider bits frequency divider bits frequency divider bits frequency divider bits frequency divider bits 5.3.6 1=external capacitor filtering data signal 5.2.1 gain setting power amplifier pa2, pa1, lowest output power pa2, pa1, highest output power 5.2.2 gain control power amplifier buffer: 1=high gain 5.3.2 gain control preamplifier receiver: 1=high gain ByLNA 5.3.1 bypassed 5.1.3 Ref6 reference settings lock detector Ref5 Ref4 0's: highest reference Ref3 1's: lowest reference Ref2 Ref1 Ref0 Cpmp1 5.1.4 charge pump Cpmp1=0, Cpmp0=0 ±125uA setting: Cpmp0 Cpmp1=0, Cpmp0=1 ±500uA Cpmp1=1, Cpmp0=0 controlled LockDet (LD) LD=0: ±500uA, LD=1: ±125uA Cpmp1=1, Cpmp0=1 same previous current ±500µA. 5.3.2 Active RCFc1=0, Fc0=0 10kHz Fc1=1, Fc0=0 60kHz filter settings Fc1=0, Fc0=1 30kHz Fc1=1, Fc0=1 200kHz OutS2 OutS1 OutS0 IchOut QchOut OutS2 Q-channel OutS2 OutS1 OutS0 IchOut QchOut lim_qch gm_qch output select high high OutS1 gm_ich lim_ich sk_ich sk_qch OutS0 high Dual gm_ich gm_qch N_div M_div lim_ich lim_qch sk:_*:Sallen-Key-filter output, gm_*:gyrator-filter output, lim_*:limiter output, *_div:frequency divider output (for testing). dual loop-filter applications, section 5.1.7.3. Mod1 5.1.6 Mod1 Mod0 modulation applied Mod1 Mod0 modulation applied VCO: open loop modulation Mod0 Mod1 Mod0 modulation switching between sets dividers Mod1 Mod0 modulation adding/subtracting divider fdeviation fcomparison receive mode transmit mode power power down (When Pu=1, power down controlled PuExt)
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When modulation applied using dividers When Mod1 Mod0 possible switch between different dividers PLL. DataIXO controls switching. When DataIXO uses dividers When DataIXO uses dividers Switching between different dividers used implement modulation. values calculated from formula:
control word entered into first register. transition RegIn signal when ClkIn high will turn power amplifier off. When power amplifier turned internal load pulse generated. control word loaded into parallel register circuit enters mode this case power down mode). ClkIn must after internal load pulse generated. long transitions RegIn avoided when ClkIn high, control word clocked into first register time without affecting operation transceiver.
Example 869.0MHz, frequency deviation: ±10kHz, fXCO 10.00MHz. modulation implemented switching between dividers.
RxFilt Ref6 Ref0 OutS1 Ref5 Ref4 Cpmp1 Cpmp0 OutS0 Mod1 Ref3 Mod0 Ref2 ByLNA Ref1 OutS2
where comparison frequency. 80bit control word first read into shiftregister, then loaded into parallel register transition RegIn signal (positive negative) when ClkIn signal high. circuit then goes directly into specified mode (receive, transmit, etc.).
ClkIn RegIn Load_int PA_C LockDet
Binary form: (MSB left):
001001 011011 000010001001 000010000110 0001100101 0001100011 01011110000000001010001011 110010 110010 000010000111 000010000111 0001100100 0001100100 01011110000000001010001001
Figure Timing ClkIn, RegIn internal Load_int PA_C signals.
second last clocked into first shift register (`1'). last clocked into first shift register (`1'). transition RegIn signal generates internal load pulse that loads control word into parallel register. circuit enters mode this case Tx-mode). circuit stabilizes mode. When clock signal goes low, power amplifier (PA) turned slowly order minimize spurious components output signal. sure lock before turned should turned after LockDet been set. negative transition clock signal should come minimum time period comparison frequency after internal load pulse generated. power amplifier fully turned
When modulation implemented switching between different dividers values corresponding receive frequency both transmit frequencies have found.
Example 869.0MHz, 10.00MHz. modulation applied VCO.
RxFilt Ref6 Ref0 OutS1 Ref5 Ref4 Cpmp1 Cpmp0 OutS0 Mod1 Ref3 Mod0 Ref2 ByLNA Ref1 OutS2
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Binary form: (MSB left):
110010 110010 000010000111 000010000111 0001100100 0001100100 01011110000000010100000011 111011 111011 000010001110 000010001110 0001101010 0001101010 01011110000000010100000001
With modulation applied VCO, values corresponding receive frequency have found. same values used modes.
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Application circuit: modulation:
Figure shows example transceiver with modulation applied VCO. matching components optimized 869MHz. inductors trimming capacitors must have good high frequency performance.
4.7n4.7n 8.2k
MixQoutn MixQoutp MixIoutn MixIoutp IFQinn IFQinp IFIinn QchC IFIinp
varactor MA4ST-350-1141 single variable capacitance diode manufactured MACOM. pindiode Bar63 manufactured Siemens.
3.9p 3.9n Bar63 1.5k ant-switch
vb_lp IchC
IFGnd IFVdd
MixerVdd
IchOut QchOut
IchOut
MixerGnd LNA_C
QchOut
RFGnd2
OscVdd
BCC918
TQFP44
RFin
MA4ST350 1.5-3p
1.5k
OscIn
RFVdd RFGnd
5.6p
OscGnd
ground
RFout
1.5k
CmpOut PAbias
4.7n
100n
CmpR XoscIn DataIXO XoscOut
LockDet DigVdd DataC RegIn PdExt LD_C RSSI
PA_C DigGnd
470p
Bar63
270k
470p 470p 100n RegIn PuExt RSSI ClkIn 10MHz 3-10p 8.2p DataIXO LockDet 1.5k 150k 5.6p 5.6p
Figure Application circuit
List components
Component Values 8.2k 1.5k 150k 1.5k 270k 1.5k 1.5k 47pF 47pF 47pF Component Values 47pF 4.7nF 4.7nF 5.6pF 1.5pF-3pF 4.7nF 68nF 470pF 100nF 470pF 3pF-10pF 8.2pF 22pF Component crystal Values 470pF 10nF 47pF 3.9pF 47pF 47pF 5.6pF 5.6pF 47pF 12nH 3.9nH 12nH 10nH 10nH MA4ST-350-1141 BAR63 BAR63 10MHz
ClkIn
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5.1.2 Crystal oscillator
Circuit blocks
section
frequency synthesizer consists VCO, crystal oscillator, dual modulus prescaler, programmable frequency dividers, phase-detector, charge-pump, lock-detector external loopfilter. dual modulus prescaler divides VCOfrequency 64/65. This mode controlled A-divider. There sets Afrequency dividers. Using both sets transmit mode, implemented switching between those sets. phase-detector frequency/phase detector with back-slash pulses minimize phase-noise. VCO, crystal oscillator, charge-pump, lock-detector loop-filter will commented more detail below.
crystal oscillator very critical block. crystal oscillator reference output frequency also frequency receiver, very good phase frequency stability required. schematic crystal oscillator with external components 10MHz shown Figure These components optimized crystal with 15pF load capacitance.
DigVdd
10MHz 3-10p DigGnd XoscOut
Figure Crystal oscillator
5.1.1 Voltage controlled oscillator (VCO)
1.5k loopfilter_output MA4ST350 12nH 1.5-3p 5.6p
OscOut
crystal oscillator tuned varying trimming capacitor C19. drift frequency same drift crystal frequency when measured ppm. total difference ppm, f(ppm), between tuned frequency drifted frequency given
where
Figure
circuit schematic with external components shown Figure basically Colpitts oscillator. oscillator external resonator varactor. resonator consists inductor series connection capacitor C13, internal capacitance capacitance varactor. capacitance varactor (D1) decreases input voltage increases. frequency will therefore increase input voltage increases. positive gain (MHz/Volt). frequency tuned varying trimming capacitor C13. value capacitor becomes small amplitude signal decreases, which leads lower output power.
layout very critical. external components should placed close input (pin possible. Ground vias should next component pads.
total temperature coefficient oscillator frequency (due crystal components) ppm/°C. change temperature from room temperature, which crystal tuned. ageing ppm/year time years) elapsed since transceiver last tuned. demodulator will able decode data when ppm) larger than frequency deviation. small frequency deviations, crystal should pre-aged, should have small temperature coefficient. circuit been tested with 10MHz crystal, other crystal frequencies used well.
5.1.2.1 Prestart
start-up time crystal oscillator typically some milliseconds. Therefore, save current consumption, BCC918 circuit been designed that turned before other circuit block. During start-up amplitude will eventually reach sufficient level trigger M-counter. After counting M-counter output pulses rest circuit will turned current consumption during prestart period approximately 300µA.
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5.1.3 Lock detector
BCC918 circuit lock detector feature that indicates whether lock not. logic high (LockDet) means that lock. phase detector output converted into voltage that filtered external capacitor C22, connected LDC. resulting voltage compared reference window bits Ref0 Ref5. reference window stepped up/down linearly between 0Volt, Ref0 Ref5=1, Ref0 Ref5=0, which gives highest value voltage) reference window. size window either equal (Ref6=1) reference steps reference steps (Ref6=0). What setting that corresponds lock vary, depending e.g. temperature, loop filter type varactor. Therefore, lock detect circuit needs calibrated regularly software routine that finds correct setting, running through combinations bits Ref0 Ref5. Depending size reference window, there will several combinations that show lock. instance, with large reference window, much five combinations make lock detector show lock. have maximum robustness noise third settings should chosen.
5.1.5 Tuning
There circuit blocks that need tuning, crystal oscillator. 5.1.5.1 tuning Tune trimming capacitor resonator until lock charge pump output voltage (loop filter voltage) around mid-point supply rails. This particularly important when using modulation. gain curve (MHz/Volt) linear gain will therefore vary with loop voltage. This means that frequency deviation also varies with loop voltage. therefore important trim loop voltage same value from circuit circuit. When using internal modulation, tuning omitted long gain large enough allow handle variations process parameters temperature without going lock. 5.1.5.2 tuning Tune trimming capacitor crystal oscillator precise desired receive frequency. possible tune crystal oscillator over large frequency range. values must therefore chosen give frequency very close desired frequency. Because small tuning range will lock when tuning crystal oscillator.
5.1.4 Charge pump
charge-pump programmed four different modes with currents, ±125µA ±500µA. control word (cpmp1 cpmp0) controls operation. four modes are: cpmp1=0 Current constant ±125µA. Used cpmp0=0 applications where short lock time importance. cpmp1=0 Current constant ±500µA. Used cpmp0=1 applications where short lock time important, e.g. internal modulation. chapter 5.1.7.1. cpmp1=1 Current ±500µA when cpmp0=0 lock ±125µA when lock. Controlled LockDet (pin 15). Lock time halved. chapter 5.1.7.2. cpmp1=1 Same above cpmp0=1 current ±500µA. Used when using dual loop filters. chapter 5.1.7.3.
5.1.6 modulation
circuit sets frequency dividers frequency dividers programmed control word. programmed with receive frequency used receive mode. There three ways implementing FSK:
modulation applied VCO. This implementing modulation explained more detail chapter 5.1.7. values corresponding transmit frequency should programmed dividers DataIXO must kept tri-state from time Tx-mode entered until starts sending data. modulation switching between sets dividers. values corresponding receive frequency both transmit frequencies have found. transmit values corresponding
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data should programmed dividers values corresponding data should programmed dividers modulation adding/subtracting divider frequency deviation will equal comparison frequency. values corresponding transmit frequency should programmed dividers
With this loop filter, internal modulation 2400bps possible. lock time from power-down will approximately 1ms.
5.1.7.2 Modulation outside (closed loop)
types modulation, data entered DataIXO pin.
5.1.7 Loop filter
design loop filter great importance optimizing parameters like modulation rate, lock time, bandwidth phase-noise. bitrates will allow modulation inside PLL, which means loop will lock different frequency This implemented switching internal dividers Higher modulation rates (above 2400bps) imply implementation modulation outside PLL. This implemented applying modulation directly VCO. Loop filter values found using appropriate software program.
When modulation applied outside PLL, means that should track changes loop modulation signal. loop filter with relatively bandwidth therefore necessary. exact bandwidth will depend actual modulation rate. Because loop bandwidth will significantly lower than comparison frequency, second order loop filter will normally give adequate attenuation comparison frequency. not, third order loop filter give extra attenuation needed.
Example
Radio frequency Comparison frequency Loop bandwidth gain Phase comparator gain Phase margin
868MHz 140kHz 900Hz 30MHz/V 125µA/rad
component values will
4.7n
CmpR
5.1.7.1 Modulation inside
fast requires loop-filter with relatively high bandwidth. second order loop-filter chosen, give adequate attenuation comparison frequency. Therefore following example third order loop-filter chosen.
Example
Figure order loop filter.
Radio frequency Comparison frequency Loop bandwidth gain Phase comparator gain Phase margin Breakthrough suppression
868MHz 100kHz 3.8kHz 30MHz/V 500µA/rad 20dB
Data rates above approximately 19200baud (including Manchester coding) used with this loop filter without significant tracking modulating signal. lock time will approximately 4ms. faster lock time wanted, charge pump made deliver current 500µA unit phase error, while open drain NMOS chip (pin CmpR) switches second damping resistor (R10) ground shown Figure Once locked correct frequency, automatically returns standard noise operation (charge pump current: 125µA/rad). correct settings have been made control word (cpmp1=1, cpmp0=0), fast locking feature activated will reduce lock time factor without affecting phase margin loop. Components C17, C19, R11, (see application circuit) necessary modulation applied VCO. Data entered DataIXO-pin will then through Mod-
component values will
R101 C116 R109
C115
C101 100p
Figure order loop filter.
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(no. which current output. sources current 50uA when logic entered DataIXO drains current logic capacitance will order filtering baseband signal. large capacitance will give slow ramp-up therefore high order filtering baseband signal, while small capacitance gives fast ramp-up, which turn also gives broader frequency spectrum. Resistors frequency deviation. large compared C17, frequency deviation will large. should large avoid influencing loop filter. DataIXO must kept tri-state from time Tx-mode entered until starts sending data.
5.1.7.3 Modulation outside PLL, dual loop-filters
decrease with time current leakage. transmit time will therefore limited dependent bandwidth loop-filter. High bandwidth gives capacitor values loop voltage will decrease faster, which gives shorter transmit time. loop closed until locked desired frequency power amplifier turned loop immediately opens when modulation starts. loop will track modulation, modulation still needs free coupling modulation network.
Transmit section
5.2.1 Power amplifier (PA)
Modulation outside requires loop-filter with relatively bandwidth compared modulation rate. This results relatively long loop lock time. applications where modulation applied VCO, same time short start-up time from power down receive mode needed, dual loop-filters implemented. Figure shows implement dual loop-filters.
CmpOut
R102 4.7n C116 C115 C103 100p towards_VCO
power amplifier biased class last stage open collector, external load inductor (L2) therefore necessary. current amplifier adjusted with external bias resistor (R12). good starting point when designing 1.5k bias resistor which gives bias current approximately 50µA. This will give bias current last stage about 15mA. impedance matching circuit will depend type antenna used, should designed maximum output power. maximum output power load seen must resistive should about 100. output power programmable steps, with approximately between each step. This controlled bits Pa0. prevent spurious components from being transmitted should switched on/off slowly, allowing bias current ramp up/down rate determined external capacitor connected ramp up/down current typically 1.1µA, which makes on/off rate 3.0V power supply 2.6µs/pF. Turning on/off affects PLL. Therefore on/off rate must adjusted bandwidth.
R109
Figure Dual loop-filters
loop-filter used transmit mode made C15, C16, R10. fast lock feature also included (internal NMOS controlled FLC, Fast Lock Control). This filter automatically switched in/out internal NMOS QchOut, which controlled (Dual Filter Control). Bits OutS2, OutS1, OutS0 must 110. When QchOut used switch loop-filter ground, neither QchOut IchOut used test pins look different receiver signals. receive mode loop-filter comprises C115, C116, R109, R101 C101.
5.1.7.4 Modulation outside (open loop) this mode charge pump output tri-stated. loop open will therefore track modulation. This means that loop-filter have relatively high bandwidth, which give short switching times. However loop-voltage will
5.2.2 buffer
buffer amplifier connected between power amplifier ensure that input signal sufficient amplitude wanted output power. This buffer bypassed setting
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Receive section
5.3.1 Front-end (LNA mixers)
noise amplifier receivers used boost incoming signal prior frequency conversion process. This important order prevent mixer noise from dominating overall front-end noise performance. twostage amplifier nominal gain 23dB 900MHz. feedback loop, which provides bias LNA. external capacitor decouples stabilizes overall feedback loop, which large frequency loop gain. Figure shows input impedance LNA. Input matching very important high receive sensitivity. bypassed setting ByLNA `1'. This useful very strong signal levels. mixers have gain about 12dB 900MHz. differential outputs mixers available output impedance each mixer about 15k.
cut-off freq. (kHz)
Recommended channel spacing (kHz)
10kHz cut-off frequency first pole must generated externally connecting 820pF capacitor between outputs each mixer. 30kHz cut-off frequency 68pF capacitor needed between outputs. cut-off frequency gyrator filter varying external resistor, optimum channel spacing will depend cut-off frequencies Sallen-Key filter. table above shows recommended channel spacing depending different settings.
5.3.3 Gyrator-filter
main channel filter gyrator-capacitor implementation seven-pole elliptic lowpass filter. elliptic filter minimizes total capacitance required given selectivity dynamic range. external resistor adjust cut-off frequency gyrator filter. table below show cut-off frequency varies with bias resistor: Bias resistor Cut-off freq. (kHz)
gyrator filter cut-off frequency should chosen approximately same cut-off frequency Sallen-Key filter. maximum cut-off frequency gyrator filter 175kHz.
Figure Input impedance
5.3.4 Cut-off frequency setting 5.3.2 Sallen-Key filter preamplifier
Each channel includes pre-amplifier prefilter, which three-pole elliptic Sallen-Key lowpass filter with 20dB stopband attenuation. protects following gyrator filter from strong adjacent channel signals. preamplifier gain 20dB when Gc=0 30dB when Gc=1. output voltage swing about 200mVpp 30dB gain setting 1Vpp 20dB gain setting. third order Sallen-Key lowpass filter programmable four different cut-off frequencies according table below: cut-off frequency must high enough pass received signal (frequency deviation modulation). minimum cut-off frequency given
Baudrate frequency deviation fDEV =30kHz baudrate 20kbaud, minimum cut-off frequency 40kHz. setting Fc1=1 Fc0=0, which gives cut-off kHz, would best choice. gyrator filter bias resistor should therefore 7.5k gyrator filter cut-off frequency approximately 60kHz.
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crystal tolerance must also taken into account when selecting receiver bandwidth. crystal temperature tolerance e.g. ±10ppm over total temperature range, incoming signal signal theoretically 20ppm away from each other. frequency deviation must always larger than maximum frequency drift demodulator able demodulate signal. minimum frequency deviation (fDEV min) equal baudrate, according specification page This means that frequency deviation least equal baudrate plus maximum frequency drift. frequency deviation therefore vary from minimum frequency deviation minimum frequency deviation plus times maximum frequency drift. minimum cut-off frequency when crystal tolerances considered therefore given Baudrate where maximum frequency drift between signal incoming signal crystal tolerances. frequency drift 20ppm 8680Hz 434MHz. frequency deviation must higher than 28.68kHz baudrate 20kbaud. frequency deviation then vary from 20kHz, when signal 20ppm lower than signal, 37.36kHz when signal 20ppm higher than signal. minimum cut-off frequency therefore 47.36kHz.
zero frequency offsets). channel signal lags channel, tone frequency lies above frequency (data `1'). channel leads channel, tone lies below frequency (data `0'). inputs output demodulator filtered first order lowpass filters then amplified Schmitt triggers produce clean square waves. recommended bitrates (<10kbps) that additional capacitor connected (DataC) decrease bandwidth data signal filter. bandwidth filter must adjusted bitrate. This functionality controlled RxFilt.
5.3.7 Received Signal Strength Indicator (RSSI)
RSSI provides output voltage proportional strength input signal. graph typical RSSI response shown Figure (fDEV 30kHz, Gc=1).
-110 -100
(dBm)
Figure Typical RSSI characteristics
5.3.5 Limiter
limiter serves zero crossing detector, thus removing amplitude variations signal, while retaining only phase variations. limiter outputs ideally suited measure phase difference, since outputs square waves with sharp edges.
This graph shows range 0.7V 2.05V over input range 70dB. RSSI used signal presence indicator. When signal received, RSSI output increases. This could used wake circuitry that normally sleep mode configuration conserve battery life. Another application which RSSI could used determine transmit power reduced system. RSSI detects strong signal, could tell transmitter reduce transmit power reduce current consumption.
5.3.6 Demodulator
demodulator demodulates channel outputs produces digital data output. detects relative phase difference between channel signals. every edge (positive negative) channel limiter output, amplitude channel limiter output sampled, vice versa. output demodulator available DataIXO pin. data output therefore updated times cycle signal. This also means that maximum jitter data output 1/(4*f) (valid only
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