0.6µm Drawn Gate Length (0.5µm Leff) Sea-of-Gates Architecture With Tr

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0.6µm Drawn Gate Length (0.5µm Leff) Sea-of-Gates Architecture With Tr

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ATL60
0.6µm Drawn Gate Length (0.5µm Leff) Sea-of-Gates Architecture With Triple Level Metal Volt, Volt, Volt Operation Including Mixed Voltages Chip Phase Locked Loop Available Synthesize Frequencies Manage Chip-to-Chip Clock Skew Compiled (gate level) Embedded (custom) SRAMs, ROM, CAMs Available PCI, SCSI, High Speed (250 MHz) Buffers Available Easy Alternative Sourcing Existing ASIC, FPGA, Designs Design-for-Test methods Including JTAG, Serial Boundary Scan, ATPG High Output Drive Capability: with Slew Rate Control
Description
Atmel's next generation ATL60 Series CMOS Gate Arrays fabricated using 0.6µm drawn gate, oxide isolated, triple level metal process. Extensive cell libraries available support major software tools. with Atmel gate array families, customer involvement satisfaction integral steps design flow. variety Design Testability techniques supported libraries, wide range packaging options available. ATLS version utilizes fine pitch staggered bond pads achieve smallest size possible given count. ATLS60 only available limited number PQFP packages.
ATL60 ATLS60 Series Gate Arrays/ Embedded Arrays
ATL60/4 ATL60/15
ATL60 Array Organization
Device Number ATL60/4 ATL60/15 ATL60/25 ATL60/40 ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL60/200 ATL60/235 ATL60/300 ATL60/435 ATL60/550 ATL60/700 ATL60/870 ATL60/1100
Note:
ATL60/25
Count Pins Gate(1) Speed
Gates 4,000 15,000 25,000 38,000 58,000 86,000 110,000 149,000 195,000 232,000 301,000 430,000 545,000 693,000 870,000 1,119,000
Routable Gates 3,000 10,000 16,900 25,400 34,600 51,900 65,900 89,300 116,900 139,500 181,000 260,000 288,000 363,000 456,000 590,000
ATL60/40 ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL60/200 ATL60/235 ATL60/300 ATL60/435 ATL60/550 ATL60/700 ATL60/870 ATL60
0388B 6-15 ATL60 ATLS60 Series Gate Arrays/ Embedded Arrays
Nominal Input NAND Gate with volts
ATLS60 Array Organization
Device Number ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATLS60/225 ATLS60/256
Note:
Gates 12,500 20,400 30,200 44,600 55,300 96,500 113,500 148,200
Routable Gates 8,000 13,000 17,500 26,000 32,500 57,000 67,500 88,000
Count
Pins
Gate Speed
Nominal Input NAND Gate with volts
Design
Design Systems Supported Atmel supports several major software systems design with complete macro cell libraries, well utilities checking netlist accurate pre-route delay simulations. CadenceVerilog-XLis Atmel's golden simulator. MentorQuickSim IIis sign-off level simulator. following design systems supported: Level DesignFloor Planner This includes functional well timing performance evaluation. Upon completion this critical step, Atmel performs physical place-and-route. Additional simulations performed, based physical design, including generation back annotation report provide customer with most accurate timing information available. Final Design Review last step design flow prior generation masks. After this acceptance step completed, masks generated released, prototype parts, ceramic packages, delivered.
Definition Requirements Design Flow
Atmel provides four methods implementing gate array design, while maintaining same basic design flow each them. This flow involves both Customer Atmel critical review acceptance steps, seen from chart below. Data Base Acceptance occurs when Atmel receives accepts complete design data base. Preliminary Design Options Design Review follows Cadence simulation verification Atmel. Schematic Capture Within Physical Design Step (ie. layout) certain restrictions apply during definition. corner pins each reserved programmable Power Ground only. other buffer pins fully programmable Input, Output, Bi-directional, Clock-into-Array, Power, Ground.
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ATL60
ATL60
ATL60 Gate Array Design Flow
Customer Atmel Cell Library Gate Array Design Translation Design Synthesis -VHDL -Verilog-HDL FPGA/PLD Conversions Atmel
Database Acceptance
Atmel
Simulation Verification
Atmel
Customer
Preliminary Design Review
Atmel
Physical Design, Simulation Verification
Atmel
Customer
Final Design Review
Atmel
Customer
Prototype Delivery
schematic capture method design performed customer using Atmel provided macro cell library. complete netlist vector must then provided Atmel. Upon acceptance this data set, Atmel continues with standard design flow.
These designs have been optimized speed gate count modified logic memory, replicated pin-for-pin compatible, drop-in replacement.
FPGA Conversions
Atmel successfully translated existing FPGA/PLD designs from most major vendors (Xilinx, Actel Altera, Atmel) into gate arrays. There four primary reasons convert from FPGA/PLD gate array. Conversion high volume devices (over 10,000 units) single combined design cost effective. Performance often optimized speed power consumption. Several FPGA/PLDs combined onto single chip minimize cost while reducing on-board space requirements. Finally, situations where FPGA/PLD used fast cycle time prototyping, gate array provide lower cost answer long-term volume production.
VHDL/Verilog-HDL
Atmel accept Register Transfer Level (RTL) designs VHDL (MIL-STD-454, IEEE 1076) Verilog-HDL format. Atmel fully supports Synopsys VHDL simulation well synthesis. VHDL Verilog-HDL Atmels preferred method performing gate array design.
ASIC Design Translation
Atmel successfully translated dozens existing designs from most major ASIC vendors (LSI Logic, Motorola, SMOS, Oki, NEC, Fujitsu, others) into gate arrays.
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Embedded Array
Mixed Voltage Operation
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ATL60
ATL60
ATL60 Series Cell Library
Atmels ATL60 Series gate arrays make extensive library macro cell structures, including logic cells, buffers inverters, multiplexers, decoders, options. Soft macros also available. ATL60 Series operates frequencies with minimal phase error jitter, making ideal frequency synthesis high speed on-chip clocks chip chip synchronization. Output buffers programmable meet voltage current requirements both SCSI. These cells well characterized SPICE modeling transistor level, with performance verified anufact test arrays. Character ization performed over military temperature voltage ranges ensure that simulation accurately predicts performance finished product.
Cell Index
Signal Name ADD3X AND2 AND2H AND3 AND3H AND4 AND4H AND5 AOI22 AOI22H AOI222 AOI222H AOI2223 AOI2223H AOI23 BUF1 BUF2 BUF2T BUF2Z BUF3 BUF4 BUF8 BUF12 BUF16 CLA7X DEC4 DEC4N DEC8N
Note:
Description full adder with buffered outputs input input high drive input input high drive input input high drive input input into input input into input high drive Two, input ANDs into input Two, input ANDs into input high drive Three, input ANDs into input Three, input ANDs into input high drive input into input buffer buffer State driver with active high enable State driver with active enable buffer buffer buffer buffer buffer input carry lookahead decoder decoder with active enable decoder with active enable
Site Count(1)
single ATL60 routing site contains transistors, N-channel P-channel, aligned columns. number sites used gate varies according specific isolation power requirements. Percent utilization varies from 70%, with more accurate utilization figures generated netlist checker software(v3h).
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Cell Index
Signal Name DFFBCPX DFFBSRX DFFC DFFR DFFS DFFSR DLY1500 DLY2000 DLY6000 DSSBCPY DSSBR DSSBS DSSR DSSS DSSSR INV1 INV1D INV1Q INV1TQ INV2 INV2T INv3h INV4 INV8 INV10 JKFBCPX JKFC LATBG LATBH
Note:
Description flip-flop flip-flop with asynchronous clear preset with complementary outputs flip-flop with asynchronous reset with complementary outputs flip flop with asynchronous clear flip-flop with asynchronous reset flip-flop with asynchronous flip-flop with asynchronous reset Delay buffer Delay buffer Delay buffer scan flip-flop scan flip-flop with clear preset scan flip-flop with reset scan flip-flop with scan flip-flop with reset scan flip-flop with scan flip-flop with reset inverter Dual inverters Quad inverters Quad State inverter inverter State inverter with active high enable inverter inverter inverter inverter flip-flop Clear preset flip-flop with asynchronous clear preset complementary outputs flip-flop with asynchronous clear LATCH LATCH with complementary outputs inverted gate signal LATCH with high drive complementary outputs
Site Count(1)
single ATL60 routing site contains transistors, N-channel P-channel, aligned columns. number sites used gate varies according specific isolation power requirements. Percent utilization varies from 70%, with more accurate utilization figures generated netlist checker software(v3h).
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ATL60
ATL60
Cell Index
Signal Name LATR LATS LATSR LSCC LSISO MUX2 MUX2H MUX2I MUX2IH MUX2N MUX2NQ MUX2Q MUX3I MUX3IH MUX4 MUX4X MUX4XH MUX5H MUX8 MUX8N MUX8XH NAN2 NAN2D NAN2H NAN3 NAN3H NAN4 NAN4H NAN5 NAN5H NAN6 NAN6H NAN8 NAN8H NOR2
Note:
Description LATCH with reset LATCH with LATCH with reset Voltage level shifter Voltage level shifter with power supply isolation function high drive with inverted output with inverted output high drive with active enable Quad with active enable Quad with inverted output with inverted output high drive with transmission gate data inputs with transmission gate data inputs high drive high drive with active enable with transmission gate data inputs high drive input NAND Dual input NAND input NAND high drive input NAND input NAND high drive input NAND input NAND high drive input NAND input NAND high drive input NAND input NAND high drive input NAND input NAND high drive input
Site Count(1)
single ATL60 routing site contains transistors, N-channel P-channel, aligned columns. number sites used gate varies according specific isolation power requirements. Percent utilization varies from 70%, with more accurate utilization figures generated netlist checker software(v3h).
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Cell Index
Signal Name NOR2D NOR2H NOR3 NOR3H NOR4 NOR4H NOR5 NOR8 OAI22 OIA22H OAI222 OAI222H OAI22224 OAI23 ORR2 ORR2H ORR3 ORR3H ORR4 ORR4H ORR5 XNR2 XNR2H XOR2 XOR2H
Note:
Description Dual input input high drive input input high drive input input high drive input input input into input NAND input into input NAND high drive Two, input into input NAND Two, input into input NAND high drive Four, input into input NAND input into input NAND input input high drive input input high drive input input high drive input input exclusive input exclusive high drive input exclusive input exclusive high drive
Site Count(1)
single ATL60 routing site contains transistors, N-channel P-channel, aligned columns. number sites used gate varies according specific isolation power requirements. Percent utilization varies from 70%, with more accurate utilization figures generated netlist checker software(v3h).
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ATL60
ATL60
Buffer Cell Index
Signal Name PBD2C PBC3C PBD32TS PBD5C PBDSCSITS PBS1C PBS1CS PBS1TS PBS2C PBS2CS PBS2T PBS2TS PBS3C PBS3CS PBS31T PBS3T PBS3TS PBS4C PBS4CS PBS4T PBS4TS PBS5C PBS5CS PBS5T PBS5TS PBS6C PBS6CS PBS6T PBS6TS PBS7C PBS7CS PBS7T PBS7TS PBS8C PBS8CS PBS8T PBS8TS PBS9C Description bidi CMOS buffer bidi CMOS buffer bidi buffer with Schmitt Trigger bidi buffer with Schmitt Trigger 48mA NMOS, SCSI buffer with Schmitt Trigger bidi CMOS buffer bidi CMOS buffer with Schmitt Trigger bidi buffer with Schmitt Trigger bidi CMOS input buffer bidi CMOS input buffer with Schmitt Trigger bidi buffer with Schmitt Trigger bidi CMOS buffer with Schmitt Trigger bidi buffer bidi buffer bidi with Schmitt Trigger bidi CMOS buffer bidi CMOS buffer with Schmitt Trigger bidi buffer bidi buffer bidi CMOS buffer bidi with Schmitt Trigger bidi buffer with Schmitt Trigger bidi CMOS buffer bidi Schmitt Trigger bidi buffer bidi buffer with Scmitt Trigger bidi CMOS buffer bidi CMOS buffer with Schmitt Trigger bidi buffer bidi buffer with Schmitt Trigger bidi CMOS buffer bidi CMOS buffer with Schmitt Trigger bidi buffer bidi buffer with Schmitt Trigger bidi CMOS buffer
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Buffer Cell Index
Signal Name PBS9CS PBS9T PBS9TS PBSAC PBSACS PBSAT PBSATS PBSA6T PBSBC PBSBCS PBSBT PBSBTS PBSCC PBSCCS PBSCT PBSC1T PBSCTS PICI PICS PITS PO2B PO61 POZ8B 6-24 Description bidi CMOS buffer with Schmitt Trigger bidi buffer bidi buffer with Schmitt Trigger bidi CMOS buffer bidi CMOS buffer with Schmitt Trigger bidi buffer bidi with Schmitt Trigger bidi buffer bidi CMOS buffer bidi CMOS buffer with Schmitt Trigger bidi buffer bidi buffer with Schmitt Trigger dibi CMOS buffer bidi CMOS buffer with Schmitt Trigger bidi buffer bidi buffer bidi buffer with Schmitt Trigger CMOS input buffer CMOS inverting input buffer CMOS input buffer with Schmitt Trigger input buffer input buffer with Schmitt Trigger clock driver clock driver output buffer output buffer inverting output buffer output buffer output buffer output buffer output buffer output buffer output buffer output buffer open Crain inverting output buffer output buffer output buffer output buffer
ATL60
ATL60
Buffer Cell Index
Signal Name PTD2 PTD3 PTD32 PTD5 PTS1 PTS2 PTS3 PTS31 PTS33 PTS4 PTS41 PTS5 PTS6 PTS63 PTS7 PTS8 PTS81 PTS9 PTSA PTSA6 PTSB PTSC PTSC1 PTSC2 PX2CL PX2CR PX4CL PX4CR Description output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer crystal oscillator buffer (left side normalized input) crystal oscillator buffer (right side normalized input) crystal oscillator buffer (left side normalized input crystal oscillator buffer (right side normalized input)
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CMOS Input Interface Characteristics
Interface CMOS Logic High 3.5V Minimum 2.0V Minimum Logic 1.5V Maximum 0.8V Maximum Switchpoint Typical 1.4V Typical
Absolute Maximum Ratings*
Operating Temperature. -55°C +125°C Storage Temperature. -65°C +150°C Voltage with Respect Ground .-2.0V +7.0V1 Maximum Operating Voltage 6.0V
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Note:
Volt Characteristics
Applicable over recommended operating range from -55°C +125°C, 4.5V 5.5V (unless otherwise noted) Symbol Parameter Input Leakage High Input Leakage pull-up) pull-up Output Leakage pull-up) Output Short Circuit Current Buffer)(1) Input Voltage CMOS Input Voltage Input High Voltage CMOS Input High Voltage Switching Threshold CMOS Switching Threshold Output Voltage Output buffer stages drive capability with stage Output High Voltage Output buffer stages drive capability with -2mA stage Test Condition VIN=VDD, VDD=5.5V VIN=VSS, VDD=5.5V VIN=VSS, VDD=5.5V VIN=VDD VSS, DD=5.5V VDD=5.5V, VOUT=V VDD=5.5V, VOUT=V -100 VDD=5.0V, 25°C VDD=5.0V, 25°C IOL=as rated VDD=4.5V Units
IOH=as rated VDD=4.5V
Note:
This specification Buffer. Output short circuit current other outputs will scale accordingly. more than output shorted time, maximum second, allowed.
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ATL60
ATL60
Volt Characteristics
Applicable over recommended operating range from -55°C +125°C, 2.7V 3.6V (unless otherwise noted) Symbol Parameter Input Leakage High Input Leakage pull-up) pull-up (U31) Output Leakage pull-up) Output Short Circuit Current Buffer)(1) CMOS Input Voltage CMOS Input High Voltage CMOS Switching Threshold Output Voltage Output buffer stages drive capability with stage. Output High Voltage Output buffer stages drive capability with -1mA stage. VDD=3.0V, 25°C IOL=as rated VDD=2.7V 0.7xVDD Test Condition VIN=VDD, VDD=3.6V VIN=VSS, VDD=3.6V VIN=VSS, VDD=3.6V VIN=VDD VSS, DD=3.6V VDD=3.6V, VOUT=VDD VDD=3.6V, VOUT=VSS Units
IOH=as rated VDD=2.7V
0.7xVDD
Volt Characteristics
Applicable over recommended operating range from -0°C +70°C, 1.8V 2.2V (unless otherwise noted) Symbol Parameter Input Leakage High Test Condition VIN=V VDD=2.2V 0.8xVDD 0.5xVDD rated DD=1.8V Units
Input Leakage pull-up) IN=V VDD=2.2V pull-up (U31) IN=V VDD=2.2V Output Leakage pull-up) Output Short Circuit Current Buffer)(1) CMOS Input Voltage CMOS Input High Voltage CMOS Switching Threshold Output Voltage Output buffer stages drive capability with 0.5mA stage. Output High Voltage Output buffer stages drive capability with -0.5mA stage. VIN=V VSS, DD=2.2V DD=2.2V, VOUT=VDD DD=2.2V, VOUT=VSS
rated DD=1.8V
0.8xVDD
Note:
This specification Buffer. Output short circuit current other outputs will scale accordingly. more than output shorted time, maximum second, allowed.
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Buffer Characteristics
Symbol COUT CI/O Parameter Capacitance, Input Buffer (die) Test Condition 5.0V, 3.3V, 2.0V Units
Capacitance, Output Buffer (die) 5.0V, 3.3V, 2.0V Capacitance, Bi-Directional 5.0V, 3.3V, 2.0V
Schmitt Trigger Positive Threshold CMOS Positive Threshold Negative Threshold CMOS Negative Threshold Hysteresis CMOS Hysteresis CMOS Positive Threshold CMOS Negative Threshold CMOS Hysteresis 25°C, 5.0V 25°C, 5.0V 25°C, 5.0V 25°C, 5.0V 25°C, 5.0V 25°C, 5.0V 25°C, 3.3V 25°C, 3.3V 25°C, 3.3V
Buffers
Programmable output drive IOL; volts IOL; volts 2000 5000 volts protection Programmable slew rate control Built-in configurable test logic
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ATL60
ATL60
Design Testability
Atmel supports wide range Design Testability techniques improve percentage design that fully tested. achieving high degree testability, designer reduce design prototype debug time, minimize production test time, improve board system level test diagnostic capability. Synopsys Test Compiler software fully supported Atmel. this system during design, computer will create scan chains design, test vectors will generated provide greater than fault coverage. This method requires only added pins Test Enable Test Mode. This easiest least expensive method designing testability into gate array design. means increasing testability gate array also available. Partitioning, memory array isolation, test point insertion encouraged supported ATL60 Series gate arrays. Atmel also encourages inclusion Built Self-Test (BIST) techniques whenever possible. Each these methods discussed detail Atmel CMOS Gate Array Design Manual. addition above, ATL60 Series gate arrays also support Joint Test Action Group (JTAG) boundary cces requirements. required soft hard macros implement IEEE 1149.1 compliant architecture available Atmel's cell library. JTAG architecture requires additional pins test mode, data, clock signals.
Advanced Packaging
ATL60 Series gate arrays offered wide variety standard packages, including plastic ceramic quad flatpacks, thin quad flatpacks, ceramic grid arrays, ball grid arrays. High volume on-shore off-shore contractors provide assembly test commercial product, with prototype capability Colorado Springs. Custom package designs also available required meet customer's specific needs, supported hrough package design cent When standard package cannot meet customer's need, package designed precisely application maintain performance obtained silicon. Atmel delivered custom-designed packages wide variety configurations.
Packaging Options
Package Type PQFP TQFP PLCC CPGA CQFP Count 100, 120, 128, 132, 144, 160, 184, 208, 240, 100, 120, 128, 144, 160, 176, 100, 124, 144, 155, 180, 223, 224, 299, 100, 120, 132, 144, 160, 224, 121, 169, 225,
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0.6µm Drawn Gate Length (0.5µm Leff) Sea-of-Gates Architecture With Tr

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