0.5µm Drawn Gate Length (0.45µm Leff) Sea-of-Gates Architecture With T

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0.5µm Drawn Gate Length (0.45µm Leff) Sea-of-Gates Architecture With T

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ATL50
0.5µm Drawn Gate Length (0.45µm Leff) Sea-of-Gates Architecture With Triple Level Metal Volt Operation Volt compatible input buffers On-Chip Phase Locked Loop (PLL) Available Synthesize Frequencies Manage Chip-to-Chip Clock Skew Compiled (gate level) Embedded (custom) SRAMs, ROM, CAMs Available 3.3V PCI, SCSI, High Speed (250 MHz) Buffers Available Easy Alternative Sourcing Existing ASIC, FPGA, Designs Design-for-Test methods Including JTAG, Serial Boundary Scan, ATPG
Description
Atmel's next generation ATL50 Series CMOS Gate Arrays fabricated using 0.5µm drawn gate, oxide isolated, triple level metal process. Extensive cell libraries available support major software tools. with Atmel gate array families, customer involvement satisfaction integral steps design flow. variety Design Testability techniques supported libraries, wide range packaging options available.
ATL50 Series Gate Arrays/ Embedded Arrays
ATL50/4 ATL50/15 ATL50/25 ATL50/40 ATL50/60 ATL50/85 ATL50/110 ATL50/150 ATL50/200 ATL50/235 ATL50/300 ATL50/435 ATL50/550 ATL50/700 ATL50/870 ATL50/1100
ATL50 Array Organization
Device Number ATL50/4 ATL50/15 ATL50/25 ATL50/40 ATL50/60 ATL50/85 ATL50/110 ATL50/150 ATL50/200 ATL50/235 ATL50/300 ATL50/435 ATL50/550 ATL50/700 ATL50/870 ATL50/1100
Note:
Gates 4,000 15,000 25,000 38,000 58,000 86,000 110,000 149,000 195,000 232,000 301,000 430,000 545,000 693,000 870,000 1,119,000
Routable Gates 3,000 10,000 16,900 25,400 34,600 51,900 65,900 89,300 116,900 139,500 181,000 260,000 288,000 363,000 456,000 590,000
Count
Pins
Gate(1) Speed
Nominal Input NAND Gate volts
ATL50 Series Gate Arrays/ Embedded Arrays
0753B
Design
Design Systems Supported
Atmel supports several major software systems design with complete macro cell libraries, well utilities checking netlist accurate pre-route delay simulations. CadenceVerilog-XLis Atmel's golden simulator. MentorQuickSim IIis sign-off level simulator. following design systems supported: Level DesignFloor Planner This includes functional well timing performance evaluation. Upon completion this critical step, Atmel performs physical place-and-route. Additional simulations performed, based physical design, including generation back annotation report provide customer with most accurate timing information available. Final Design Review (FDR) last step design flow prior generation masks. After FDR, masks generated, wafers fabricated, prototype parts delivered.
Design Flow
Atmel provides four methods implementing gate array design, while maintaining same basic design flow each them. This flow involves both Customer Atmel critical review acceptance steps, seen from chart below. Data Base Acceptance occurs when Atmel receives accepts complete design data base. Preliminary Design Review follows Cadence simulation verification Atmel.
Definition Requirements
Within Physical Design Step (i.e., layout) certain restrictions apply during definition. corner pins each reserved programmable Power Ground only. other buffer pins fully programmable Input, Output, Bi-directional, Clock-into-Array, Power, Ground.
ATL50
ATL50
Design Options
Schematic Capture
schematic capture method design performed customer using Atmel provided macro cell library. complete netlist vector must then provided Atmel. Upon acceptance this data set, Atmel continues with standard design flow. speed gate count modified logic memory, replicated pin-for-pin compatible, drop-in replacement.
FPGA Conversions
Atmel successfully translated existing FPGA/PLD designs from most major vendors (Xilinx, Actel, Altera, AMDand Atmel) into gate arrays. There four primary reasons convert from FPGA/PLD gate array. Conversion high volume devices (over 10,000 units) single combined design cost effective. Performance often optimized speed power consumption. Several FPGA/PLDs combined onto single chip minimize cost while reducing on-board space requirements. Finally, situations where FPGA/PLD used fast cycle time prototyping, gate array provide lower cost answer long-term volume production.
VHDL/Verilog-HDL
Atmel accept Register Transfer Level (RTL) designs Verilog-HDLformat. Atmel fully supports Synopsys VHDLsimulation well synthesis. VHDL Verilog-HDL Atmel's preferred method performing gate array design.
ASIC Design Translation
Atmel successfully translated dozens existing designs from most major ASIC vendors (LSI Logic, Motorola, SMOS, Oki, NEC, Fujitsu, AMIand others) into gate arrays. These designs have been optimized
ATL50 Embedded Array
ATL50 Series Cell Library
Atmel's ATL50 Series gate arrays make extensive library macro cell structures, including logic cells, buffers inverters, multiplexers, decoders, options. Soft macros also available. ATL50 Series operates frequencies with minimal phase error jitter, making ideal frequency synthesis high speed on-chip clocks chip chip synchronization. Output buffers programmable meet voltage current requirements both SCSI. These cells well characterized SPICE modeling transistor level, with performance verified manufactured test arrays. Characterization performed over military temperature voltage ranges ensure that simulation accurately predicts performance finished product.
Cell Index
Signal Name ADD3X AND2 AND2H AND3 AND3H AND4 AND4H AND5 AOI22 AOI22H AOI222 AOI222H AOI2223 AOI2223H AOI23 BUF1 BUF2 BUF2T BUF2Z BUF3 BUF4 BUF4T BUF8 BUF12 BUF16 CLA7X DEC4 DEC4N Description full adder with buffered outputs input input high drive input input high drive input input high drive input input into input input into input high drive Two, input ANDs into input Two, input ANDs into input high drive Three, input ANDs into input Three, input ANDs into input high drive input into input buffer buffer State driver with active high enable State driver with active enable buffer buffer Tri-State driver with active high enable buffer buffer buffer input carry lookahead decoder decoder with active enable Site Count(1)
Note: single ATL50 routing site contains transistors, N-channel P-channel, aligned columns. number sites used gate varies according specific isolation power requirements. Percent utilization varies from 70%, with more accurate utilization figures generated Atmel's proprietary netlist checker software (v3h).
ATL50
ATL50
Cell Index
Signal Name DEC8N DFFBCPX DFFBSRX DFFC DFFR DFFS DFFSR DLY1500 DLY2000 DLY3000 DLY6000 DSSBCPY DSSBR DSSBS DSSR DSSS DSSSR HLD1 INV1 INV1D INV1Q INV1TQ INV2 INV2T INV3 INV4 INV8 INV10 JKFBCPX JKFC
Note:
Description decoder with active enable flip-flop flip-flop with asynchronous clear preset with complementary outputs flip-flop with asynchronous reset with complementary outputs flip flop with asynchronous clear flip-flop with asynchronous reset flip-flop with asynchronous flip-flop with asynchronous reset Delay buffer Delay buffer Delay buffer Delay buffer scan flip-flop scan flip-flop with clear preset scan flip-flop with reset scan flip-flop with scan flip-flop with reset scan flip-flop with scan flip-flop with reset hold cell inverter Dual inverters Quad inverters Quad State inverter inverter State inverter with active high enable inverter inverter inverter inverter flip-flop Clear preset flip-flop with asynchronous clear preset complementary outputs flip-flop with asynchronous clear
Site Count(1)
single ATL50 routing site contains transistors, N-channel P-channel, aligned columns. number sites used gate varies according specific isolation power requirements. Percent utilization varies from 70%, with more accurate utilization figures generated Atmel's proprietary netlist checker software (v3h).
Cell Index
Signal Name LATBG LATBH LATR LATS LATSR MUX2 MUX2H MUX2I MUX2IH MUX2N MUX2NQ MUX2Q MUX3I MUX3IH MUX4 MUX4X MUX4XH MUX5H MUX8 MUX8N MUX8XH NAN2 NAN2D NAN2H NAN3 NAN3H NAN4 NAN4H NAN5 NAN5H NAND5S NAN6 NAN6H NAN8 Description LATCH LATCH with complementary outputs inverted gate signal LATCH with high drive complementary outputs LATCH with reset LATCH with LATCH with reset high drive with inverted output with inverted output high drive with active enable Quad with active enable Quad with inverted output with inverted output high drive with transmission gate data inputs with transmission gate data inputs high drive high drive with active enable with transmission gate data inputs high drive input NAND Dual input NAND input NAND high drive input NAND input NAND high drive input NAND input NAND high drive input NAND input NAND high drive input NAND single stage input NAND input NAND high drive input NAND Site Count(1)
Note: single ATL50 routing site contains transistors, N-channel P-channel, aligned columns. number sites used gate varies according specific isolation power requirements. Percent utilization varies from 70%, with more accurate utilization figures generated Atmel's proprietary netlist checker software (v3h).
ATL50
ATL50
Cell Index
Signal Name NAN8H NOR2 NOR2D NOR2H NOR3 NOR3H NOR4 NOR4H NOR5 NOR5S NOR8 OAI22 OIA22H OAI222 OAI222H OAI22224 OAI23 ORR2 ORR2H ORR3 ORR3H ORR4 ORR4H ORR5 XNR2 XNR2H XOR2 XOR2H
Note:
Description input NAND high drive input Dual input input high drive input input high drive input input high drive input input single stage input input into input NAND input into input NAND high drive Two, input into input NAND Two, input into input NAND high drive Four, input into input NAND input into input NAND input input high drive input input high drive input input high drive input input exclusive input exclusive high drive input exclusive input exclusive high drive
Site Count(1)
single ATL50 routing site contains transistors, N-channel P-channel, aligned columns. number sites used gate varies according specific isolation power requirements. Percent utilization varies from 70%, with more accurate utilization figures generated Atmel's proprietary netlist checker software (v3h).
Buffer Cell Index
Signal Name PBD2C PBC3C PBD5C PBS1C PBS1CS PBS2C PBS2CS PBS3C PBS3CS PBS4C PBS4CS PBS5C PBS5CS PBS6C PBS6CS PICI PICS PO2B PTD2 PTD3 PTD5 PTS1 PTS2 PTS3 PTS4 PTS5 PTS6 PX2CL PX2CR PX4CL PX4CR Description bidi CMOS buffer bidi CMOS buffer bidi buffer with Schmitt Trigger bidi CMOS buffer bidi CMOS buffer with Schmitt Trigger bidi CMOS input buffer bidi CMOS input buffer with Schmitt Trigger bidi CMOS buffer with Schmitt Trigger bidi CMOS buffer bidi CMOS buffer with Schmitt Trigger bidi CMOS buffer bidi with Schmitt Trigger bidi CMOS buffer bidi Schmitt Trigger CMOS input buffer CMOS inverting input buffer CMOS input buffer with Schmitt Trigger clock driver output buffer output buffer inverting output buffer output buffer output buffer output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer State output buffer crystal oscillator buffer (left side normalized input) crystal oscillator buffer (right side normalized input) crystal oscillator buffer (left side normalized input crystal oscillator buffer (right side normalized input)
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ATL50
ATL50
Absolute Maximum Ratings*
Operating Ambient Temperature -55°C +125°C Storage Temperature. -65°C +150°C Voltage with Respect Ground .-2.0V +5.0V(1) Maximum Operating Voltage 3.7V
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Note: Minimum voltage -0.6V which undershoot -2.0V pulses less than Maximum output voltage 0.75V which overshoot +5.0V pulses less than
Volt Characteristics
Applicable over recommended operating range unless otherwise noted
Symbol Parameter
Operating Temperature Supply Voltage High-level Input Current
Buffer
TTL, CMOS TTL, CMOS
Test Condition
Units
degrees
VDD, VDD(max)
VSS, VDD(max), pull VSS, VDD(max) pull (33kOhm)
-100
Low-level Input Current
TTL, CMOS
High-impedance state Output Current
VSS, VDD(max), pull VOUT VDD, VDD(max) VOUT VSS, VDD(max)
0.475VDD
Output Short-circuit Current Buffer Buffer TTL, CMOS
High-level Input Voltage
CMOS Schmitt
Low-level Input Voltage
TTL, CMOS CMOS Schmitt rated, VDD(min) -500uA rated, VDD(min) 1.5mA
0.325
VHYS
Hysteresis High-level Output Voltage
TTL, CMOS TTL, CMOS
Low-level Output Voltage
TTL, CMOS
6-11
Buffer Characteristics
Symbol COUT CI/O Parameter Capacitance, Input Buffer (die) Capacitance, Output Buffer (die) Capacitance, Bi-Directional Test Condition 3.3V 3.3V 3.3V Units
Buffers
Programmable output drive 12mA IOL, -12mA 3.3V) 2,000 5,000 volts protection Programmable slew rate control Built-in configurable test logic
pins Test Enable Test Mode. This easiest least expensive method designing testability into gate array design. means increasing testability gate array also available. Partitioning, memory array isolation, test point insertion encouraged supported ATL50 Series gate arrays. Atmel also encourages inclusion Built Self-Test (BIST) techniques whenever possible. Each these methods discussed detail Atmel CMOS Gate Array Design Manual. addition above, ATL50 Series gate arrays also support Joint Test Action Group (JTAG) boundary scan architecture Test Access Port (TAP) requirements. required soft hard macros implement IEEE 1149.1 compliant architecture available Atmel's cell library. JTAG architecture requires additional pins test mode, data, clock signals.
Design Testability
Atmel supports wide range Design Testability techniques improve percentage design that fully tested. achieving high degree testability, designer reduce design prototype debug time, minimize production test time, improve board system level test diagnostic capability. Synopsys Test Compiler software fully supported Atmel. this system during design, computer will create scan chains design, test vectors will generated provide greater than fault coverage. This method requires only added
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ATL50
ATL50
Advanced Packaging
ATL50 Series gate arrays offered wide variety standard packages, including plastic ceramic quad flatpacks, thin quad flatpacks, ceramic grid arrays, ball grid arrays. High volume on-shore off-shore contractors provide assembly test commercial product, with prototype capability Colorado Springs. Custom package designs also available required meet customer's specific needs, supported through Atmel's package design center. When standard package cannot meet customer's need, package designed precisely application maintain performance obtained silicon. Atmel delivered ustom design packages wide variet configurations.
Packaging Options
Package Type PQFP TQFP PLCC CPGA CQFP Count 100, 120, 128, 132, 144, 160, 184, 208, 240, 100, 120, 128, 144, 160, 176, 100, 124, 144, 155, 180, 223, 224, 299, 100, 120, 132, 144, 160, 224, 121, 169, 225,
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0.5µm Drawn Gate Length (0.45µm Leff) Sea-of-Gates Architecture With T

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