Dual 6-bit Gsps Converter AT76C610 Preliminary Applications

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Dual 6-bit Gsps Converter AT76C610 Preliminary Applications

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Dual 6-bit Resolution Full-power Input Bandwidth Gsps Sampling Rate SINAD (5.7 ENOB) SFDR Gsps, 2-tone IMD: Gsps, MHz, 0.25 Typ, 0.25 Channel-to-channel Input Offset Error: Max, Gain Matching (Channel-to-channel): ±0.5 Max, ±0.25 Error Rate (10-10) Gsps Very Input Capacitance: Differential Single Analog Inputs Differential Single-ended PECL-compatible Clock Inputs LVDS Output Compatibility (100) Data Output De-multiplexer Power Consumption: 25°C 70°C Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output) Available 80-lead TQFP Package
Dual 6-bit Gsps Converter AT76C610 Preliminary
Applications
Satellite Receiver Direct Down-conversion
Description
AT76C610 monolithic dual 6-bit analog-to-digital converter, designed digitizing in-phase quadrature wide bandwidth analog signals very high sampling rates Gsps (gigasamples second). ability directly interface signals makes AT76C610 ideal applications such direct satellite demodulation. AT76C610 uses innovative architecture fabricated with advanced high-speed bipolar process. on-chip cores have closely matched full-power input bandwidth, providing excellent dynamic performance undersampling applications (high digitizing). samples from each converter de-multiplexed ratio output data stream LVDS-compliant.
Rev. 2100A-02/01
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Figure AT76C610 Symbol
VCCA VCCD VCC0
VINI VINIB VINQ VINQB AT76C610
DOAI0:DOAI5 DOAI0N:DOAI5N DOBI0:DOBI5 DOBI0N:DOBI5N DOAQ0:DOAQ5 DOAQ0N:DOAQ5N DOBQ0:DOBQ5 DOBQ0N:DOBQ5N DOIR, DOIRN CLKO CLKOB
CLKB
GNDA
GNDD
GNDO
Table Signal Description
Signal Name VCCA VCCD VCCO GNDA GNDD GNDO VINI, VINIB VINQ, VINQB CLK, CLKB CLKO, CLKOB DOAI0:DOAI5 DOAI0N:DOAI5N DOBI0:DOBI5 DOBI0N:DOBI5N DOAQ0:DOAQ5 DOAQ0N:DOAQ5N DOBQ0:DOBQ5 DOBQ0N:DOBQ5N DOIR, DOIRN Function Positive analog power supply Positive digital power supply Positive output power supply Analog Ground Digital Ground Output Ground Differential analog inputs Differential analog inputs Differential clock inputs Differential clock outputs Differential output data port Channel Differential output data port Channel Combined output range data Direction
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Table Digital Output Coding
Differential Single Analog Input +406 +406 +393 +206 +193 +6.25 -6.25 -206 -193 -393 -406 <-406 Voltage Level Positive full scale Positive full scale Positive full scale Positive scale Positive scale Bipolar zero Bipolar zero Negative scale Negative scale Negative full scale Negative full scale Negative full scale Digital Output Binary 111111 111111 111111 110000 101111 100000 011111 010000 001111 000000 000000 000000 Range
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Figure AT76C610 Simplified Block Diagram
Buffer Divider
0.62 VCCA ohms VINI VINIB ohms 0.62 VCCA
CLK, CLKB CLKO, CLKOB
6-bit
ohms VINQ
INQB
LVDS Buffer
0.62 VCCA
0.62 VCCA
ohms
6-bit
DOAI, DOAIN DOBI, DOBIN DOAQ, DOAQN DOBQ, DOBQN
DOIR, DOIRN
Functional Description
AT76C610 dual 6-bit, Gsps based advanced high-speed bipolar technology featuring cutoff frequency GHz. Each 6-bit Flash-like core architecture. output data followed multiplexer LVDS output buffer (100 common over-range combiner provided external gain control adjustment. AT76C610 works fully differential mode from analog inputs digital outputs. AT76C610 features full-power input bandwidth MHz.
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Application Scenario
Figure shows AT76C610 integrated into typical application scenario digital signal reception demodulation.
Figure Functional Application (Typical)
Satellite Noise Converter Bandpass Amplifier Parabolic Antenna 11.12 Synthesizer Bandpass Amplifier Pass Filter Tunable Band Filter Band Filter
Local Oscillator
Control Functions: Clock Carrier Recovery, Gain Adjustment. CLOCK Digital AT76C610 Analog
In-phase Local Oscillator
Quadrature
DEMODULATION
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Electrical Characteristics
Table Absolute Maximum Ratings
Symbol VCCA VCCD Vcco DVCCA VCCO DVCCA VCCD DVCCD VCCO VINI VINIB VINQ VINQB VCLK VCLKB VCLK VCLKB Parameter Analog Positive Supply Voltage Digital Positive Supply Voltage Output Supply Voltage Maximum Difference between VCCA VCCO Maximum Difference between VCCA Maximum Difference between VCCD VCCO Analog Input Voltages Digital Input Voltage Digital Output Voltage Clock Input Voltage Maximum Difference between VCLK VCLKB Maximum Junction Temperature Storage Temperature Lead Temperature (Soldering Value +1/-1 -0.3 VCCD +0.3 -0.3 VCCD +145 +150 +300 Unit Comments
TSTG TLEADS Notes:
Absolute maximum ratings limiting values (referenced 0V), applied individually, while other parameters within specified operating conditions. Long exposure maximum rating effect device reliability. thermal heat sink mandatory. Limiting values given accordance with Absolute Maximum Rating System (IEC 134). These stress ratings only operation device these other conditions above those given Electrical Characteristics sections specification implied. Exposure limiting values extended periods effect device reliability.
Table Recommended Conditions
Symbol VCCA VCCD VCCO VINI VINIB VINQ VINQB VCLK VCLKB Parameter Analog Supply Voltage Digital Supply Voltage Output Supply Voltage Differential Single Analog Input Voltage (Full Scale) Clock Input Level Differential Operating Temperature Range 2.25 Unit mVPP mVPP Comments Civil: grade
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Operating Characteristics
following conditions apply electrical operating characteristics given Table test levels given Table 3.3V, 3.3V, 2.25V, VINI VINIB VINQB mVPP Full Scale Differential Input (Digital outputs LVDS 100) (typical) 25°C. Full Temperature Range: 70°C Table Electrical Operating Characteristics
Symbol Parameter Temp Test Level Unit
Power Requirements VCCA VCCD VCCO ICCA ICCD ICCO PSRR Power Supply Voltage Analog Power Supply Voltage Digital Power Supply Voltage Output Digital (LVDS) Supply Current Analog Supply Current Digital Supply Current Output Nominal Power Dissipation Power Supply Rejection Ratio Resolution Analog Inputs VINI VINQ Full Scale Input Voltage Range (Differential Mode) 0.62 VCCA Common Mode Voltage Full Scale Input Voltage Range (Single Mode) 0.62 VCCA Common Mode Voltage Analog Input Capacitance Input Bias Current Input Resistance Full-power Input Bandwidth Small Signal Input Bandwidth (10% Full Scale) 2.25 mV/V bits
VINIB INQB FPBW SSBW Clock Input
Logic Compatibility Clock Inputs PECL (VCLK VCLKB) Logic Voltage PECL (VCLK VCLKB) Logic Voltage PECL (VCLK VCLKB) Logic Current PECL (VCLK VCLKB) Logic Current Power Level into Termination Clock Input Power Level Clock Input Capacitance
PECL into
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Table Electrical Operating Characteristics (Continued)
Symbol Digital Outputs LVDS with differential input mode; clock duty cycle (CLK, CLKB); VCCO 2.25V, VCCD 3.3V. (typical) 25°C. Full temperature range: 70°C. Logic Compatibility Digital Outputs (Depending Value VCCO Differential Output Voltages Swings (Assuming VCCO 2.25V 3.3V) Output Levels (Assuming VCCO 2.25V VCCD 3.3V) Differentially Terminated Logic Voltage Logic Voltage Output Offset Voltage (Assuming VCCO 2.5V VCCD 3.3V) Differentially Terminated Output Impedance Change between Change between Output Current (Shorted Output) Output Current (Grounded Output) Output Level Drift with Temperature Accuracy Single-ended clock duty cycle (CLK, CLKB); binary output data format. (typical) 70°C. Full temperature range: 70°C. Differential Non-linearity Integral Non-linearity Missing Codes Gain Error (Single Channel Input Offset Voltage (Single Channel Gain Error Drift Offset Error Drift Input Offset Matching Channel (Static) Gain Matching Channel (Static) Transient Performance Error Rate Gsps, Settling Time Channel VINI VINIB mVPP 1E-9 1E-10 Error/ Sample 0.25 0.25 Allowed mV/°C 25°C Full LVDS Parameter Temp Test Level Unit
25°C
0.925 1125 1200 1.475 1275
Guaranteed over specified temperature range 0.25 ppm/°C ppm/°C
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Table Electrical Operating Characteristics (Continued)
Symbol Parameter Overvoltage Recovery Time Temp Test Level Unit
Performance Differential input clock mode; clock duty cycle (CLK, CLKB); binary output data format, 25°C, unless specified. Signal-to-noise Distortion Ratio SINAD Gsps, Gsps, Effective Number Bits ENOB Gsps, Gsps, Total Harmonic Distortion Gsps, Gsps, Spurious Free Dynamic Range SFDR Gsps, Gsps, Two-tone Inter-modulation Distortion (Single Channel) FIN1 MHz, FIN2 Gsps Gain Flatness: 0.5db Phase Matching (Channel MHz, Crosstalk Channel versus Channel MHz, 5.65 5.65 bits bits
Switching Performance Characteristics Timing Diagrams Jitter Maximum Clock Frequency Minimum Clock Frequency Minimum Clock Pulse Width (High) Minimum Clock Pulse Width (Low) Aperture Delay Aperture Uncertainty Data Output Delay Output Skew TR/TF Output Rise/Fall Time Data Ready (20% 80%) Data Pipeline Delay Sampling Delay 0.500 0.500 +250 Gsps Msps ps(rms) clock cycles
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Timing Diagram
Data Data Analog Input Input Data phase Data Data Data Data Data
Data phase
Data
Data
Data
Test Levels
Table Test Levels
Note:
Only minimum maximum values guaranteed (typical values issued from characterization results).
100% wafer tested +25°C(1) 100% production tested +25°C(1) (for packaged device) 100% production tested +25°C(1) sample tested specified temperatures Sample tested only specified temperatures Parameter guaranteed design characterization testing (thermal steady-state conditions specified temperature) Parameter typical value only 100% production tested over specified temperature range Unless otherwise specified, tests pulsed tests, therefore, where junctions, case ambient temperature, respectively.
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Packaging Information
Figure 80-lead TQFP Pinout
DOBQ1N
DOAQ0N
DOBQ0N
DOBI0N
DOAI0N
DOBI1N
DOBQ1
DOAQ0
DOBQ0
DOBIO
DOIRN
DOAI0
DOBI1
GNDO
GNDD
VCCO
VCCD
CLKB
DOIR
DOAQ1 DOAQ1N DOBQ2 DOBQ2N DOAQ2 DOAQ2N DOBQ3 DOBQ3N GNDO VCCO DOAQ3 DOAQ3N DOBQ4 DOBQ4N DOAQ4 DOAQ4N DOBQ5 DOBQ5N DOAQ5 DOAQ5N
DOAI1 DOAI1N DOBI2 DOBI2N DOAI2 DOAI2N DOBI3 DOBI3N GNDO VCCO DOAI3 DOAI3N DOBI4 DOBI4N DOIA4 DOIA4N DOBI5 DOBI5N DOAI5 DOAI5N
AT76C610 80-lead TQFP
CLKO
VCCA
VCCD
VCCD
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CLKOB
VCCA
GNDA
VINQB
GNDA
GNDA
VINIB
GNDA
VCCD
VCCD
VINQ
VINI
GNDD
GNDD
GNDD
GNDD
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80-lead TQFP Description
Table AT76C610 80-lead TQFP Description
Symbol GNDA, GNDD, GNDO VCCA VCCD VCCO VINI VINIB VINQ VINQB CLKB DOAI0:DOAI5 DOAI0N:DOAI5N DOBI0:DOBI5 DOBI0N:DOBI5N DOAQ0:DOAQ5 DOAQ0N:DOAQ5N DOBQ0:DOBQ5 DOBQ0N:DOBQ5N DOIR DOIRN CLKO CLKOB Number Function Ground pins. connected external ground plane. Digital positive supply: typ. +3.3V digital supply +2.5V output supply In-phase analog input signal sample hold differential preamplifier channel Inverted phase analog input signal INI) In-phase analog input signal sample hold differential preamplifier channel Inverted phase analog input signal INQ) In-phase PECL clock input signal. analog input sampled held rising edge signal. Inverted phase PECL clock input signal (CLK) In-phase digital outputs first phase de-multiplexer DOAI0 LSB. D0AI5 MSB. Channel In-phase digital outputs first phase de-multiplexer DOAI0N LSB. D0AI5N MSB. Channel In-phase digital outputs second phase de-multiplexer DOBI0 LSB. D0BI5 MSB. Channel In-phase digital outputs second phase de-multiplexer DOBI0N LSB. D0BI5N MSB. Channel In-phase digital outputs first phase de-multiplexer DOAI0 LSB. D0AI5 MSB. Channel In-phase digital outputs first phase de-multiplexer DOAI0N LSB. D0AI5N MSB. Channel In-phase digital outputs second phase de-multiplexer DOBQ0 LSB. D0BQ5 MSB. Channel In-phase digital outputs second phase de-multiplexer DOBQ0N LSB. D0BQ5N MSB. Channel Combined in-phase out-of-range first phase de-multiplexer. out-of-range high leading edge code code Combined in-phase out-of-range first phase de-multiplexer Output clock in-phase (+),1/2 input clock frequency Output clock in-phase (-),1/2 input clock frequency
Thermal Characteristics
Table 80-lead TQFP Package Thermal Characteristics
Package Type 80-lead TQFP (°C/W) 39.0
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Definition Terms
Table Definition Terms
Error Rate Full-power Input Bandwidth Probability exceeding specified error threshold sample. error code code that differs more than LSBs from correct code. Analog input frequency which fundamental component digitally reconstructed output fallen with respect frequency value (determined analysis) input full scale. Ratio expressed signal amplitude, below full scale, other spectral components, including harmonics except Ratio expressed signal amplitude, below full scale, other spectral components excluding five first harmonics. Ratio expressed first five harmonic components, value measured fundamental spectral component. Ratio expressed signal amplitude, below full scale, value next highest spectral component (peak spurious spectral component). SFDR parameter selecting converter used frequency domain application (radar systems, digital receiver, network analyzer.). reported (i.e., degrades signal levels lowered), dBFS (i.e., always related back converter full scale).
SINAD SFDR
Signal-to-noise Distortion Ratio Signal-to-noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range
ENOB
Effective Number Bits
SINAD 1.76 A/V/2 -6.02
where actual input amplitude full scale range under test.
Differential Non-linearity
differential non-linearity output code difference between measured step size code ideal step size. expressed LSBs. maximum value (i). error specification less than guarantees that there missing output codes that transfer function monotonic. integral non-linearity output code difference between measured input voltage which transition occurs ideal value this transition. expressed LSBs, maximum value |INL (i)|. peak gain variation percent) five different levels signal full scale peak-to-peak amplitude. MHz. (TBC) Peak phase variation degrees) five different levels signal full scale peak-to-peak amplitude. MHz. (TBC) Delay between rising edge differential clock inputs (CLK, CLKB) (zero crossing point), time which (VIN VINB) sampled. Sample-to-sample variation aperture delay. voltage error jitter depends slew rate signal sampling point. Time delay achieve 0.2% accuracy converter output when full scale step function applied differential analog input. Time recover 0.2% accuracy output, after 150% full scale step applied input reduced midscale. Delay from falling edge differential clock inputs (CLK, CLKB) (zero crossing point) next point change differential output data (zero crossing) with specified load.
Integral Non-linearity
JITTER
Differential Gain Differential Phase Aperture Delay Aperture Uncertainty Settling Time Overvoltage Recovery Time Digital Data Output Delay
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Table Definition Terms (Continued)
Time Delay from Data Data Ready Time Delay from Data Ready Data Encoding Clock Period Pipeline delay Time delay from Data transition Data Ready. General expression with encoding clock period. Minimum clock pulse width (high) Minimum clock pulse width (low) Number clock cycles between sampling edge input data associated output data being made available (not taking account TOD). TS8388BF, clock periods. Delay between falling edge Data Ready output asynchronous Reset signal (DDRB) reset digital zero transition Data Ready output signal (DR). Time delay output DATA signals rise from delta between level high level. Time delay output DATA signals fall from delta between level high level. Ratio input offset variation change power supply voltage. When input signal larger than upper bound input range, output code identical maximum code Range logic "1". When input signal smaller than lower bound input range, output code identical minimum code, Range logic "1". assumed that input signal amplitude remains within absolute maximum ratings.) two-tone intermodulation distortion (IMD) rejection ratio either input tone worst third order intermodulation products. input tone levels full scale. measured characterize performance response broad bandwidth signals. When using notch-filtered broadband white-noise generator input under test, noise power ratio defined ratio average out-of-notch average in-notch power spectral density magnitudes spectrum output sample test.
TRDR
Data Ready Reset Delay
PSRR
Rise Time Fall Time Power Supply Rejection Ratio Non-return Zero
Inter-modulation Distortion
Noise Power Ratio
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Ordering Information
Prefix Device 76C610 Suffix
Manufacturer Prefix: Product Family 76C6xx Broadband DataComm 76C61x Broadband DataComm 76C62x Broadband DataComm Prototype Version Temperature Range: (-40 Package: TQFP Speed Gsps
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Dual 6-bit Gsps Converter AT76C610 Preliminary Applications

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