Fast Read Access Time Power CMOS Operation Maximum Standby Maximum Act

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Fast Read Access Time Power CMOS Operation Maximum Standby Maximum Act

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AT27C4096
Fast Read Access Time Power CMOS Operation Maximum Standby Maximum Active JEDEC Standard Packages 40-Lead PDIP 44-Lead PLCC 40-Lead TSOP Direct Upgrade from 512K bit, bit, (AT27C516, AT27C1024, AT27C2048) EPROMs Power Supply High Reliability CMOS Technology 2,000V Protection Latchup Immunity RapidProgramming Algorithm µs/word (typical) CMOS Compatible Inputs Outputs Integrated Product Identification Code Commercial Industrial Temperature Ranges
Megabit (256K CMOS EPROM
Description
AT27C4096 low-power, high performance 4,194,304 one-time programmable read only memory (OTP EPROM) organized 256K bits. requires single power supply normal read mode operation. word accessed less than eliminating need speed-reducing WAIT states. by-16 organization makes this part ideal high-performance microprocessor systems. (continued)
Configurations
Name Function Addresses Outputs Chip Enable Output Enable Connect
PDIP View
AT27C4096
Note: Both pins must connected. PLCC View
TSOP View Type
Note:
PLCC pkg. pins DON'T CONNECT.
0311D
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Description (Continued)
read mode, AT27C4096 typically consumes Standby mode supply current typically less than AT27C4096 available industry standard JEDEC-approved one-time programmable (OTP) plastic PDIP, PLCC, TSOP packages. device features two-line control (CE, eliminate contention high-speed systems. With high density 256K word storage capability, AT27C4096 allows firmware stored reliably accessed system without delays mass storage media. Atmel's AT27C4096 additional features that ensure high quality efficient production use. RapidProgramming Algorithm reduces time required program part guarantees reliable programming. Programming time typically only µs/word. Integrated Product Identification Code electronically identifies device manufacturer. This feature used industry standard programming equipment select proper programming algorithms voltages.
System Considerations
Switching between active standby conditions Chip Enable produce transient voltage excursions. Unless accommodated system design, these transients exceed data sheet limits, resulting device non-conformance. minimum, high frequency, inherent inductance, ceramic capacitor should utilized each device. This capacitor should connected between Ground terminals device, close device possible. Additionally, stabilize supply voltage level printed circuit boards with large EPROM arrays, bulk electrolytic capacitor should utilized, again connected between Ground terminals. This capacitor should positioned close possible point where power supply connected array.
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AT27C4096
AT27C4096
Block Diagram Absolute Maximum Ratings*
Temperature Under Bias -55°C +125°C Storage Temperature. -65°C +150°C Voltage with Respect Ground. -2.0V +7.0V Voltage with Respect Ground -2.0V +14.0V Supply Voltage with Respect Ground. -2.0V +14.0V
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Note: Minimum voltage -0.6V which undershoot -2.0V pulses less than Maximum output voltage 0.75V which overshoot +7.0V pulses less than
Operating Modes
Mode Read Output Disable Standby Rapid Program Verify Inhibit Product Identification
Outputs DOUT High High DOUT High Identification Code
Notes: VIH. Refer Programming characteristics. 12.0 0.5V.
identifier words selected. inputs held (VIL), except which which toggled (VIL) select Manufacturer's Identification word high (VIH) select Device Code word. Standby current (ISB) specified with VCC. will cause slight increase ISB.
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Operating Conditions Read Operation
AT27C4096 Operating Temperature (Case) Power Supply Com. Ind. 70°C -40°C 85°C 70°C -40°C 85°C 70°C -40°C 85°C 70°C -40°C 85°C
Operating Characteristics Read Operation
Symbol IPP1
Parameter Input Load Current Output Leakage Current
Condition VOUT ISB1 (CMOS) 0.3V ISB2 (TTL) 0.5V
Units
Read/Standby Current
Standby Current
Active Current Input Voltage Input High Voltage Output Voltage Output High Voltage
MHz,IOUT -0.6 -400
Notes: must applied simultaneously before VPP, removed simultaneously after VPP.
connected directly VCC, except during programming. supply current would then IPP.
Characteristics Read Operation
AT27C4096 Symbol tACC
Parameter
Address Output Delay Output Delay Output Delay
Condition
Units
Notes:
High Output Float, whichever occurred first Output Hold from Address, whichever occurred first
Waveforms Read Operation diagram.
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AT27C4096
AT27C4096
Waveforms Read Operation
Notes: Timing measurement references 0.8V 2.0V. Input drive levels 0.45V 2.4V, unless otherwise specified. delayed after falling edge without impact tCE.
delayed tACC after address valid without impact tACC. This parameter only sampled 100% tested. Output float defined point when data longer driven.
Input Test Waveforms Measurement Levels
Output Test Load
(10% 90%)
Note: including capacitance.
Capacitance 25°C)
COUT
Note:
Units
Conditions VOUT
Typical values nominal supply voltage. This parameter only sampled 100% tested.
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Programming Waveforms
Notes: Input Timing Reference 0.8V 2.0V VIH. tDFP characteristics device must accommodated programmer.
When programming AT27C4096, capacitor required across ground suppress spurious voltage transients.
Programming Characteristics
5°C, 0.25V, 13.0 0.25V Limits Symbol Parameter Input Load Current Input Level Input High Level Output Voltage Output High Voltage Supply Current (Program Verify) Supply Current Product Identification Voltage 11.5 -400 12.5 Test Conditions VIL, -0.6
Units
ICC2 IPP2
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AT27C4096
AT27C4096
Programming Characteristics
5°C, 0.25V, 13.0 0.25V Sym- Parameter Test Conditions*
Rapid Programming Algorithm
pulse width used program. address first location. raised 6.5V raised 13.0V. Each address first programmed with pulse without verification. Then verification/reprogramming loop executed each address. event word fails pass verification, successive pulses applied with verification after each pulse. word fails verify after pulses have been applied, part considered failed. After word verifies properly, next address selected until have been checked. then lowered 5.0V 5.0V. words read again compared with original data determine device passes fails.
Limits
Units
tDFP tVPS tVCS tPRT
Address Setup Time
tOES Setup Time
Data Setup Time Address Hold Time Data Hold Time High Output Float Delay Setup Time Setup Time Program Pulse Width Data Valid from Pulse Rise Time During Programming
47.5
52.5
Conditions Test: Input Rise Fall Times (10% 90%) Input Pulse Levels.0.45V 2.4V Input Timing Reference Level. 0.8V 2.0V Output Timing Reference Level.0.8V 2.0V Notes: must applied simultaneously before removed simultaneously after VPP. This parameter only sampled 100% tested. Ouput Float defined point where data longer driven timing diagram. Program Pulse width tolerance µsec
Atmel's 27C4096 Integrated Product Identification Code
Pins Codes Manufacturer Device Type
015-08
Data
001E 00F4
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Ordering Information
tACC (ns) (mA)
Active Standby
Ordering Code AT27C4096-85JC AT27C4096-85PC AT27C4096-85VC AT27C4096-85JI AT27C4096-85PI AT27C4096-85VI AT27C4096-10JC AT27C4096-10PC AT27C4096-10VC AT27C4096-10JI AT27C4096-10PI AT27C4096-10VI AT27C4096-12JC AT27C4096-12PC AT27C4096-12VC AT27C4096-12JI AT27C4096-12PI AT27C4096-12VI AT27C4096-15JC AT27C4096-15PC AT27C4096-15VC AT27C4096-15JI AT27C4096-15PI AT27C4096-15VI
Package 40P6 40P6 40P6 40P6 40P6 40P6 40P6 40P6
Operation Range Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C)
Package Type
40P6
Lead, Plastic J-Leaded Chip Carrier (PLCC) Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Lead, Plastic Thin Small Outline Package (TSOP)
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AT27C4096

Fast Read Access Time Power CMOS Operation Maximum Standby Maximum Act

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