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DATA ACQUISITION SEMINAR
Applications Seminar Agenda Section
Introduction Welcome Introduction Analog-to-Digital Converters Analog-to-Digital Converter Topologies Measurement, Testing Troubleshooting Digital-to-Analog Converters
Board System Design
Concluding Remarks
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Basic Rules High Performance, Mixed Signal Layout
Separate analog digital circuits segment
functionality speed
Distribute power supply grounds taking care
minimize loop area return current paths
Isolate noisy return current paths from more sensitive
analog circuits
Minimize interference from clocks Decouple power supply pins Minimize emissions
Very high fidelity signal paths must isolated from noisy influences. Unfortunately, compromised layouts often required support interaction between mixed signal components satisfy routing requirements multiple clocks. Additionally, digital analog components share common points connection like power supplies, grounds interfaces. first step solving these issues physical separation components, separating circuit blocks function speed. Splitting ground into separate analog digital grounds best guarantee that noisy digital currents will flow analog area.
During prototype phase, allow possibility several points connection between ground planes then experiment determine which point connection optimal. production board, connect grounds using substantial pieces copper ensure good ground connection frequencies (better than jumper wire). Remember investigate routing signal power lines, including circuit board traces, wire harnesses, cables connectors. Good layout techniques will also reduce emissions limit susceptibility emissions.
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Design Construction Affect Overall Performance
Subsystems circuits interact with each other Operating conditions change Outside events disrupt operation Good design techniques required optimum
performance
Good design techniques will also reduce emissions
limit susceptibility
ADCs often used applications detecting measuring low-level signals. When analog circuits integrated into system, undesirable electric magnetic energy induced upon sensitive signals. This unwanted energy adds noise causes distortion. result decrease accuracy. Noise sources inside external system. With internal noise sources, design affect system's emissions susceptibility. With external sources, design only affect system's susceptibility.
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Noise Management Techniques
Noise Source
Methods Noise Coupling
Coupling Channel
Receptor
Common Impedance Common Ground Impedance Electric Field Capacitive Coupling Magnetic Field Inductive Coupling Electromagnetic Radiation Radio Frequency Interference (RFI)
noise problem exist, there noise source, coupling channel receptor. three areas must addressed solve noise problems. methods noise coupling classified according channel transmission. system design must incorporate proper combination shielding, signal routing, physical layout.
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Common Impedance
Circuit
Circuit
Ground Current
Ground Common Current Ground Impedance
ground voltage each circuit affected ground current other circuit Use:
Good Ground Planes Star Power Distribution
Common impedance situation were current from circuit flows through impedance shared another circuit, producing noise second circuit. Thus fluctuations caused source circuit channeled through common resistor coupled receptor circuit. most common causes common impedance noise involves distribution power. This happens when several circuits same power supply return, when several loads connected parallel. When dealing with common impedance noise, designer must concerned with routing scheme relates power distribution impedance. power ground planes technique minimize common impedance problems.
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Single-Point Grounds
Daisy Chain
Susceptible common
Star
Controls common
impedance coupling
Simplifies routing
impedance problems
Single point grounds used eliminate ground loops. Implementation single point ground scheme affects common impedance noise. basic types single point grounding schemes "Daisy Chain" "Star" topologies. daisy chain topology susceptible common impedance noise. When circuit switches large load, change current affect circuits single point ground connected star topology used control common impedance problems. this case separate return line routed from ground each circuit. When circuit switches large load, change current does affect circuits Power should distributed manner that parallels ground structure. This includes positive well negative power supplies. sound power distribution scheme requires more wire implement, result better performance.
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Electric Field
(Culprit)
(Victim)
(Culprit) (Victim)
culprit signal capacitively coupled victim
Electric field noise caused coupling noise parasitic capacitance, This capacitance exists between wires, cables, circuit board traces. Notice that circuits need physically connected energy electrically coupled.
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Reducing Effects Capacitive Coupling
Reduce capacitance
Separate conductors Shorten trace lengths
Reduce victim impedance Reduce culprit signal's dv/dt Faraday shields
effects capacitive coupling minimized source, channel, receptor. magnitude noise function strength electric field, frequency variation, victim impedance coupling capacitance. effect coupling channel reduced lowering coupling capacitance. This accomplished increasing physical separation conductors including cables, harnesses, wires, circuit board traces. capacitance between conductors inversely proportional distance between them. keep conductors that like noise sources, such clock signals away from receptors. helpful highlight digital clock conductors sensitive analog input signals with different colors when reviewing circuit board layout. Also careful placement critical signals connectors cables which contain variety signal types. best route sensitive signals noisy signals separately, with their connector their cable.
Reducing length traces reduces effects distributed capacitance. important investigate possibility reducing culprit noise source dv/dt. couple suggestions include selective choice digital logic family, clock frequencies when possible, control turn-on turn-off loads. Lowering victim impedance will help improve circuit's immunity capacitively coupled noise. Certain logic families terminating resistors will improve performance. Faraday shields used shield electronics from electric fields. shield affective, must have impedance path ground some other reference potential. result coupling capacitance virtually eliminated. There still small amount coupling capacitance imperfections shield.
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Magnetic Field
(Culprit)
(Victim)
(Culprit) (Victim)
culprit signal inductively coupled mutual inductance, victim
Magnetic field noise caused coupling noise mutual inductance, This inductance exists between wires, cables, circuit board traces. Notice that circuits need physically connected energy magnetically coupled. changing magnetic field will induce voltage circuit that field.
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Reducing Effects Inductive Coupling
Reduce inductance
Reduce loop area culprit victim Shorten trace lengths
ground planes trace fill Reduce culprit signal's di/dt Mu-metal shields
effects inductive coupling minimized manner similar capacitive coupling. goal minimize magnetic fields with respect source, channel, receptor. magnitude noise function strength magnetic field, frequency variation, culprit impedance loop area. effect coupling channel reduced lowering mutual inductance. This accomplished reducing loop area culprit victim circuits shortening trace lengths. larger loop area encompasses more magnetic flux than small loop area. Using power ground planes along with trace fill signal layers will reduce loop area culprit victim circuits. strength magnetic field reduced physically separating source from receiving loop. with capacitively coupled noise, investigate sensitive analog signals noisy digital signals routed printed circuit boards. Carefully examine complete
signal path manage return signal paths critical signals. Take advantage physical separation when ever possible. Make twisted pair wires when routing signals constructing cables harnesses. Magnetic fields created changing currents conductors. strength magnetic field reduced limiting di/dt. This accomplished controlling switching currents increasing impedance culprit loop. Using shields prevent inductive coupling difficult because magnetic fields penetrate conductive shields. metal shields should used frequencies (<10 kHz). important note that frequencies, absorption loss primary shielding mechanism magnetic fields. careful saturate shield which results reduction permeability. Check curve shielding material.
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Electromagnetic Radiation
Electromagnetic waves have both electric
magnetic field components
Electric field Antenna
Magnetic field
electromagnetic wave made combination both electric magnetic fields. When voltage applied antenna, electric field set-up. same time, this voltage will cause current flow antenna. current flow produces magnetic field. case electromagnetic radiation, culprit victim physically located apart, least one-sixth wave length electromagnetic wave. energy transferred plane-wave propagation.
Signal Wave Length One-sixth Wave Length
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Reducing Effects Electromagnetic Radiation
shielding keep radiated electromagnetic energy
from leaving specific region
shielding keep radiated electromagnetic energy
from entering specific region
Reduce receiving emitting mechanisms
High E-field from dipole H-field from loop area
power ground planes along with trace fill
signal layers
Shielding used reduce effects electromagnetic radiation. shields either used keep radiated electromagnetic energy from leaving specific region entering specific region. Work also done area reducing receiving emitting mechanisms. This includes reducing electric field emitted from dipole magnetic field emitted from loop area. Power ground planes valuable reducing effect electromagnetic radiation. planes serve purposes. first purpose reduction emitting receiving mechanisms. planes reduce effective antenna culprit victim circuits. second purposes plane that shield. Power ground planes create Faraday shield circuit board.
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Example Layout Surround Sound Processor
System requirements:
channel Digital-to-Analog Converter Digitally controllable volume control channel Analog-to-Digital Converter Microcontroller Clocks derived from digital audio input on-board oscillator Single
Maximum analog performance Minimized emissions susceptibility
examine layout example where Analogto-Digital Converters (ADCs) Digital-toAnalog Converters (DACs) with programmable gain controls located circuit board with microcontroller well clock management circuitry. Surround Sound processor would require channels Digitalto-Analog conversion, digitally controlled volume control, channels Analog-to-Digital conversion, Digital Signal Processor (DSP), microcontroller, fairly complex clock management system. clock management system would have generate master clocks converters, high-speed clocks DSP, clock microcontroller. various clocks derived routed will affect system performance.
This system will constructed single circuit card. Combining multiple functions circuit card degrade performance. minimum analog performance greater than signal noise ratio. product's electromagnetic emissions susceptibility must minimized. good design techniques will achieving objective.
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Step System Architecture
Arrange components functional blocks minimize interaction
Low-Speed Logic Low-Frequency Clock Medium-Speed Logic Medium-Speed Frequency High-Speed Logic High-Frequency Clock Connector Frequency Circuits Medium Frequency Circuits High Frequency Circuits
Interface Circuits Connector
DIGITAL ONLY LAYOUT
ANALOG ONLY LAYOUT
Analog Circuits
Logic Circuits
Analog
Analog Circuits
Analog Digital Interface System Clocks
Frequency Logic
High Frequency Logic
Analog Interface
Logic Interface
Connector
Connector
MIXED SIGNAL LAYOUT
first step determine functional blocks system arrange those blocks that interaction between potentially noisy circuit blocks sensitive analog circuits minimized. Logic circuits should grouped board accordance with speed which logic operates. Keep high-frequency logic close together segregated area board, preferably close connector that highfrequency trace lengths minimized. Short trace lengths reduce amount distributed capacitance mutual inductance between signal routes. Low-frequency logic placed further away board longer trace lengths acceptable. Similarly, analog circuits should grouped separated according frequency, minimizing length high-frequency signal paths.
Mixed signal boards follow much same rules, isolating high frequency from frequency, digital from analog much possible. Minimize length high-frequency traces. interface between analog digital circuits should carefully laid minimize interaction.
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Step System Architecture
Separate circuits speed function
Interface Micro Controller Analog Digital Conversion Input Buffers Digital Analog Conversion Clock Management Control Volume Control Digital Audio Receiver Transmitter Power Supply Regulation Digital Audio Input/Output
Analog Input/Output
system architecture board places analog side board digital other with analog corner which opposite microcontroller. clock management power supply regulation centrally located that supplies clocks distributed with minimal length traces, ground return paths minimized. Notice that high speed digital signals associated with function located corner opposite more sensitive analog input output. Power supply regulation centrally located minimize return paths common impedance noise.
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Step Split analog digital grounds
Interface Ground Plane Split
Digital Ground
Micro Controller Clock Management Control Digital Audio Receiver Transmitter Power Supply Regulation Digital Audio Input/Output
Analog Digital Conversion Input Buffers
Digital Analog Conversion Volume Control
Analog Ground
Analog Input/Output
multi-layer boards, power plane should match ground plane
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Step Split analog digital grounds
only ensure that interaction between analog digital signals will minimized isolate circuit areas separate analog digital ground planes. analog plane will contain only analog circuits digital plane only digital circuits. ground planes should never overlap another. multi-layer board with power ground planes optimal, always practical layer board, ground plane area should maximized both sides board. This accomplished using trace fill signal side printed circuit board. Trace fill involves filling open area between signal traces with copper connecting this "mini-plane" ground. Examine Crystal Semiconductor evaluation boards, such CDB5390, examples using trace fill (page 3-185 1994 Audio data book). Ground planes trace fill significantly reduce coupling. Power planes designed using same rules ground planes. power planes used, never bridge split between analog digital ground. Keep analog supply plane entirely under (over) analog ground plane. Whether circuit board layer more, general rule that analog digital ground planes should separated least (1/8"). between ground planes intended minimize distributed capacitance point where interaction between ground planes minimal. This capacitance based length ground plane well separation. small boards where distance ground plane split small, width reduced. some place circuit, analog digital grounds must tied together establish
common voltage digital interface between analog digital circuits. Proper selection this connection point crucial maximizing system performance. must attempt keep digital return currents that flow back regulator from passing through analog circuits, vise-versa. this case centralized location power supply regulation beneficial: power supply return currents have direct path back regulators. most layouts best point analog digital grounds together never completely clear. prototyping stage, pick numerous locations likely candidates ground plane tie. Then experiment determine which location maximizes analog performance, that point ground tie. Ideally second pass layout board will allow ground permanently etched into circuit board. nice wide ground provides good connection between grounds frequencies. inductance thin wire jumper will limit effectiveness high frequencies, could possibly cause shift ground potential between planes.
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Grounds Mixed Signal Boards
ground planes wherever possible. This
includes ground plane fill both analog digital areas
Ground planes trace fill significantly
reduce coupling
Ground split should (1/8") multilayer boards analog digital
grounds should never overlap
cautious ground loops
Investigate grounding scheme current return paths entire system. cautious ground loops. Ground loops occur when return current more than possible path return power supply.
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Grounds Mixed Signal Boards
Wisely choose best point connect analog
digital grounds
Connect grounds only point Experimentation necessary best results Allow several options prototypes possible "bridge" where digital interface signals cross split Near power supply distribution
Options single point ground are:
Tying board ground chassis ground
required reduce emissions
Same qualitative rules apply
analog digital ground planes must referenced another somewhere system. proper location this reference point varies each product application. grounds connected only point. options single point ground "bridge" where digital interface signals cross ground plane split near power supply distribution. example ground plane "bridge" shown latter slide. Design flexibility into your prototype such that location analog digital ground plane reference easily changed best results. Often necessary reference circuit chassis ground order reduce electromagnetic emissions. aware ground loops grounding requirements when connecting system chassis ground. Connecting chassis ground should create ground loop.
physical connection chassis should provide current carrying capacity required application. Investigate chassis connection's resistance inductance.
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Fracture Ground Planes Isolation
Clocks Digital Audio
Digital Control
Analog Return Current Analog Signals
Noisy Return Currents
Divisions ground plane help isolate noisy return currents from noise sensitive areas
Fractures ground planes used further isolation return currents within plane. ground plane fracture direct digital return current away from sensitive analog signals. example, digital interface circuit return current restricted limited path, away from sensitive analog areas located same plane. Similarly, fractures used control current flow between high current current circuit areas, isolate noise from high frequency clocks. There several precautions observe when designing fractures into ground planes. First, many fractures disrupt continuity effectiveness plane. result could higher common impedance larger loop areas. frugal with number plane fractures. Another caution deals with fracture thickness.
fracture which thin will direct frequency current, however high frequency current capacitively coupled over fracture. fracture thickness should least 1/16th inch.
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Step Place Mixed-Signal Components Near Split
Digital Ground Plane Analog Ground Plane
Digital
Place mixed-signal parts analog
ground plane
Digital return currents flow
through analog plane, should small
over ground plane reduces coupling
DGND AGND
Good
Digital Ground Plane Analog Ground Plane AGND
Noisy digital return currents flow
through degrading performance
over ground plane Susceptible Radio Frequency
Interference Electrostatic Discharge
DGND
AGND
Mixed signal parts like Analog-to-Digital Converters (ADCs) Digital-to-Analog Converters (DACs) should located close split minimize excursion digital lines into analog area. placement ICs, helps know supply ground arrangements silicon itself. Crystal Semiconductor's with multiple ground pins, analog digital grounds separate, though they expected same potential. There tradeoffs placing single relative ground plane split. Placing package across ground plane split questionable benefit. thought that having mixed signal chips reside over both analog digital plane improved performance. separate supplies grounds ensure excellent isolation, keeping digital interface return currents analog ground. This provide good performance, however design
susceptible Radio Frequency Interference (RFI) Electrostatic Discharge (ESD) problems. problems very high frequency noise cause problems planes momentarily rises voltage. This voltage rise cause calibration memory corrupted. Placing component entirely over analog ground plane greatly diminished problem. small amount digital return current will flow analog plane, should inconsequential. recommended that mixed signal parts located entirely over analog ground plane. location should edge analog plane next digital ground plane, with digital pins facing digital ground plane. Only small amounts digital return currents should flow through analog plane back digital power supply.
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Isolating Supplies Planes
Preferred Method Isolate with resistor Larger resistance provides more isolation Larger capacitance provides more high-frequency attenuation
From Regulator
power transients warrant larger capacitance Small resistance ferrite high current
From Regulator
Ferrite Bead
Crystal Semiconductor's ICs, there recommended operating conditions which specify power supply voltages. These specifications dictate that must always most positive voltage part. When separately regulated, take care ensure that always comes first never drops below VD+. method ensure that always greater than derive from through resistor ferrite bead capacitor. resistor bead capacitor combination provides pass filter isolate digital switching noise from analog power supply. application will dictate size capacitor, ferrite bead resistor.
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Step Capacitor Decoupling
Decouple power supplies voltage references close supply reference pins ground pins possible -Minimize Loop Area Digital Supply Digital Supply
vias through
ground plane
FILT
vias through
ground plane
FILT
Analog Supply
Analog Supply
additional large filter capacitance parts that have large and/or dynamic current consumption
decoupling capacitor's filter noise power supply pins ground. noise supply either caused coupling dynamics power pins themselves. Bond wire lead, frame trace inductance resistance serve inhibit function capacitor. Sensitive analog pads usually oriented minimize bond wire lead frame lengths that they effectively decoupled. Adequate bypass capacitors between power supply pins ground mandatory. critical connect these capacitors close pins possible. effectiveness capacitor will lost there much resistance inductance series with Usually capacitors recommended each supply pin, small 0.01 ceramic capacitor together with tantalum capacitor. Because small capacitor handles high
frequency transients, needs closer two, while larger afford further away. surface mount board, capacitors should component side such that direct connection made pins without going through vias. Vias resistance inductance connection. Bulk decoupling power supply point where power supply enters board helps stabilize supply voltage. This particularly important current draw demands board dynamic case with digital circuits. Distributed trace inductance power supply leads could cause fluctuations supply voltages board. Consider additional bulk decoupling near component that uses current dynamic way.
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Right Monolithic Ceramic
Good power supply decoupling Inexpensive small size High self-resonant frequency
Decoupling
BUT.
Relative Capacitance
Excellent temperature coefficient Capacitance voltage dependent High self-resonant frequency
-0.1 -0.2 -0.3 -0.4 -0.5
Signal Path
>1%/V, 0-5V
Volts
Temp.
Relative Capacitance
Relative Capacitance
Temp.
Tolerance range
Small values only Expensive
BUT.
type capacitor used affect performance analog circuitry. When choosing capacitor, important understand capacitor's function performance deviates from ideal. Important attributes include size, price, self-resonant frequency, temperature coefficient, voltage coefficient. Temperature voltage coefficient numbers important capacitors used signal path. temperature changes capacitor's value, filter pole move resulting degraded performance. Examine capacitor's value could change over operating temperature application. voltage coefficient required good dynamic performance. voltage changes across capacitor's plates, distance between plates affected. change separation between capacitor plates results change capacitance. amount change described
voltage coefficient. result voltage across capacitor changing capacitance distortion signal. Generally, capacitor that excellent temperature coefficient excellent voltage coefficient.
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Right (cont.)
Equivalent Circuit Model Capacitor
Equivalent series resistance including trace resistance Equivalent series inductance including trace inductance Capacitance Parallel resistance dielectric losses leakage isolation resistance
Self Resonant Frequency Capacitor Make sure capacitor performs well intended application frequency
important consider frequencies capacitor intended handle avoid application capacitor frequencies approaching self resonance. Notice that sampling frequency Analog-to-Digital Converter many times higher than bandwidth signal. audio converter samples times digital word output rate. digital word output rate kHz, analog input signal sampled MHz. self-resonant frequency capacitor increases value capacitance decreases. Film capacitors often used audio designers because they "sound good" available many sizes. sampling rate audio Analog-to-Digital Converter range well beyond self-resonant frequency film caps.
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Step Reduce Interference from Clocks
Synchronize board functions master clock Minimize routing high frequency signals
XTAL 11.2896 CS8412 MCLK Digital Audio XTAL 12.288 System Master Clock
Ideally Turn power unused clocks
Many systems synchronize external clock source this example, digital audio input), need capability function when digital signal present, therefore have crystal oscillators. system have additional requirement operation more than sample rate. Three oscillators simultaneously running could cause horrendous problems high performance analog system. best operate only desired oscillator. unused oscillators should turned reduce noise. some cases more than oscillator must enabled. example, want choose clock source monitoring lock indicator Crystal Semiconductor CS8412. Minimizing trace lengths isolating return currents crucial maintaining high analog performance levels. Take advantage physical separation keeping clock sources close together circuit card.
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High-Speed Clocks Processors
Ideally synchronize clocks
board clock
Some Digital Signal Processors
have internal Phase Locked Loops generate high-speed clock
GREAT FEATURE
CS8412
Clock
49.152
45.1584
Minimize routing
trace length clocks
Master Clock
clocks required digital processing produce noise system. easier handle noise clocks synchronized. Some components such Digital Signal Processors (DSPs) have internal phase lock loops (PLLs). This feature reduces number clocks signal routes required implement application. beneficial have only system master clock. However, this possible, minimize routing trace length clock signals.
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Minimize Routing Clocks
Clocks modulator's frequency should avoided CS4330/1/3, CS5330/1, CS4327/9 modulators operate clocks produce tones audio spectrum should avoided Internal Serial Clock mode creates virtual SCLK
LRCK SCLK SDATA
Left Channel
Right Channel
Simplifies routing Reduces tone susceptibility
aware problems which arise when clock frequencies half frequency modulator's sample frequency. Half modulator sample frequency convenient signal SCLK. This case provides opportunity aliasing high frequency noise into passband. Crystal Semiconductor CS4330/1/3, CS5330/1, CS4327/9 products relieve this problem requiring SCLK. digital interface synchronized with master clock part. Thus SCLK signal required. This reduces package count eliminates clock trace printed circuit board. Less noise generated signal routing simplified.
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Reducing Emissions from Clocks
Ferrite Beads
Resistance Frequency (MHz) 1000
Reduced High-Frequency Current Flow
Ferrite beads reduce high-frequency current flow
Slows down edges Reduces overshoot Reduces emissions
Ferrite beads used reduce noise emissions clock signals. Notice ferrite bead's impedance increase frequency increases. When ferrite beads used with circuit board traces, signal rise fall times increased. This decreases circuit's di/dt dv/dt, resulting reduction noise emissions.
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Reducing Emissions from Clocks
Ground planes trace fill reduce emissions Route high-frequency traces level
Avoid vias Avoid sharp angles
BETTER BEST
Reduce current flow high frequency traces
Resistors series Ferrite Bead alternative
Ground planes trace fill used reduce noise emissions reducing transmitter loop area. manner which circuit traces constructed affect clock emissions. Sharp turns bends create concentrations magnetic fields point bend. bend turn also affect characteristic impedance trace particular point. This results mismatched impedance impedance discontinuities signal trace. Note that circuit board vias harsh ninety degree signal turns. Placing series impedance signal traces reduces noise emissions reducing amount current switched. Recall formula coupling noise magnetic field: di/dt
reducing change current, strength magnetic field reduced, turn reducing amount noise voltage that coupled.
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Step Minimize Excursion Digital Signals into Analog
Place digital interfaces mixed signal parts toward
ground plane split
SDATAIN LRCK SDATA3 SDATA2 SDATA1
DIGITAL
CLOCK MGMT CIRCUIT
GROUND PLANE SPLIT
GROUND PLANE SPLIT
DAC3
DAC2
DAC1
ANALOG
Operate digital signals analog area only when needed
mixed signal components located over analog plane near edge. digital interface signal pins should facing toward digital plane order reduce length signal trace. this example, analog digital ground planes connected location "bridge". digital signals mixed signal components located over analog ground plane routed over "bridge". affect this signal routing have digital return current follow path under signal traces resulting smaller effective loop area. Care taken reduce lengths traces avoid sharp turns bends.
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CS3310 Stereo Volume Control CS3310's innovative interface allows daisy chaining numerous
SDATAI Audio Signal CS3310 SCLK
Controller
AINL AINR
AOUTL SDATAO SDATAI Audio Signal CS3310 SCLK
AOUTR
Control simple three wire interface Communication from microcontroller only needed basis Minimizes microcontroller activity analog circuit area
AINL AINR
AOUTL SDATAO Additional CS3310s
AOUTR
design Crystal Semiconductor CS3310 allows easy implementation multiple volume controls. Multiple CS3310s daisy chained together connecting SDATO device SDATI another. Communications CS3310 simple three wire interface consisting SCLK (serial clock), SDATA (serial data) (chip select). This interface does require multiple chip selects.
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Crystal's Designs Eliminate Noise Sources
Volume Change Occurs Here Instead Here
time-out zero crossing
CS3310 incorporates noise free level transitions changing values zero crossing. This feature eliminates zipper noise when device used volume control.
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Step Analog Optimize Input Buffer Performance
Carbon OP27 100k Carbon Carbon Carbon Metal Film OP27 Metal Film (NPO) Metal Film
GOOD
Resistors large, carbon Wrong dielectric capacitor OP27 distorts non-inverting mode
Resistors small, metal film (NPO) dielectric capacitor OP27 inverting configuration
When designing analog input circuit, careful selection components. Large resistors more noise circuit than small resistors. This effect thermal noise which proportional resistance. Also carbon resistors tend noisier than metal film their structure. careful selection capacitors dielectric material. capacitors with good voltage coefficients with self-resonant frequency less than sample rate. op-amp used non-inverting configuration distort input signal. This change bias current function input signal. non-inverting mode, input op-amp changes signal voltage changes. op-amp bias current constant over different voltage levels. change input bias current requirements causes distortion analog input signal.
same op-amp used inverting configuration better performance. input op-amp constant zero volts. constant input constant bias current. Thus there fluctuations bias current distort signal.
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Input Buffer Circuit CS5330/31
INPUT 100k 7.87k TANT 7.5k 0.01 CS5330/1
Input low-pass filter:
Isolate op-amp from high-speed sampling input Provides anti-aliasing
Input offset approximate bias CS5330/31 provides on-chip high-pass filter
Analog input buffer Crystal Semiconductor CS5330 operates from single five volt supply. input op-amp capacitively coupled output centered around volts. resistor 0.01 capacitor form pass filter with corner frequency well below half sample frequency CS5330/31 modulator.
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Differential Input Buffer Circuit
+15V 7.75k -15V +15V -15V 7.75k +15V 7.75k -15V Op-amps OPA-627 AINR VAVA+ AINR 7.75
Always route differential circuits differentially Schottky diodes protect against overvoltage inputs
differential input circuit above ideal match Crystal Semiconductor CS5389/CS5390 professional audio applications. circuit will accept differential single-ended signal either polarity provide differential signal CS5389/CS5390. circuit also incorporates attenuation required scale professional audio levels input voltage range CS5389/CS5390. nominal input level will achieve full-scale digital code from CS5389/CS5390. common-mode rejection system limited passive component matching input buffer circuit. Resistor-Capacitor (RC) network comprised R10-R11 provide anti-alias filtering optimum source impedance CS5389/CS5390 right channel inputs. Input protection provided D1-D5, D7-D9.
further information refer Application Note AN20, "ADC Input Buffer Protection Techniques."
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Step Chassis Grounds Contain Emissions
low-resistance metal chassis surrounds circuit with Faraday shield that will contain emissions Interface cables with shield connected chassis ground extends chassis' Faraday shield around conductor, thereby containing emissions
Signal Shield Surrounds Conductor GND1 GND2
Caution Connecting shields (and therefore chassis) grounded boxes together will create ground loop Caution GND1 GND2 different potentials current will flow shield, potentially inhibiting circuit performance
Many applications consist more than circuit cards. These boxes connected another with connectors cables. Often these cables constructed extended Faraday shield include boxes cables. This reduces emissions decreases susceptibility electromagnetic radiation. When boxes connected together, careful create ground loop. Ground loops exist when there multiple current return paths ground. This often happens when multiple circuit boards electronic boxes used electronic system. power signal paths need checked ground loops especially cable shields used. symptom ground loop problems when each individual component check separately, however performance degrades when integrated into system.
When unit required pass emissions testing, interconnect cables that connect become antennas that radiate highfrequency energy that present circuit. these cases, chassis must tied circuit ground, cable shields must connect this ground contain emissions. same qualitative rules apply connecting chassis ground board ground when connecting analog digital grounds together. Take care prevent chassis currents from flowing analog digital grounds circuit. make sure that signal paths power routes have only return path. where does current
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Balanced Interfaces
Transformer isolation allows appropriate referencing signals
Ground Lift 100pF Shield 100pF
Source, cable termination impedance should equal Chassis grounding shield transmitter extends Faraday shield around transmitted signal containing General rules Connect shield ground transmitter Capacitively couple shield ground receiver
Ideally, shields connected chassis transmitter capacitively coupled chassis receive end. This method minimized emissions avoids ground loops. There industry standard grounding shields, cannot assured that receive capacitively coupled, tied directly ground. happens that both ends cable's shield tied ground, resulting ground loop prove devastating operation equipment. "Ground Lift" chassis ground provides convenient place break ground loop. Ground Lift jumper that removed disconnect shield from chassis ground. good idea leave small capacitor connected between shield chassis.
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Multiple Board Systems
complete functions unique circuit boards Increase distance between culprit victim
circuits physical separation (signal strength decreases square distance)
Position higher power circuit boards nearest
single point ground minimize common impedance coupling
synchronous clocks when possible twisted pairs other controlled impedance
cabling
Separate high-level low-level signals impedance grounds
Certain problems arise when complete system consists multiple circuit boards. These systems have tendency large, complex, utilize variety electronic components. Problems occur when signals noise coupled areas where they wanted. Some simple design rules used minimize problems improve performance. When designing system architecture, complete functions should placed unique circuit boards. This will reduce routing distance signals provide physical separation between different functions. Another advantage reduction connector size. attention location various circuit boards system. Note where noisy sensitive boards located. Signal strength decrease square distance. this advantage when designing mother board system wire harness placing various circuit boards. minimize common impedance coupling, locate higher power boards nearest single point ground. often easier handle synchronous noise opposed asynchronous noise. amount noise energy will same, however synchronous noise known location
spectrum (probably digital signal processing techniques used filter unwanted noise. master clock system derive other clocks from master clock. When routing signals power between circuit boards twisted pairs other controlled impedance cables. These cables control path current flow reducing loop area circuit. This reduces amount magnetic noise emitted received. High level signals should physically separated. This separation should included circuit boards, harness cable routing, location connectors. possible separate cables, harnesses, connectors, sensitive signals. Examine signals arranged connectors. Physically separate sensitive pins from noisy pins, group pins according function (for example, analog, digital, power, clock, etc.), spare pins separation, carry shield through connector appropriate. impedance grounds should used minimize common impedance problems.
Board System Design Crystal World Tour Application Seminar
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DATA ACQUISITION SEMINAR
Multiple Circuit Board System
Higher Power Noisy Digital Sensitive Analog
Analog Connector
Digital Connector
Example multiple board system. INVESTIGATE: Function cards components Physical placement circuit cards, power supplies, connectors, harnesses Routing power Routing noisy sensitive signals Type wire used
Board System Design Crystal World Tour Application Seminar
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DATA ACQUISITION SEMINAR
Power Distribution
Subsystem Subsystem Subsystem
Power Supply Input Power
desirable distribute power manner that parallels ground structure controlled impedance wires such twisted pairs distribute power
desirable distribute power manner that parallels ground structure. Twisted pairs used decrease loop area. current only return path back power supply. power starred avoid common impedance problems. avoid line drop, impedance wires should used with bulk capacitors voltage sense lines. Remember that power distribution system will pick noise.
Board System Design Crystal World Tour Application Seminar
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DATA ACQUISITION SEMINAR
Power Supplies
Systems have different performance when
using linear switching power supplies
Turn Time Load Regulation Line Regulation Line Noise Switching Noise
Switching frequency change with load
Power supply characteristics affect system performance. Often effect seen until late system integration even field operation. biggest change switching from power supply field supply. power supplies generally well regulated filtered linear power supplies. field supply generally switching power supply battery. Specifications investigate include turn-on time, load regulation, line regulation, over voltage protection, line noise switching noise.
When using switching power supplies, switching frequency change under different loading conditions. This important when using converters. converters utilize digital filtering. switching noise moves frequency, noise filtering characteristics vary under various operating conditions. This could produce intermittent problem that difficult identify.
Line Regulation Load Regulation Output Ripple Transient Response Efficiency
Linear Power Supply ±0.05% line change ±0.05% load change PK-PK <50µs load change
Switching Power Supply ±0.3% PK-PK 500ms typical
Board System Design Crystal World Tour Application Seminar
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DATA ACQUISITION SEMINAR
Silicon Controlled Rectifier Latch-up
+15V +15V -15V VREF +15V AGND DGND Digital Logic
Investigate power-up power-down sequences Mixed signals more susceptible
multiple power supplies high voltages
Investigate transient steady state Field power supplies have different rise times
Silicon-Controlled Rectifier (SCR) latch-up CMOS products occur during power-up sequences. Since Analog-to-Digital Converters (ADCs) Digital-to-Analog Converters (DACs) mixed signal components, they often have multiple power pins. This increases potential parasitic latch-up proper power supply sequencing followed. system design engineer needs investigate transient power-up conditions. power-up, study various components will react. example, fast will voltage regulator reference come will output op-amp supply rail, when will digital supply come analog digital grounds separate? Remember investigate lab, production/test, field conditions. digital logic powered-up when powered? This could happen during
power supply turn-on conditions when trying implement power conservation techniques. Digital logic that active when powered-up create latch-up. latch-up more likely occur systems which contain multiple power supplies, high voltage signals, high current drive circuits, power management techniques, multiple connectors. close attention different permutations power supply turn-on conditions procedures plugging cables.
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Summary
Have ground decoupling plan circuit
cards, mother boards, chassis systems
"Where does current go?" Both Analog Digital Engineers must control
grounding, power distribution, transients, decoupling, EMI, RFI, etc.
system integration have good grounding decoupling plan. same design rules precautions used circuit board design applied system integration. Think about physical placement circuit boards, wires, harnesses, cables connectors. Group specific functions together separate boards, cables, connectors noise management technique. physical separation your advantage. Investigate flow current multiple circuit boards integrated, cables shields added, multiple boxes connected. Even though noise normally considered analog problem, analog digital engineers must involved noise management.
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