Introduction EtherC E-DMAC SH7615 applied Solution Engine MS7615SE01 B

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Introduction EtherC E-DMAC SH7615 applied Solution Engine MS7615SE01 B

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Version: app091/1.0
Introduction EtherC E-DMAC SH7615 applied Solution Engine MS7615SE01 Board
Frank Field Application Engineer
Introduction:
SH7615 equipped with Media Access Controller (MAC) conforming IEEE802.3u standard, Ethernet controller (EtherC) that includes media independent interface (MII) standard unit, enabling 10/100 Mbps connection. This document describes basic functions EtherC cooperating Ethernet controller (E-DMAC). Source code excerpts illustrate usage cooperation between EtherC E-DMAC.
Contents:
Ethernet Controller (EtherC) 1.1. Media Independent Interface (MII).2 1.1.1. Register Access 1.2. Transmit Receive Contoller 1.3. Address.10 E-DMAC 2.1. Transmission 2.1.1. Transmission Flow 2.2. Reception 2.2.1. Reception Flow 2.3. Transmit Receive FIFO.13 2.4. Transmit Descriptor 2.5. Receive Descriptor EtherC E-DMAC Device Driver
16.08.00
32-bit SH-DSP SH7615 http://www.hitachi-eu.com
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Ethernet Controller (EtherC)
1.1. Media Independent Interface (MII) SH7615 equipped with Media Access Controller (MAC) conforming IEEE802.3u standard, Ethernet controller (EtherC) that includes media independent interface (MII) standard unit, enabling 10/100 Mbps full duplex connections.
EtherC FIFO Transmit Controller
FIFO E-DMAC Receive Controller
Command/Status Interface
Media Independent Interface (MII) wire MAC/PHY interface described IEEE802.3u. purpose interface allow layer devices attach variety Physical Layer devices (PHY) through common interface. operates either 100Mbps 10Mbps, dependent speed Physical Layer. With clocks running either MHz, data clocked between PHY, synchronous with Enable Error signals. time lock incoming signal from wire interface, will generate RX-CLK either 10Mbps 100Mpbs. receipt valid data from wire interface, RX-DV will active signalling that valid data will presented ERXD[3:0] pins speed RX-CLK. transmission data from MAC, TX-EN presented indicating presence valid data ETXD[3:0]. ETXD[3:0] sampled synchronous TX-CLK during time that TX-EN valid. internal registers accessible only through 2-wire Serial Management Interface with signals MDIO.
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Interface Register provides means accessing internal registers MII:
Function Reserved
Description These bits always read write value should always
Management Data-In (MDI) Management Data-Out (MDO) Management Mode (MMD)
Reads data from MII. Writes data MII. Specifies data read/write direction Read direction Write direction
Management Data Clock (MDC)
Supplies management data clock
clock input PHY, which used latch data instructions PHY. MDIO bi-directional connection used write instructions write data read data from PHY. Each data latched either rising edge MDC. MDC/MDIO common signal pair PHYS design. Therefore, each needs have unique Physical Address. Physical Address using pins defined PHYAD[4:0] PHY. These input signals strapped externally sampled reset negated. idle, responsible pull MDIO line high state. Therefore, 1.5K Ohms resistor required connect MDIO line Vcc. interface doesn't support RMII standard (Reduced Media Independent Interface). This standard reduces count halving number data pins, eliminating pins used switch applications, using single global clock. above table lists Ethernet Transceivers, which connected directly interface.
Manufacturer Lucent Technologies National Semiconductor National Semiconductor SMSC SMSC Semiconductor Corp. Altima Communications Inc. Quality Semiconductor
Part Name Am79C873 Am79C874 LU3X31T-T64 DP83840A DP83843BVJE LAN83C180 LAN83C183 78Q2120 AC101QF/TF QS6612
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1.1.1. Register Access beginning read write cycle, will send continuous bits level one, clock rate indicate preamble. zero will follow indicate start frame. read code zero, while write code zero one. These will followed bits indicate address bits indicate register address. Then bits follow allow turn around time. read operation, first will high impedance. Neither station will assert this bit. During second time, will assert this zero. write operation, station will drive first time, zero second time. bits data field then presented. first that transmitted register content. Internal registers written according following template:
output write management frame preamble (PRE): write_PHY(0xffff); write_PHY(0xffff); select register BMCR with write management frame write_PHY(BMCR_W); write data into BMCR write_PHY(BMCR_D); force independent release EtherC.PIR.LONG=0x00000000;
write management frame writing register BMCR defined follows:
write management frame defined (Preamble) (Start Frame) code PHYAD (PHY address) bits, ones bits, must bits, must write bits, 00001 MS7616SE
REGAD (register address) bits (switching time) bits, must write
#define BMCR_W
0x5082
Total: bits without
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function write_PHY defined follows:
void write_PHY(unsigned short wdata)
output bits interface register PIR, these could either Preamble write/read manag. frame: Part write management frame: Part write management frame: for(i i++) check wdata output interface register if((wdata 0x8000) 0x8000) write_1(); else write_0(); shift next output position wdata wdata (2x16 bits)
ST+OP+PHYAD+REGAD+TA bits) DATA bits)
functions write_1 write_0 defined follows:
void write_1() EtherC.PIR.BIT.MDO output EtherC.PIR.BIT.MMD write direction clock data EtherC.PIR.BIT.MDC EtherC.PIR.BIT.MDC
void write_0() EtherC.PIR.BIT.MDO output EtherC.PIR.BIT.MMD write direction clock data EtherC.PIR.BIT.MDC EtherC.PIR.BIT.MDC
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Internal registers read according following template:
unsigned short rdata;
output read management frame preamble (PRE): write_PHY(0xFFFF); write_PHY(0xFFFF); select register BMCR with read management frame read register rdata read_PHY(BMCR_R);
read management frame reading from register BMCR defined follows:
write management frame defined (Preamble) (Start Frame) code PHYAD (PHY address) bits, ones bits, must bits, must read bits, 00001 MS7616SE
REGAD (register address) bits, (switching time) bits, must read
#define BMCR_R
0x6082
Total: bits without
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function read_PHY defined follows:
unsigned short read_PHY(unsigned short MIIReadFrame) unsigned short rdata
output bits interface register PIR, these are: Part read management frame: ST+OP+PHYAD+REGAD bits) for(i i++){ check wdata output interface register if((MIIReadFrame 0x8000) 0x8000) write_1(); else write_0(); shift next output position MIIReadFrame MIIReadFrame
outputs remaining bits interface register PIR, these are: read management frame release: bits) out_hiz();
input bits interface register PIR, these are: Part read management frame: DATA bits) rdata read_MDI(); for(i (16-1); i++){ shift input towards rdata rdata read bit, read order rdata read_MDI(); return rdata;
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function out_hiz releasing defined follows:
void out_hiz() EtherC.PIR.LONG 0x00000000;
EtherC.PIR.BIT.MDC EtherC.PIR.BIT.MDC
function read_MDI returns 16-bit data internal registers:
unsigned short read_MDI() unsigned short rdata;
EtherC.PIR.LONG
0x00000000;
EtherC.PIR.BIT.MDC rdata EtherC.PIR.BIT.MDI; EtherC.PIR.BIT.MDC return rdata;
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1.2. Transmit Receive Contoller
64~1518bytes Preamble 7bytes 1byte Destination Address 6byte Source Address 6byte Frame Length 2byte Data 46~1500bytes 4bytes
SFD: Start Frame Delimiter FCS: Frame check Sequence
Ethernet Frame Format
Transmit data stored transmit FIFO from memory transmit E-DMAC. transmit controller assembles this data into Ethernet/IEEE802.3 frame, which outputs MII. main functions transmit controller follows: Frame generation transmission: Monitors line status, then adds preamble, SFD, data transmitted, sends MII. After passing through MII, transmit data sent onto line PHY. generation: Generates data field, adds transmit frame. Transmission retry: when collision detected collision window (during transmission 512-bit data that includes preamble from start transmission), transmission retried times based back-off algorithm
After frame received MII, receive controller carries address information, frame length, FCS, other checks, receive data transferred memory receive E-DMAC. main functions receive controller follows: Receive frame header check: Checks preamble SFD, discards frame with invalid pattern. Receive frame data check: Checks data length header, reports error status data length less than bytes greater than specified number bytes. Receive check: Performs check frame data field, reports error status case abnormality Line status monitoring: Reports error status illegal carrier detected means fault detection signal from Magic Packet monitoring: Detects Magic Packet from receive frames
Receive Frame Length Register (RFLR) specifies maximum frame length bytes) that received EtherC. frame length refers fields from destination address including data. When data that exceeds specified value received, part data that higher than specified value discarded. Frame contents from destination address including data actually transferred memory. data included transfer.
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1.3. Address Solution Engine MS7615SE01 equipped with four 8-bit general-purpose switches (SW5.SW8) which used 48-bit bytes) address EtherC.
Switch
Physical Address 0210 000016 0210 000116 0210 000216 0210 000316
Note: Please specify 16-bit data width State Controller (BSC) accessing SW5.SW8.
Address: 0x02000000 0x03FFFFFF: space, cache area Address: 0x22000000 0x23FFFFFF: space, cache-through area #define DP_MAC (*(volatile unsigned long 0x22100000)
unsigned long mac; unsigned char MAC[6];
define Address High Register MAHR EtherC #define MAHR (*(volatile unsigned long 0xFFFFFD70) define Address High Register MALR EtherC #define MALR (*(volatile unsigned long 0xFFFFFD74)
DP_MAC; store 48-Bit address array MAC[0] 0x00; MAC[1] 0x00; MAC[2] (char)((mac 0xFF000000) 24); MAC[3] (char)((mac 0x00FF0000) 16); MAC[4] (char)((mac 0x0000FF00) MAC[5] (char)((mac 0x000000FF)); write 48-Bit address register MAHR MALR ((unsigned long)MAC[0] initialise address
((unsigned long)MAC[1] ((unsigned long)MAC[2] ((unsigned long)MAC[3]); MAHR mac; ((unsigned long)MAC[4]
((unsigned long)MAC[5]); MALR mac;
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E-DMAC
E-DMAC manages transmit/receive buffers means corresponding transmit/receive circular descriptor buffer. E-DMAC reads transmit data from transmit buffer writes received data receive buffer accordance with descriptor control information. setting number consecutive descriptors, possible execute transmission reception continuously. communication program creates transmit receive descriptor linked lists memory. start addresses these lists then Tx-Descriptor List Address Register (TDLAR) Rx-Descriptor List Address Register (RDLAR). last descriptor transmit/receive descriptor list marked last entry order ring configuration. Note: descriptor start address must aligned with descriptor length (16-byte, 32-byte 64-byte) specified E-DMAC Mode Register (EDMR).
Descriptor information
FIFO
Internal Interface
Tx-DMAC
Descriptor information
FIFO
EtherC
Rx-DMAC
E-DMAC
External Interface
INTC
Tx-Descriptor Tx-Buffer
Rx-Descriptor Rx-Buffer
Memory
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2.1. Transmission transmit E-DMAC fetches transmit buffer address from transmit descriptor list, transfers transmit data buffer transmit FIFO. transmit directive follows descriptor, E-DMAC reads next descriptor transfers data corresponding buffer transmit FIFO. this way, continuous data transmission carried out. When transmit command issued from transmit E-DMAC, EtherC starts transmission accordance with predetermined transmission procedure. 2.1.1. Transmission Flow
creates Tx-Descriptor list moves frame data into Tx-buffers initializes EtherC E-DMAC registers, then sets Transmitter Enable (TE) EtherC Mode Register (ECMR) sets (Transmit Request) E-DMAC Transmit Request Register (EDTRR) initiate transmission E-DMAC then starts reading Tx-Descriptor transfers frame data from Tx-buffer Tx-FIFO EtherC starts transmit preamble whenever Tx-FIFO becomes full reaches threshold monitors Ethernet transmits data during idle period collision occurs EtherC retransmits according Back-off algorithm times) EtherC E-DMAC continues transfer data from Tx-Buffer Tx-FIFO, providing FIFO full threshold reached (E-DMAC transfers data byte units) EtherC continues send data then completes packet appending E-DMAC updates Tx-Descriptor (Descriptor Write-Back), then generates TxComplete Interrupt (TC). After waiting frame interval time, transmission continues next frame
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2.2. Reception When own-address frame (including broadcast frame) received, EtherC transfers frame receive E-DMAC while carrying format checks. frame reception EtherC carries check, completing reception frame. receive data transferred memory receive data E-DMAC does include data. each start receive E-DMA transfer, receive E-DMAC fetches receive buffer address from receive descriptor list. When receive data stored receive FIFO, E-DMAC transfers this data receive buffer. When reception frame finished, E-DMAC performs receive status write fetches receive buffer address from next descriptor. repeating this sequence, consecutive frames received. 2.2.1. Reception Flow
creates Rx-Descriptor list allocates Rx-Buffer space initializes EtherC E-DMAC registers, then sets Receiver Enable (TE) EtherC Mode Register (ECMR) sets (Receive Request) E-DMAC Receive Request Register (EDRRR) E-DMAC starts reading Rx-Descriptor monitors status then acknowledges EtherC Ethernet frame recognized EtherC confirms destination address, separates frame, transfers data portion Rx-FIFO E-DMAC then transfers data from Rx-FIFO Rx-buffer when data reaches threshold where minimum transfer unit bytes E-DMAC checks packet. match, generates Error Interrupt (CERF) E-DMAC updates Rx-Descriptor (Write-Back), then generates Frame Received Interrupt (FR)
2.3. Transmit Receive FIFO receive transmit FIFOs have maximum capacity Bytes. FIFO Depth Register (FDR) specifies depth (size) transmit receive FIFOs. Valid sizes bytes. FIFO Threshold Register (TFTR) specifies FIFO threshold which first transmission started. Valid treshold values range from 4.512 bytes steps bytes store-and-forward mode (transmission starts when frame data written FIFO full). receive FIFO E-DMAC hold eight frames. ninth frame received when there already eight frames receive FIFO, receive frame counter overflows ninth frame discarded. Discarded frames counted missed-frame counter register. eight frames receive FIFO retained, transferred memory when E-DMA transfer becomes possible. When frame counter value falls below another frame received.
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2.4. Transmit Descriptor
TD0: TD1: TD2: TACT TDLE Transmit Frame Status (TFS) Valid Transmit Data Transmit Buffer
Transmit Data Length (TDL) Transmit Buffer Address (TBA) Address next Transmit Descriptor
TACT
Indicates that this descriptor active. sets this after transmit data been transferred transmit buffer. E-DMAC resets this completion frame transfer when transmission suspended. Indicates that this descriptor last linked transmit descriptor list. After completion corresponding buffer transfer, E-DMAC references next descriptor. This specification used ring configuration transmit descriptors. These bits specify relationship between transmit buffer transmit frame (Frame Start, Middle, Entire frame). Indicates that other transmit frame status indicated bits set. Whether transmit frame status information copied into this specified Tx/Rx Status Copy Enable Register (TRSCER). These bits indicate error status during frame transmission. These bits specify valid transfer byte length corresponding transmit buffer. Specifies 32-bit transmit buffer start address
TDLE
TFP1, TFP0
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TDLAR Current E-DMA transmission
Transmit Buffers
Next Available Transmit Buffer TACT (valid descriptor)
(last descriptor)
When transmitter enabled Transmit Request E-DMAC Transmit Request Register EDTRR, E-DMAC reads descriptor following previously used from transmit descriptor list. setting TACT read transmit descriptor "active" E-DMAC reads transmit frame data sequentially from transmit buffer start address specified TBA, transfers EtherC. EtherC creates transmit frame starts transmission MII. E-DMAC continues reading descriptors transmitting frames long setting TACT read transmit descriptors "active." When descriptor with "inactive" TACT read, E-DMAC resets Transmit Request Transmit Register EDTRR ends transmit processing. After E-DMA transfer data equivalent buffer length specified descriptor, following processing carried according value:
TFP[1:0] TFP[1:0] TFP[1:0] TFP[1:0] (start frame): Descriptor write-back performed after E-DMA transfer. (frame continuation): Descriptor write-back performed after E-DMA transfer. (end frame): Descriptor write-back performed after completion frame transmission. (entire frame): Descriptor write-back performed after completion frame transmission.
Note: E-DMAC doesn't reset bits TFP[1:0] completion frame transfer when transmission suspended. These bits have controlled software.
Start Frame Frame continues Frame continues Frame Entire Frame Start Frame Frame
Packet
Packet
Packet TFP[1:0]
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2.5. Receive Descriptor frame reception, E-DMAC performs data rewriting receive buffer 16-byte boundary, regardless receive frame length. Finally, actual receive frame length reported descriptor. Data transfer receive buffer performed automatically E-DMAC give frame/one buffer frame/multi-buffer configuration according size received frame.
RD0: RD1: RD2: RACT RDLE Receive Frame Status (RFS) Receive Buffer
Receive Buffer Length (RBL) Receive Data Length (RDL)
Valid Receive Data
Receive Buffer Address (RBA) Address next Receive Descriptor
RACT
Indicates that this descriptor active. E-DMAC resets this after receive data been transferred receive buffer. completion receive frame processing, sets this prepare reception. Indicates that this descriptor last transmit descriptor list. After completion corresponding buffer transfer, E-DMAC references next descriptor. This specification used ring configuration receive descriptors. These bits specify relationship between receive buffer receive frame (Frame Start, Middle, Entire frame). Indicates that other receive frame status indicated bits set. Whether receive frame status information copied into this specified Tx/Rx Status Copy Enable Register (TRSCER). These bits indicate error status during frame reception. These bits specify maximum transfer byte length corresponding receive buffer. These bits specify data length receive frame stored receive buffer. Specifies 32-bit transmit buffer start address
RDLE
RFP1, RFP0
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When receiver enabled sets Receive Request (RR) EDMAC Receive Request Register EDRRR, E-DMAC reads descriptor following previously used from receive descriptor list, then enters receivestandby state. setting RACT "active" own-address frame received, E-DMAC transfers frame receive buffer specified RBA. data length received frame greater than buffer length given RBL, EDMAC performs write-back descriptor when buffer full (RFP[1:0] x0), then reads next descriptor. E-DMAC then continues transfer data receive buffer specified RBL. When frame reception completed, frame reception suspended because error some kind, E-DMAC performs writeback relevant descriptor (RFP[1:0] x1), then ends receive processing. E-DMAC then reads next descriptor enters receive-standby state again.
RFP[1:0] RFP[1:0] RFP[1:0] RFP[1:0] (start frame): Descriptor write-back performed after E-DMA transfer. (frame continuation): Descriptor write-back performed after E-DMA transfer. (end frame): Descriptor write-back performed after completion frame transmission. (entire frame): Descriptor write-back performed after completion frame transmission.
Note: receive frames continuously, Receive Enable Control must Receive Control Register (RCR). After initialisation, this cleared
RDLAR
Next readable buffer
Receive Buffers
Current active receive
RACT (valid descriptor)
(last descriptor)
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EtherC E-DMAC Device Driver
transmit receive descriptor structure defined follows:
typedef struct Descript{ unsigned long unsigned short unsigned short char status; bufsize; size; *buf_p;
struct Descript *next; }ethfifo;
#define #define #define #define #define
0x80000000 0x40000000 0x20000000 0x10000000 0x08000000
descriptor lists corresponding buffers defined follows:
#define ENTRY ethfifo rxPkt[ENTRY]; ethfifo txPkt[ENTRY]; descriptors list receive descriptor list
transmit descriptor list
#define BUFSIZE
buffer size corresponds FIFO size specified FIFO Depth Register
char rxbuf[ENTRY][BUFSIZE]; char txbuf[ENTRY][BUFSIZE];
receive data buffers transmit data buffers
define current descriptor pointer init. head list ethfifo *txcurrent &txPkt[0]; ethfifo *rxcurrent &rxPkt[0];
Note: transmit receive descriptors have align with descriptor length (16-byte, 32-byte 64-byte) specified E-DMAC Mode Register (EDMR). corresponding transmit receive buffers have aligned 16-byte boundary.
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receive transmit descriptor lists have initialised before first use:
pointer descriptor array status: status descriptor (either void long init_ethfifo(ethfifo p[], unsigned long status)
list receive transmit descriptors ENTRY; i++){ status selects transmit receive descriptor list (status p[i].buf_p &txbuf[i][0]; transmit buffer address else p[i].buf_p &rxbuf[i][0]; receive buffer address
BUFSIZE; j++) clear complete buffer p[i].buf_p[j]
p[i].bufsize BUFSIZE; enter buffer size descriptor
size data transmitted size receive data p[i].size p[i].status status; receive active, transmit inactive address next receive transmit descriptor p[i].next &p[i+1]; p[ENTRY-1].status DLE; init. last descriptor, last descriptor address last list entry, because want have circular descriptor buffer p[ENTRY-1].next &p[0];
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function write_ethfifo copies data into transmit buffer inactive (TACT transmit descriptor. error returned transmit descriptor active. amount data transferred larger than actual size transmit buffer, difference returned.
buf: size: pointer transmit descriptor buffer holding data transmitted amount data transmitted
return: amount transmitted bytes long long write_ethfifo(ethfifo unsigned char buf[], long size)
((p->status ACT) ACT) return
current descriptor active can't access buffer
copy data transmitted from buf[] transmit buffer size; i++){ p->buf_p[i] buf[i]; if(i BUFSIZE) check against buffer overflow break; want transfer more bytes than actual buffer size, have split transfer. p->size enter actual transmission size report transmission size return
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function write_ethfifo used function eth_write split frames into transmit FIFO size specified FIFO Depth Register FDR. Furthermore, this function manages circular buffer holding transmit descriptors.
data: count: buffer holding data transmitted amount data transmitted
return: amount transmitted bytes long long long long length; flag FP1; size count; start frame, i.e. FP1=1, FP0=0 eth_write(char *data, long count)
split data into frames size length, i.e. length FIFO depth specified FIFO Depth Register (length count count count length) soon descriptor inactive, data transferred from buffer denoted data transmit buffer. write_ethfifo returns transmission size. while((length write_ethfifo(txcurrent, data, count))
indicate that last frame transmit, otherwise continues mode (length count) flag FP0; frame, i.e. FP1=x, FP0=1
txcurrent->status ~(FP1|FP0); clear previous settings txcurrent->status flag ACT; activate transmit descriptor flag continues frame, i.e. FP1=0, FP0=0 txcurrent txcurrent->next; select next descriptor list data length; increment pointer data buffer if(E_DMAC.EDTRR.LONG 0x00000000) restart E-DMAC, stopped E_DMAC.EDTRR.LONG 0x00000001; return(size); return transfer count
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function read_ethfifo copies data from receive buffer inactive (RACT receive descriptor. error returned receive descriptor active. amount data which received returned. maximum return value FIFO size specified FIFO Depth Register FDR.
buf: pointer receive descriptor buffer receiving data
return: amount received bytes long read_ethfifo (ethfifo char buf[]) long byte counter
((p->status ACT) ACT) return
current descriptor active can't access buffer
copy received data from receive buffer buf[] p->size; i++) buf[i] p->buf_p[i]; return
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function read_ethfifo used function eth_read concatenate frames with size equal size receive buffer copy them buffer denoted data. Furthermore, this function manages circular buffer holding receive descriptors.
data: buffer receiving data return: amount received bytes long long receivesize; receive byte counter long length; long flag continue receive long equal eth_read(char *data)
while(flag){ soon descriptor inactive, data transferred from receive buffer buffer denoted data. read_ethfifo returns amount received bytes. while((length read_ethfifo (rxcurrent, data))
start frame frame receive, i.e. ((rxcurrent->status FP1) FP1) receivesize
frame frame receive, i.e. ((rxcurrent->status FP0) FP0) flag
if((rxcurrent->status receivesize error occurred else receivesize length; increment received byte counter
mark receive descriptor ready receive rxcurrent->status ACT; data length; increment pointer receive data buffer rxcurrent rxcurrent->next; select next descriptor list return receivesize; return receive byte count
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When using this document, keep following mind, This document may, wholly partially, subject change without notice. rights reserved: permitted reproduce duplicate, form, whole part this document without Hitachi's permission. Hitachi will held responsible damage user that result from accidents other reasons during operation user's unit according this document. Circuitry other examples described herein meant only indicate characteristics performance Hitachi's semiconductor products. Hitachi assumes responsibility intellectual property claims other problems that result from applications based examples therein. license granted implication otherwise under patents other rights third party Hitachi, Ltd. MEDICAL APPLICATIONS: Hitachi's products authorised MEDICAL APPLICATIONS without written consent appropriate officer Hitachi's sales company. Such includes, limited life support systems. Buyers Hitachi's products requested notify relevant sales office when planning products MEDICAL APPLICATIONS. Copyright ©Hitachi, Ltd.,1995. rights reserved
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Introduction EtherC E-DMAC SH7615 applied Solution Engine MS7615SE01 B

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