APN1010 Introduction increased demand mobile network connections

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APN1010 Introduction increased demand mobile network connections

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Design WLAN Applications 2.4-2.5 Band
APN1010 Introduction
increased demand mobile network connections lead establishment interface standards Wireless Local Area Networks (WLANs). unlicensed frequency band, 2.4-2.5 GHz, been designated WLAN usage. Table 1[1] displays frequency allocations different parts world WLAN. IEEE 802.11 specifies physical layer interfaces WLAN, Direct Sequence Spread Spectrum (DSSS), Frequency Hopped Spread Spectrum (FHSS). DSSS uses 11-bit Barker code where each information spread within single channel. IEEE standard allocates channels, each wide, with spacing between center frequencies 83.5 band. This creates channels whose frequencies overlap. With FHSS, there channels, each wide. transmitter receiver follow predetermined frequency-hopping sequence least once every frequency-hopping sequences have been arranged spread power evenly across band. typical DSSS interface architecture, shown Figure signal passes through antenna diversity switch (this switch designed using Alpha's common cathode SMP1320-074 diode). signal passes through bandpass filter switch (this switch designed using Alpha's diodes SMP1320-079 SMP1322-017[3]). down/up converter Intersil HFA3683, signal converted MHz. signal enters second down/up converter, Intersil HFA3783, further converted to/from baseband input/output interface range. This architecture uses external VCOs local oscillators. selected frequency plan, operational range 2.06-2.1095 operates fixed frequency. This application note describes design VCOs 2.4-2.4835 WLAN application. based frequency plan described above. Although this design addresses particular system outline, this example applied most WLAN systems.
Region Europe Japan France Spain
Allocated Spectrum (GHz) 2.4-2.4835 2.471-2.497 2.4465-24835 2.445-2.475
Table Global Spectrum Allocation GHz1
2.4-2.4835 2.4-2.4835 HFA3683 SMP1320-074 SMP1322-017 SMP1320-079 Base Band Processor HFA3783
0/90°
Ant. Select
2.026-2.1095
Figure Typical WLAN Interface Architecture Based Intersil Prism Chip Set2
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Design WLAN Applications 2.4-2.5 Band
APN1010
Specifications
frequency plan shown Figure frequency range 2.026-2.1095 GHz. reality, tuning range specific design should stretched accommodate conditions that would affect frequency. These factors include temperature variations, component value variations, aging, humidity. Table shows tuning range needs expanded meet these conditions. assume that +0.1%/10°C temperature sensitivity, which typical uncompensated designs.
Similar considerations lead extension range MHz, ±3.2%, (724-772 MHz) resulting tuning range. performance also depends characteristics specific chip-set used. Table lists typical performance objectives VCO.
Design Considerations
important consideration other components integrated same ability cover frequency range with trimming. Non-trimmed VCOs particularly sensitive variations component values material characteristics. addition, VCOs operating oscillation frequencies greater than even more sensitive these variations. this reason, this design employs frequency-doubling scheme achieve between 1.969-2.1841 GHz. fundamental frequency architecture, Figure operates 0.9845-1.092 GHz, half output frequency. This signal multiplier/buffer transistor, whose output circuit tuned second harmonic, 1.969-2.184 GHz. important benefit frequency doubling inherent high level load isolation, reducing buffer amplifier's complexity. However, presence fundamental component output spectrum require some filter circuitry multiplier output prevent counter errors. fundamental designed using traditional Colpitts circuit procedures. Similarly, also traditional design using separate Colpitts buffer transistor, both operating same frequency range 0.726-0.770 GHz.
Tuning Range (GHz) Range Description Operational Temperature (+15°C 85°C) Components Variations Aging Other +0.7 ±2.3 ±0.5 Margin Min. 2.026 2.026 1.979 1.969 Max. 2.1095 2.1243 2.1732 2.1841
Table Tuning Range Margins
this design, there frequency trimming allowed after mounting. Therefore, tuning range will extended cover deviations resulting from component value variations. inductors capacitors with tolerance worst case ±2.3% frequency variation result. Including aging other factors, ±0.5% final tuning range will from 1.969-2.184 GHz, MHz.
Parameter Frequency Range (GHz)
Test Conditions VCTL
1.969 0.726 2.184 0.770 0.5-2.5
Tuning Sensitivity (MHz/V) Supply Voltage Supply Current (mA) Control Voltage Output Power (dBm) Pushing Figure (MHz/V) Pulling Figure (MHz) Phase Noise (dBc/Hz) VSWR Phases VCTL POUT
0.5-2.5
Table Typical RF/IF Performance
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Design WLAN Applications 2.4-2.5 Band
APN1010
Transistor
Buffer Transistor
Frequency Doubler Transistor
VCTL
0.9845-1.092 0.9845-1.092
0.9845-1.092
1.969-2.184
Figure Block Diagram
Colpitts Fundamentals
fundamental Colpitts operation illustrated Figures Figure shows Colpitts circuit usually implemented PCB. Figure reconfigures same circuit common-emitter amplifier with parallel feedback. transistor junction package capacitors, CEB, CCE, shown separated from
CSER CVCC
transistor parasitic components demonstrate their direct effect tank circuit. actual low-noise circuit, capacitor noted CVAR have more complicated structure. would include series parallel-connected discrete capacitors used oscillation frequency tuning sensitivity. parallel resonator simply resonator) consists parallel connection resonator inductance, LRES, varactor capacitive branch, CVAR. fundamental property parallel resonator Colpitts inductive impedance oscillation frequency. This means that parallel resonant frequency always higher than oscillation frequency. parallel resonance resonator branch, impedance feedback loop high, acting like stop band filter. Thus, closer oscillation frequency parallel resonant frequency, higher loss introduced into feedback path. However, since more reactive energy stored parallel resonator closer resonant frequency, higher Q-loaded (QL) will achieved. Obviously, low-loss resonators, such crystal dielectric resonators, allow closer lower loss oscillation buildup parallel resonance comparison microstrip discrete inductor-based resonators. proximity parallel resonance oscillation frequency effectively established CSER capacitance value. Indeed, capacitance CSER reduced, parallel resonator will have higher inductance compensate increased capacitive reactance. This means that oscillation frequency will move closer parallel resonance resulting higher higher feedback loss. Leeson equation establishing connection between tank circuit losses states:
CDIV1 LRES CVAR CDIV2 POUT
Figure Basic Colpitts Configuration
CSER LRES CVCC
CDIV1
CVAR
CDIV2
Figure Common Emitter View Colpitts
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Design WLAN Applications 2.4-2.5 Band
APN1010
Where large-signal noise figure amplifier shown Figure 1b), loop feedback power (measured input transistor), loaded These three parameters have significant consequence phase noise actual low-noise VCO. designing noise VCO, need define condition minimum maximum This discussion shows that loop power contradictory parameters. That increase leads more loss feedback path resulting lower loop power. condition optimum noise figure also contrary maximum loop power largely depends specific transistor used. best noise performance usually achieved with high gain transistor whose maximum gain coincides with minimum noise large signals. Since there such specifications currently available standard industry transistors, only base transistor choice experience.
Figure Resonator Model
Transmission line models physical connection resonator with base transistor (Figure 4b). circuit model, shown Figure transistors, connected cascode sharing base bias network consisting (RDIV1), (RDIV2) bias resistor values were designed evenly distribute voltages between emitter bias resistor, RL1, chosen value minimize voltage drop. inductance series with network SRL1 enhances RF-to-ground impedance emitter terminal. frequencies, operates commonemitter amplifier with emitter grounded through parallel capacitor network SRLC1-SRLC3. efficiency circuit suppresses fundamental component enhances second harmonic output critical design that network. inductors parasitic inductances SRLC1 SRLC3 crucial parts design.
Model
model shown Figures Some component values, defined variables, listed "Var_Eqn" column Figure resonator model, Figure SMV1763-079 varactor model described resistor inductor, SRL4, connected series, capacitor diode SMV1763 connected parallel. varactor choice based frequency coverage requirement phase noise. resonator inductor, LRES, described series network SRL1 with parallel capacitor Parallel capacitor modeled with parasitic series inductance resistance SRLC1 series network. series capacitors, CSER CSER2, also modeled SRLC series networks, XRLC4, respectively.
Figure Circuit Model
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Design WLAN Applications 2.4-2.5 Band
APN1010
details SRLC1-SRLC3 network layout design shown Figure circuit model values appearing model were optimized circuit's performance. Some inductors model look different from layout attributed imperfection circuit component models. output circuit transistor, consists transmission line coupling capacitor SLC3. This output circuit tuned second harmonic oscillation frequency. buffer transistor operates second harmonic ordinary common-emitter amplifier with about current high gain. test bench Figure loop gain VOUT/VIN defined ratio voltage phasors input output ports OSCTEST component. Defining oscillation point technique balance input (loop) power order provide zero gain zero loop phase shift. Once oscillation point defined, frequency output power "measured." recommend OSCTEST2 component closed loop analysis, since converge does allow clear insight behavior.
Figure SRLC1-SRLC3 Network Layout Details
Figure Test Bench Open Loop Oscillator Analysis Using OSCTEST Coupler from Libra Library
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Design WLAN Applications 2.4-2.5 Band
APN1010
Model
model shown Figures Some component values, defined variables, listed "Var_Eqn" column Figure resonator model, Figure SMV1763-079 varactor model described with resistor inductor, SRL4, connected series, capacitor diode SMV1763 connected parallel. this narrow band application many varactors, abrupt hyperabrupt, work well, however, resistance hyperabrupt characteristic SMV1763-079 helps improve tuning linearity phase noise. resonator inductor, LRES, described series network, SRL1, with parallel capacitor parallel capacitor modeled with parasitic series inductance resistance SRLC1 series network. series capacitors, CSER CSER2, also modeled SRLC series networks, XRLC4 respectively. Transmission line, TL2, models physical connection resonator with base transistor, Figure circuit model, Figure transistors biased separately independently optimize performance buffer transistors. emitter bias resistor, RL1, chosen achieve current/performance balance transistor. overall current from bias approximately which adequate provide sufficient power with good phase noise performance. output signal from collector resistor shown base common-emitter amplifier buffer stage output circuit buffer stage consists parallel-connected inductor, SRL1, capacitor, SLC2, coupling capacitor, SRLC1. collector inductance modeled lossy inductance with series resistance parallel with parasitic capacitor,
Transmission line, TL1, essential contributor performance, part load/tank circuitry. According Figure active load, Figure 7b), could interpreted series impedance between collector transistor capacitor CVCC. Transmission line, TL1, Figure considered inductor series with that load. buffer input circuit then becomes parallel both Figure 7b). effective inductance improves input match buffer stage increases output power level; however, this will also increase load feedback power, which lead phase noise degradation. test bench identical Figure VCO), which defined open loop analysis with OSCTEST component above.
Figure Resonator Model
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Design WLAN Applications 2.4-2.5 Band
APN1010
Figure Circuit Model
SMV1763-079 SPICE Model
SMV1763-079 series resistance, hyperabrupt junction varactor diode. packaged small footprint, SC-79 plastic package with body size mils (total length with leads mils). SPICE model SMV1763-079 varactor diode, defined Libra environment, shown Figure with description parameters employed.
PORT P_anode port 1.10 DIODEM smv1763 1.00e-014 7.60e-012 1.11 0.50 1.00e-003
0.60 DIODE DIOD3 AREA MODEL amv1763 MODE nonlinear
IBVL NBVL TBV1 TNOM
1.60
PORT P_cathode port
Figure SMV1763-079 SPICE Model Libra
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APN1010
Table describes model parameters. shows default values appropriate silicon varactor diodes that used Libra simulator.
Parameter IBVL NBVL TNOM Series resistance
Description Saturation current (with determine characteristics diode) Emission coefficient (with determines characteristics diode) Transit time Zero-bias junction capacitance (with define nonlinear junction capacitance diode) Junction potential (with define nonlinear junction capacitance diode) Grading coefficient (with define nonlinear junction capacitance diode) Energy (with XTI, helps define dependence temperature) Saturation current temperature exponent (with helps define dependence temperature) Flicker-noise coefficient Flicker-noise exponent Forward-bias depletion capacitance coefficient Reverse breakdown voltage Current reverse breakdown voltage Recombination current parameter Emission coefficient High-injection knee current Reverse breakdown ideality factor level reverse breakdown knee current level reverse breakdown ideality factor Nominal ambient temperature which these model parameters were derived Flicker-noise frequency exponent
Unit
Default 1e-14 1.11 Infinity 1e-3 Infinity
Table Silicon Diode Default Values Libra
According SPICE model, varactor capacitor, function applied reverse voltage, expressed follows:
This equation mathematical expression capacitance characteristic. model most accurate abrupt junction varactors (like Alpha's SMV1408). hyperabrupt junction varactors, model less accurate because coefficients dependent applied voltage. make this equation work better hyperabrupt varactors coefficients were optimized best capacitance voltage shown Table Note that Libra model above, given picoFarads, while given farads comply with default unit system used Libra.
Part Number SMV1763-079
(pF)
(pF)
(nH)
Table SPICE Parameters SMV1763-079
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Design WLAN Applications 2.4-2.5 Band
APN1010
Design, Materials Layout
circuit diagram shown Figure circuit powered voltage source. current established near output signal coupled from through capacitor pF).
VCTL: 0.5-2.5
layout shown Figure board made standard thick material. passive components board have 0402 footprints. bill materials shown Table
VCC: 0.15 0.15
NE68019
NE68019
SMV1763-079
NE68519
POUT
Figure Schematic
Figure
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Design WLAN Applications 2.4-2.5 Band
APN1010
Designator
Value SMV1763-079 0.11 0.11 NE68119 NE68619 NE68619
Part Number 0402AU101KAT 0402AU5R0JAT 0402AU1R0JAT 0402AU1R8JAT 0402AU6R0JAT 0402AU3R6JAT 0402AU561KAT 0402AU2R0JAT 0402AU101KAT 0402AU7R0KAT 0402AU1R2KAT 0402AU561KAT 0402AU1R0KAT 0402AU561KAT SMV1763-079 CR10-242J-T CR10-822J-T CR10-271J-T CR10-101J-T CR10-562J-T CR10-101J-T CR10-302J-T LL1005-FH22NK 0402CS-3N9XJB MSL(Meander Line) MSL(Meander Line) HI1608-1B68N_N_K NE68119 NE68619 NE68619
Footprint 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 SC-79 0402 0402 0402 0402 0402 0402 0402 0402 0402 0.11mm 0.11mm 0603 SOT-416 SOT-416 SOT-416
Manufacturer Alpha Industries, Inc. AVX/KYOCERA AVX/KYOCERA AVX/KYOCERA AVX/KYOCERA AVX/KYOCERA AVX/KYOCERA AVX/KYOCERA TOKO COILCRAFT
(Taiwan) NEC/CEL NEC/CEL NEC/CEL
Table Bill Materials
Design, Materials Layout
circuit diagram shown Figure This circuit also powered voltage source. current established near output signal coupled from through capacitor pF). layout shown Figure board made using standard thick material. Passive components board have 0402 footprints. bill materials shown Table
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Design WLAN Applications 2.4-2.5 Band
APN1010
VCTL: 0.5-2.5 VCC:
SMV1763-079
NE68019 NE68119
Figure Schematic
Figure
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Design WLAN Applications 2.4-2.5 Band
APN1010
Designator
Value SMV1763-079 NE68119 NE68019
Part Number 0402AU101KAT 0402AU4R0JAT 0402AU2R7JAT 0402AU2R7JAT 0402AU4R0JAT 0402AU3R0JAT 0402AU561KAT 0402AU3R0JAT 0402AU101KAT 0402AU2R0KAT 0402AU3R0JAT SMV1763-079 CR10-302J-T CR10-302J-T CR10-200J-T CR10-131J-T CR10-302J-T CR10-302J-T CR10-201J-T 0402CS-56NXJB 0402CS-6N8XJB 0402CS-10NXJB NE68119 NE68019
Footprint 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 SC-79 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 SOT-416 SOT-416
Manufacturer Alpha Industries, Inc. AVX/KYOCERA AVX/KYOCERA AVX/KYOCERA AVX/KYOCERA AVX/KYOCERA AVX/KYOCERA AVX/KYOCERA COILCRAFT COILCRAFT COILCRAFT NEC/CEL NEC/CEL
Table Bill Materials
VCO: Measurement Simulation Results
measured performance this circuit simulated results obtained from model shown Figures Phase noise measurements shown Figure showing better than dBc/Hz offset better than -111 dBc/Hz offset. This dB/decade slope constant below MHz.
Frequency (GHz)
2.35 simu. 2.25 2.15 Fosc simu. 2.05 1.95 1.85 simu.
Output Power (dBm)
Control Voltage
Fosc meas. meas. meas.
Figure Tuning Response
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Design WLAN Applications 2.4-2.5 Band
APN1010
Because frequency doubling, phase noise fundamental frequency should better offset. doubled frequency phase response, shown Figure gradually diverges from fundamental frequency offset frequency increases with phase noise difference close ideal value measurements were performed using Aeroflex PN9000 Phase Noise Test with delay-line. measured frequency tuning response, Figure shows near linear, MHz/V, tuning sensitivity 0.5-2.5 range typical battery applications. simulated frequency tuning response similar measured response. output power tuning
2.10 meas.
voltage shows divergence between measurement simulation. This attributed inaccuracy model parameters, especially transistor model parameters. These models derived small-signal amplifier applications accurately reflect higher degree nonlinearity VCO. supply pushing response shown Figure shows distinct change frequency supply voltage, which probably result dominant emitterbase capacitance. Table summarizes data measured VCOs.
Parameter Frequency Range (GHz) Test Conditions VCTL Tuning Sensitivity (MHz/V) Supply Voltage Supply Current (mA) Control Voltage Output Power (dBm) Pushing Figure (MHz/V) Pulling Figure (MHz) Phase Noise (dBc/Hz) VSWR Phases VCTL POUT 1.93 0.720 2.22 0.765 0.5-2.5 0.5-2.5
Output Power (dBm)
Frequency (GHz)
2.09 Fosc meas. 2.08
2.07
Voltage Figure Pushing Response
Table Measured RF/IF Performances
Figure Phase Noise VCTL
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Design WLAN Applications 2.4-2.5 Band
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VCO: Measurement Simulation Results
measured performance simulated results shown Figures Phase noise measurements, shown Figure demonstrate better than dBc/Hz offset better than -114 dBc/Hz offset. This dB/decade slope constant below MHz. with VCO, these measurements were performed with Aeroflex PN9000 Phase Noise Test Set. measured frequency tuning response, Figure shows MHz/V tuning sensitivity 0.5-2.5 range,
Fosc simu.
typical battery applications. simulated frequency tuning response shows higher tuning range because transmission line (TL1 Figure significantly affects performance. Another reason divergence simulation measurement data effect higher harmonics. more complicated circuit model than described Figure required account higher harmonics. model used, however, quite successful achieving design goals first attempt (directly from simulation physical design) understanding phenomena such influence TL1.
Fosc meas. POUT (dBm)
Output Power (dBm)
Frequency (MHz)
simu.
Frequency (MHz)
Output Power (dBm)
Voltage Figure Pushing Response
Control Voltage
Fosc meas. meas.
Figure Tuning Response
Figure Phase Noise VCTL
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Design WLAN Applications 2.4-2.5 Band
APN1010
Summary
this application note, designs applicable 2.4-2.5 WLAN transceiver functions were demonstrated. shown that with large tuning sensitivity (about MHz/V) could achieved with phase noise dBc/Hz offset) using Alpha Industries' resistance hyperabrupt varactor SMV1763-079. This varactor also shown suit lower frequency VCO, providing good tuning range phase noise. models were developed that were able accurately predict performance, were confirmed comparison simulated measured performance.
References
AN9829, Brief Tutorial IEEE 802.11 Wireless LANs, Intersil Co., Feb. 1999. AN9837, PRISM Chip Overview, MBPS SiGe, Intersil Co., Feb. 1999. APN1016, Switch WCDMA IMT-2000 Handset Applications, Alpha Industries, Inc., 1999. APN1004, Varactor SPICE Models Applications, Alpha Industries, Inc., 1998. APN1006, Colpitts Wide Band (0.95 GHz- 2.15 GHz) Tuner Applications, Alpha Industries, Inc., 1999. APN1005, Balanced Wide Band Tuner Applications, Alpha Industries, Inc., 1999. APN1007, Switchable Dual-Band 170/420 Handset Cellular Applications, Alpha Industries, Inc., 1999. APN1012, Designs Wireless Handset CATV Set-Top Applications, Alpha Industries, Inc., 1999. APN1013, Differential Handset Applications, Alpha Industries, Inc., 1999. APN1015, GSM/PCS Dual-Band Switchable Colpitts Handset Applications. APN1016, Phase Noise Design Handset Applications, Alpha Industries, Inc., 1999.
List Available Documents
WLAN Simulation Project Files Libra WLAN Circuit Schematic Layout Protel, Client, 1998 Version. WLAN Gerber Photo-plot Files.
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APN1010 Introduction increased demand mobile network connections

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