PanelLink Technology High Speed Transmitter Receiver Data Sheet R
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65100/101
PanelLink Technology High Speed Transmitter Receiver
Data Sheet Revision December 1996
Copyright Notice Copyright© 1996 Chips Technologies, Inc. RIGHTS RESERVED. This manual copyrighted Chips Technologies, Inc. reproduce, transmit, transcribe, store retrieval system, translate into language computer language, form means electronic, mechanical, magnetic, optical, chemical, manual, otherwise part this publication without express written permission Chips Technologies, Inc. Restricted Rights Legend Use, duplication, disclosure Government subject restrictions forth subparagraph (c)(1)(ii) Rights Technical Data Computer Software clause 252.2777013. Trademark Acknowledgment CHIPS Logo, PEAK, PRINTGINE, SCAT, WINGINE registered trademarks Chips Technologies, Inc. HiQVision, HiQColor, HiQVideo, HiQV32, HiQV64, HiQV64P, HiQVPro, HiQVDual, HiQVDualP, HiQV-MPEG, HiQV-3D, SMARTMAP, "Solutions Changing World" trademarks Chips Technologies, Inc. Brooktree RAMDAC trademarks Brooktree Corporation. Hercules trademark Hercules Computer Technology. Inmos trademark Inmos Corporation. 386SX, i387, 486, i486, Pentium trademarks Intel Corporation. IBM, PS/2 Personal System/2 registered trademarks International Business Machines Corporation. trademark International Business Machines Corporation. Microsoft registered trademark Microsoft Corporation. trademarks Microsoft Corporation. MS-DOS Windows
TRI-STATE registered trademark National Semiconductor Corporation. MultiSync trademark Nippon Electric Company (NEC). PanelLink technology licensed Chips Technologies, Inc. from Silicon Image, Inc. Palo Alto, PanelLink trademark Silicon Image, Inc. VESA registered trademark Video Electronics Standards Association. VL-Bus trademark Video Electronics Standards Association. Weitek registered trademark Weitek Inc. other trademarks property their respective holders. Disclaimer This document provides general information customer. Chips Technologies, Inc., reserves right modify information contained herein necessary customer should ensure that most recent revision document. CHIPS makes warranty products bears responsibility errors which appear this document. customer should notice that many different parties hold patents products, components, processes within personal computer industry. Customers should ensure that their products does infringe upon patents. CHIPS respects patent rights third parties shall participate direct indirect patent infringement.
Revision History
Revision History
Revision 0.11 0.13 0.15 0.17 0.18 Date 11/95 11/95 12/95 1/96 1/96 Comment Internal Draft. First Draft. Added identification. Removed PixelBlaster. Added signal mapping Bypass 18/24/36-bit mode. Added control signal mapping description 36-bit mode section. Added packaging diagrams. Added additional information Product Summary Section Added connects (N/C) 65101 description. Added further DE/Data edge description Data Capture Logic section 3.1. DCLK changed ODCK Panel Interface Logic section 4.1. Added CHIPS font formatting. Specifications. Modified Electrical Mechanical
2/96 3/96
Added diagrams. Revised according etc. Modified Mechanical Specifications. Signals were changed simplify interfaces between controller PanelLink CHIPSet. requirement removed. Modified functional diagrams. Added diagrams text. description feature changes. changes. Added drawings, functional description, DSTN panel support, more AC/DC specifications. Delete bypass mode.
4/96 5/96 7/96 12/96
65100 BYPASS TESTIN TESTOUT HALFCK SYNC_CONT SYNCOUT
65101 TESTIN BYPASS SYNCIN DGND HALFCK
Revision
12/18/96
Advance Product Information 65100/101 Subject change without notice
Table Contents
Table Contents
Revision History Table Contents.ii List Tables .iii List Figures.iv Features Introduction/Overview Description 65100 Diagram. 65101 Diagram. 65100 Functional Description. Data Capture Logic DC-Balanced Encoder Voltage Swing Adjust. Synchronization. 65101 Functional Description. Impedance Matching Circuit. Data Recovery Block. Channel Synchronization Block. Decoder Block. Panel Interface Logic Block Panel Interface Logic Color Interface (DF0 Low) Color DSTN Interface (DF0 High) Signal Mapping Electrical Specifications. Timing Diagrams Input Timing Output Timing Mechanical Specifications.
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12/18/96
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List Tables
List Tables
Table Panel Data Timing Falling Edge DCLK Table Input Data Timing Rising Edge DCLK. Table 8-Bit Un-Coded Data Transitions Number 8-Bit Codes Table 8-Bit Coded Data Transitions Number 8-Bit Codes. Table Coded Un-Coded Data Average Number Transitions. Table Differential Swing Level Relative REXT_RES Table Toggling Results. Table Color Color DSTN Panel Support Configuration Table Signal Mapping 12/18/24-Bits Pixel Mode. Table Signal Mapping 36-Bit Mode Table Absolute Maximum Conditions Table Normal Operating Conditions. Table CMOS Signals Characteristics. Table Differential Receiver (65101) Specifications. Table Differential Transmitter (65100) Specifications. Table Characteristics. Table 65100 Specifications Table 65101 Specifications
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12/18/96
Advance Product Information 65100/101 Subject change without notice
List Figures
List Figures
Figure PanelLink 65100 65101 Application Diagram. Figure Transmitter (65100) Diagram Figure Receiver (65101) Diagram Figure 65100 Functional Block Diagram Figure 65100 Timing Diagrams. Figure Control Signal Timing with Respect DCLK Figure Control Signals with Respect Timing Figure FLM, CLT[3:0] Sampling Figure Voltage Differential Voltage Swing Adjust Figure Voltage Differential Signal Adjustment. Figure SYNCOUT Timing with SYNC_CONT Tied HIGH (Phase Figure SYNCOUT Timing with SYNC_CONT Tied (Phase Figure 65101 Functional Block Diagram Figure Timing Diagram: Relationship Between DCLK Output Data, PIXS DCKINV Low. Figure Pixel/Clock Timing Color Panels with DCKINV Low. Figure Timing Diagram: Relationship Between DCLK Output Data, PIXS DCKINV High Figure Pixel/Clock Timing Color Panels with DCKINV Low. Figure Timing Diagram with Figure Timing Diagram with High. Figure DCLK Timing with High, PIXS Low, DCKINV Color DSTN Panels Figure DCLK Timing with High, PIXS Low, DCKINV High Figure DCLK Timing with High, PIXS High, DCKINV Color DSTN Panels. Figure DCLK Timing with High, PIXS High, DCKINV High Color DSTN Panels Figure Transmitter Small Signal Transition Times Figure Receiver Digital Output Transition Times Figure Transmitter/Receiver Clock Cycle/High/Low Times Figure Input Data Setup/Hold Times DCLK 65100 Figure FLM, CLT[3:0] Setup/Hold Times DCLK 65100 Figure FLM, CLT[3:0] Delay Times from 65100 Figure High/Low Times 65100. Figure SYNCOUT Timing 65100 with SYNC_CONT Figure SYNCOUT Timing 65100 with SYNC_CONT Figure Output Signals Disabled/Enabled Timing from Active/Inactive from 65100 Figure Output Data Delay from DCLK 65101 Figure Output Delay from DCLK 65101 Figure Output FLM, CLT[3:0] Delay from DCLK 65101. Figure Output Signals Disabled/Enabled Timing from Active/Inactive 65101 Figure Divide-by-2 DCLK Delay Timing from Internal DCLK Figure Divide-by-4 DCLK Delay Timing from Internal DCLK Figure Transmitter (65100) 64-Pin Plastic TQFP Figure Receiver (65101) 80-Pin Plastic TQFP
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12/18/96
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Features
Features
High Speed Serial Receiver Transmitter 65100 PanelLink Transmitter 65101 PanelLink Receiver Count Packages 64-pin TQFP 65100 80-pin TQFP 65101 High Speed Operation Three low-voltage swing differential data links capable transferring data MBytes/sec Impedance matching reduce noisy reflections Transition minimized coding reduce data edges Power core voltage operation Low-voltage swing differential transceiver/receiver power/low cost CMOS technology Power down mode Direct Interface CHIPS HiQVideoPortable Graphics Accelerator Family Compatible with many graphics controllers High Speed Trims jitter less than Flexible Panel Interface 65101 programmable 24-bit pixel/clock) 36-bit pixels/clock) panel interface control signals supported addition Display Enable (DE) High Integration Three low-swing differential data links transfer both data control signals clock link Display control signals transmitted without requiring additional data links Integrated with external components DC-Balanced Encoder 65100) Decoder 65101) Reliable Data Transmission Full Color High Resolution Display Supports 24-bit/pixel panel 16.7 colors/pixel) Supports 1024x768 Active Matrix Liquid Crystal Display (AMLCD) panels pixel clock
65100 Transmitter Data Pairs
65101 Receiver Data (24/36) Decoder
Data (24) Encoder Flat Panel Graphics Controller Serializer Controls
Data Recovery Panel Interface Clock Pair
Controls Panel Control ASIC Flat Panel
Clock (max MHz)
Clock
Figure PanelLink 65100 65101 Application Diagram
Revision
12/18/96
Advance Product Information 65100/101 Subject change without notice
Introduction/Overview
Introduction/Overview
Overview
PanelLink65100 65101 High Speed Digital Video/Graphics Interconnect CHIPSet that solve issues associated with high speed displays. Capable supporting true color Active Matrix Liquid Crystal Display (AMLCD) panels, transmitter (65100) takes parallel video/graphics data from host graphics controller transmits serially receiver (65101). PanelLink technology reduces system cost, minimizes board space requirements, reduces signal line count, most importantly, lowers EMI.
Design Flexibility
Using PanelLink technology, notebook designers motherboard panel interface design support resolutions from color depths bits pixel refresh rate. This provides CHIPS family graphics accelerators with common interface. addition, panel manufacturers choose either pixels clock cycle (Does this work?) half frequency output data pins 65101 receiver. 65101 transmit pixels clock (36-bit interface) 18-bit pixel modes reduce clock speeds. Also, control lines available supporting additional features that exist panel side.
Several leading edge design features this CHIPSet lower system EMI. receiver (65101) provides variable on-chip resistors lower cable/connector noise reflections cable/connector systems. 65101's variable resistance control feature allows notebook design engineers adjust receiving chip impedance match characteristic impedance cable/connector system used, significantly reducing noise reflections. addition, on-chip design both 65100 65101 limits noise motherboard. Since radiated proportional transmitted edges, reducing number edges transmitted data bytes another objective PanelLink design. This proprietary, patented encoding method reduce number transitions data byte. PanelLink solution reduces notebook board space requirements square inches eliminating need T-filters terminating resistors typically used reduction standard high speed digital systems such SVGA notebook.
Jitter Filtering
PanelLink design trims input jitter from graphics controller less than This filtering technique ensures high quality video/graphics data flat panel display.
Cost Long Distance Cable Fiber Optics
transmitter drive lower cost cables over longer distances since voltage swing adjustable higher levels, video/graphics data inherently DCbalanced. transformer coupling needed rive panels distant locations with different power sources than those host system. Additionally, coupling required before optical converters used optical fiber transmission video/graphics data over long distances. inherently DC-balanced signals ideal transformer coupling.
Skew Tolerant Transmission
prevent synchronization errors pixel "corruption," red, green, blue data channels reference clock line force synchronization after each display line transmitted flat panel display. Also, special signal forces synchronization transmitter receiver clocks minimize phase skew errors.
Power
operating reducing capacitance load drive requirements from graphics controller display, PanelLink technology consumes minimal power saves overall system power. Transition minimization reduce number edges transmitted, frequency PLL, power down (deep sleep) mode also lower power consumption. programmable interface voltage levels (3.3 allow matching voltage levels interface between graphics controller panel interface controller.
Compatibility
devices described this data sheet have their operation verified CHIPS using CHIPS graphics controllers. Other manufacturers' devices will readily interface with PanelLink technology. Before choosing particular graphics controller, verify that input clock jitter data set-up hold times compatible.
Revision
12/18/96
Advance Product Information 65100/101 Subject change without notice
Description
Description
65100 Diagram
65100 available 64-pin TQFP package, shown below.
DVCC
CLT0 CLT1 CLT2 CLT3 DEDGE CEDGE DCLK HALFCK SYNC_CONT PLLCK
SYNCOUT SUPV EXT_RES
65100 Transmitter 64-Pin TQFP
AGND
AGND
AGND
TXC+
AVCC
AVCC
TX0+
TX1+
PGND
PVCC
TX2+
TXC-
TX0-
TX1-
Figure Transmitter (65100) Diagram
Analog Output Digital Input Ground/Power Digital Output
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12/18/96
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TX2-
Description
65100 Description
Name Type Description Flat panel data bits P[23:0]. Data synchronized with pixel clock (DCLK). Data toggle when high. While low, data will transmitted. Data latched rising falling edges DCLK depending upon whether DEDGE high low, respectively.
SYNC_CONT
Synchronization Control. high level (3.3 selects phase clock synchronize Selecting level synchronizes phase clock. Should tied high normal operation. This signal TESTIN silicon prior ES3. note below. Clock latching edge data. level indicates that panel data (P[23:0]) latched falling edge DCLK while high level (3.3 V)high level indicates that data latched rising edge DCLK. note below. Clock latching edge display enable (DE) control signals (LP, FLM, CLT[3:0]). level indicates that display enable control signals latched falling edge DCLK while high level (3.3 V)high level indicates that display enable control signals latched rising edge DCLK. note below. Pixel clock. Data latched either falling rising edge DCLK selected DEDGE. Used internal PLL, this clock needs free running well constant frequency. maximum frequency minimum frequency MHz. duty cycle ratio should between 40/60 60/40. Input jitter must less than panel applications, this clock same SHFCLK output from controller. Display Enable. This signal qualifies active display area. positive minimum DCLK cycles. must
DEDGE
CEDGE
DCLK
Note: external pull-up pull-down resistor must connected pin.
Revision
12/18/96
Advance Product Information 65100/101 Subject change without notice
Description
65100 Description (Cont'd)
Name Type Description These control signals latched rising falling edge DCLK depending upon whether CEDGE high low, respectively. They toggle when low. While high, though, information will transmitted. Latch Pulse. Flat panel equivalent HSYNC. First Line Marker. Flat panel equivalent FLM. CLT[3:0] used transfer additional control signals. General input control signal General input control signal General input control signal General input control signal Selects whether differential output clock divided relative pixel clock. This signal BYPASS silicon prior ES3. selects divide-by-two mode. HIGH selects divide-by-1 mode. note below. Synchronization. Generated every force synchronization both transmitter receiver clocks. This signal TESTOUT silicon prior ES3. Synchronization phase determined SYNC_CONT pin. This signal TESTOUT silicon prior ES3. Input threshold voltage control signal. high level (3.3 indicates that input signal voltage level level indicates that input signal voltage level 3.3V. Should match DVCC voltage. note below. Power Down mode (active low). high level (3.3 indicates normal operation level indicates power down mode. During power down mode, data (P[23:0]), display enable (DE), clock (DCLK) control signals (LP, FLM, CLT[3:0]) input buffers disabled, analog logic powered down. This active during both normal operation test modes. note Table below. table shows state output pins Power Down mode.
CLT0 CLT1 CLT2 CLT3 HALFCK
SYNCOUT
SUPV
Note:
Name PLLCK SYNCOUT TXC+/TX0+/TX1+/TX2+/-
State TRI-STATE TRI-STATE TRI-STATE TRI-STATE
external pull-up pull-down resistor must connected pin. Pins graphics controller interface signal voltage must same.
Revision
12/18/96
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Description
65100 Description (Cont'd)
Name DVCC Type Power Description Power supply input display interface signals from graphics controller. This supplies power input protection devices. This must from input signals from 3.15 3.45 input signals notes below.
TX0+ TX0TX1+ TX1TX2+ TX2TXC+ TXC-
Ground Digital GND. Ground Ground Ground Analog voltage swing differential output data pairs. Analog Analog Analog Analog Analog Analog voltage swing differential output clock pair. Analog Voltage Swing Adjust. resistor between this AVCC will adjust differential signal voltage swing. relationship resistance voltage swing characterized follows: 0.5V (500 where differential voltage swing resistance EXT_RES pin.
EXT_ Analog
PVCC AVCC AVCC AGND AGND AGND PGND PLLCK Note:
Power Power Power Power Power Power
Analog VCC. Must from 3.15 3.45 note Additional core digital pin. Must 3.15 3.45 Note that revisions this will connected. note Core VCC. These pins supply power input buffers core digital logic must note Transmitter Analog VCC. Must 3.15 3.45 note
Ground Transmitter Analog GND. Ground Ground Ground Analog GND. Internal clock test characteristics. operating frequency 2.5x that DCLK.
Refer Signal Mapping (pages 20-21) description data coordination between data-in 65100 data-out 65101. Pins (all VCC) must have same setting.
Revision
12/18/96
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Description
65101 Diagram
Receiver (65101) available 80-pin TQFP package shown below. Output data currently limited bits; therefore, pixel/clock output data format, maximum number bits pixel pixel/clock output data format, maximum number bits pixel remains
EXT_RES HALFCK DCKINV Z0CONT
AGND
AGND
AVCC
AVCC
PGND
RXC+
PVCC
RX0+
RX1+
RX2+
RXC-
RX0-
RX1-
RX2-
PLLCK SYNCIN DGND PIXS CLT0 CLT1 CLT2 CLT3 DGND DVCC
DVCC DGND
65101 Receiver 80-Pin TQFP
DVCC
DCLK
DGND
Figure Receiver (65101) Diagram
Analog Output Digital Input Ground/Power Digital Output
Revision
12/18/96
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Description
65101 Description
Name RX0+ RX0RX1+ RX1RX2+ RX2RXC+ RXCHALFCK Type Description Analog voltage swing differential input data pairs. Analog Analog Analog Analog Analog Analog voltage swing differential input clock pair. Analog Analog Differential Half Clock selects whether differential input clock divided relative pixel clock. selects divide-by-2 mode. HIGH (3.3 selects divide-by-1 mode. Note that this This default value external resistor must used select modes. note below. Power Power Receiver Analog VCC. Must from 3.15 3.45
AVCC AVCC EXT_RES
Analog Impedance matching control pin. pull-up resistor cable impedance should connected this pin. case cable between 65100 65101, external 500- resistor should connected between this minimize signal reflection. relationship applies regardless Z0CONT setting. Ground Receiver Analog GND. Ground Power Analog VCC. Must from 3.15 3.45
AGND AGND PVCC PGND PIXS
Ground Analog GND. Pixel Select option. level indicates that output data pixel 24bit) clock high level (3.3 indicates that output data pixels 36-bit) clock color support. configurations color STN-DD panel support, please refer Table DCLK mask. level allows DCLK continuously high level (3.3 enables DCLK mask: DCLK stopped (LOW) when (Display Enable) low. note below. DCLK polarity selection. support level selects normal DCLK output; that output data controls synchronized rising edge DCLK (typically with panels that sample data falling edge clock). logic high level (3.3 selects inverted DCLK output. configurations DSTN panel support, please refer Table Note: silicon revisions prior this reserved.
DCKINV
Note: external pull-up pull-down resistor must connected this pin.
Revision
12/18/96
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Description
65101 Description (Cont'd)
Name Z0CONT Type Description Termination resistance range selection. logic level selects range logic high level (3.3 selects range These ranges apply each signal each differential pair. Note: silicon revisions prior this reserved. external pull-up pull-down resistor must connected this pin. Output Display Enable. Pixel Clock Output generated from RXC+/RXC-. panel applications, this SHFCLK panel. Panel data bits P[35:0] synchronized with pixel clock (DCLK). When PIXS P[35:24] driven output from P[23:0] bits/pixel data. When PIXS high, second pixel output from P[35:18] first pixel output from P[17:0].
DCLK
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Description
65101 Description (Cont'd)
Name CLT0 CLT1 CLT2 CLT3 PLLCK Type Description Latch Pulse. Flat panel equivalent HSYNC. First Line Marker. Flat panel equivalent VSYNC. General output control signal General output control signal General output control signal General output control signal Internal clock test characteristics. operating frequency 2.5x DCLK. Power Down mode (active low). high level (3.3 indicates normal operation level indicates power down mode. During power down mode, data (P[35:0]), display enable (DE), clock (DCLK) control signals (LP, FLM, CLT[3:0]) outputs driven low, internal clock stopped analog logic powered down. Synchronization. transmitter (65100) generates SYNCIN every force synchronization both transmitter receiver clocks. SYNC_CONT (pin Transmitter (65100) selects phase phase
SYNCIN
DGND DGND DGND DGND DVCC DVCC DVCC
Ground Additional ground DVCC. This signal BYPASS silicon prior ES3. Ground Ground pins DVCCs. These pins separated from digital Ground isolate potential noise output from core digital GND. Ground Power Power Power Power display interface output signals going into panel. This supplies power output buffers input protection devices. This must from input signals must from 3.15 3.45 input signals
Ground Additional core digital ground pin. Note that current revisions this will connected. Ground Core digital ground. Ground Power Power Power Additional core digital pin. Must from 3.15 3.45 Note that current revisions this will connected. Core digital VCC. These pins supply power input buffers core digital logic must from 3.15 3.45
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65100 Functional Description
65100 Functional Description
EXT_RES SUPV P[23:0] P[15:8] CLT0 CLT1 CLT2 CLT3 DEDGE CEDGE Q_CK2 P[23:16] TX2+ TX2DE Q_CK0 P[7:0]
Swing Control Circuit
Swing_Cont.
Encoder
TX0+ TX0-
Data Capture Logic
TX1+ TX1-
Encoder
Q_CK1
Encoder
SYNC_CONT HALFCK DCLK
P_CK
CHPLL
ECK[3:0]
TXC+ TXC-
DCLK
SYNCOUT
Figure 65100 Functional Block Diagram
above drawing indicates, 65100 consists data capture logic, three encoders, three transmitters, small swing clock transmitter, charge pump PLL, swing control circuit. data capture logic catches 24-bit data P[23:0], 6-bit control signals FLM, CLT[3:0]. Data control signals latched rising falling edge DCLK depending CEDGE DEDGE signal. When DEDGE signal HIGH (LOW), data latched rising (falling) edge DCLK. When CEDGE signal HIGH (LOW), control signals latched rising (falling) edge DCLK. combinations DEDGE CEDGE signals, output signals data capture logic synchronized transmitted encoder blocks.
Each encoder receives 8-bit data, 2-bit control signals, signal. When HIGH, 8-bit data converted 10-bit coded data which DC-free transition-minimized. transition-minimized, coded data guarantees power consumption during data transmission. When LOW, 2-bit control signals converted four 10-bit control characters. Functionally, 10-bit coded data sent each transmitter. transmitter converts 10-bit coded data into serial data stream whose maximum data rate Mbps. Mbps serial data transmitted through twisted pair cable. combined structure transmitter swing control circuit guarantees small swing data transmission with normal amplitude small swing data transmission guarantees high-speed, low-power operation significantly reduces EMI.
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65100 Functional Description
Data Capture Logic
following vertical horizontal timing diagrams Flat Panel Display Graphics Controllers demonstrate relationship between controller's output data (P[23:0]) 65100 Input Clock (DCLK):
Horizontal Timing:
ACTIVE DISPLAY BLANK TIME
HSYNC DCLK DCLK IDCK P[23:0] P[23:0] D[23:0]
HORIZONTAL DISPLAYED LINE HORIZONTAL BLANK
Vertical Timing:
VSYNC
HSYNC
VERTICAL DISPLAYED FRAME VERTICAL BLANK
Data Timing:
IDCK DCLK TSDF D[23:0] P[23:0] TSDR THDR THDF
Figure 65100 Timing Diagrams
above diagram signals shown with positive polarity. must always have positive polarity whereas other control signals (CLT0, CLT1, CLT2, CLT3) have either positive negative polarity. must always connected must minimum DCLK cycles, even DSTN panels. Transmitter (65100) relies polarity timing control signals.
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65100 Functional Description
DCLK IDCK
VSYNC, HSYNC, FLM, CLT[3:0] CLT[3:0] TSDR TSDF THDR THDF
DCLK IDCK Figure Control Signal Timing with Respect toDCLK
VSYNC, FLM, HSYNC, CLT[3:0] CLT[3:0] TDDF
VSYNC, FLM, HSYNC, CLT[3:0] CLT[3:0] TDDR
Figure Control Signals with Respect Timing above diagram signals shown with positive polarity. must always have positive polarity, whereas other control signals (CLT[3:0]) have either positive negative polarity. must always connected must minimum cycles, even DSTN panels. transmitter relies polarity timing control signals.
Display Enable (DE) signal used differentiate between "active" "non-active" (blank time) display areas. 65100 requires active high Display Enable (DE) signal. described earlier, there restriction polarity control signals; however, control signals only change during "blank" time. Pixel data P[23:0] Display Enable (DE) normally valid falling edge DCLK. Transmitter (65100) P[23:0] latched rising falling edge DCLK. data (P[23:0]), FLM, CLT[3:0] setup hold times must meet 65100 electrical timing specifications. Internal latching P[23:0], FLM, CLT[3:0] controlled DEDGE CEDGE pins. DEDGE controls latching data P[23:0]. When DEDGE low, P[23:0] must latched using falling edge DCLK. When DEDGE high, P[23:0] latched using rising edge DCLK. CEDGE controls latching control signals FLM, CLT0, CLT1, CLT2, CLT3. When CEDGE low, other control signals must latched using falling edge DCLK. When CEDGE high, other control signals must latched using rising edge DCLK. timing between P[23:0] with respect DCLK falling/rising edge requires close attention. Timing considerations between other control signals DCLK restrictive since panel timing requirements relaxed. most Flat Panel Display Graphics Controllers P[23:0] have same similar timing; therefore, DEDGE CEDGE need same level. However, P[23:0] latched using rising edge DCLK latched using falling edge DCLK, then will latched half clock cycle earlier with respect P[23:0]. Subsequently, P[23:0] synchronized output data capture logic (see 65100 timing diagram previous page). DCLK must always free running with 40/60 60/40 duty cycle less than jitter, even DSTN panels.
Table below specifies input timing data when they latched falling edge DCLK. Table below specifies input timing data when they latched therising edge DCLK.
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65100 Functional Description
Table Panel Data Timing Falling Edge DCLK Symbol TSDF THDF Parameter P[23:0] setup time from DCLK falling edge P[23:0] hold time from DCLK falling edge Unit
Table Input Data Timing Rising Edge DCLK Symbol TSDR THDR Parameter P[23:0] setup time from DCLK rising edge P[23:0] hold time from DCLK rising edge Unit
DC-Balanced Encoder
Each encoder unit encodes bits data during active display time. Display enable (DE) bits control signals encoded during blanking time (when low). Three functionally identical encoders used transmit data control signals. encoder generates 10-bit DC-balanced codes. Control signals assumed change only during "blank" time when low/inactive; therefore, level control signals assumed constant during active data area when high. innovative PanelLink encoding method guarantees transition-minimized DC-free data codes support power operation guarantee DC-balancing. Four kinds special, proprietary characters used level encoding control signals include sufficient number transitions phase synchronization receiver. characters contain byte-sync information. encoding scheme supports existing future function transitionminimized data codes.
maximum number transitions possible with this encoding scheme 8-bit coded data three while 10-bit coded data five. minimum number transitions possible been theoretically shown that average number transitions random data patterns 8-bit coded data 2.41 while 10-bit coded data 3.41. This comparison 8-bit un-coded data which maximum number transitions minimum average 3.5. Therefore, PanelLink technology reduce number transitionsup random data patterns.
Table 8-Bit Un-Coded Data Transitions Number 8-Bit Codes
8-bit Un-Coded Data Transitions 8-Bit Codes Total
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65100 Functional Description
Table 8-Bit Coded Data Transitions Number 8-Bit Codes
8-bit Coded Data Transitions 8-Bit Codes Total
Table Coded Un-Coded Data Average Number Transitions
Number Transitions 8-bit Uncoded Data 8-bit Coded Data 10-bit Coded Data Maximum Minimum 2.41 3.41 Average *Note directly related each other. Therefore average using random data, following equations shows percentage reduction number transitions from 8-bit un-coded data 8-bit coded data 10-bit coded data. [(3.5 2.41) 3.5] {[(3.5/8) (3.41/10)] (3.5/8)} 31.96% 22.06% 8-bit Coded Data compared with 8-bit Uncoded Data 10-bit Coded Data compared with 8-bit Uncoded Data
encoder generates special synchronization characters depending upon level (CLT0 CLT1, CLT2 CLT3), when LOW. From special synchronization characters, digital Receiver (65101) achieves phase, byte, inter-channel synchronization. That special synchronization characters contain word boundary information. Transparent Latch Transparent Latch Opened FLM, Opened HSYNC, CLT[3:0] CLT[3:0] VSYNC,
IDCK DCLK
Transparent Latch Closed Transparent Latch Closed Latched Latched HSYNC, FLM, CLT[3:0] VSYNC, CLT[3:0]
HSYNC, FLM, VSYNC, CLT[3:0] CLT[3:0]
FLM, HSYNC, VSYNC, CLT[3:0] signals sampled each CEDGE rising/falling clock edge depending upon setting DEDGE.
Figure FLM, CLT[3:0] Sampling
Voltage Swing Adjust
voltage difference between AVCC EXT_ determines voltage swing differential signal pairs. Therefore, this adjustable voltage differential swing used various cable lengths. larger voltage
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65100 Functional Description
swing would used longer cables, lower voltage swing would used shorter cables. Sometimes larger voltage swings cause noise shorter cables transmission line effects. Therefore absolutely necessary adjust voltage swing accordingly length type cable. larger voltage swing, higher power consumption the65100/101 pair system. EXT_RES left unconnected, internal voltage divider circuit will EXT_RES approximately 2.8V when AVCC producing approximately swing differential signal pairs. (Please Figure below.) differential voltage level swing single ended formula: VSWING 0.5V (500/REXT_RES where VSWING REXT_RES Single Ended Differential voltage swing External Resistor EXT_RES
Table Differential Swing Level Relative REXT_RES
(RPOT1)
1,000
(Theoretical Calculation) (mV)
2,500 1,250
Note: Recommended Normal Operation.
AVCC
REXT_TERM REXT-RES
AVCC AVCC
REXT_SWING REXT-RES
Termination Control
Data
Swing Control Transmitter SiI100 (65100) (Transmitter)
SiI101 Receiver (Receiver) (65101) (65100) represents characteristic impedance line cable. represents characteristic impedance line cable. REXT_RES controls level swing differential pairs. REXT_SWING controls level swing differential pairs. REXT-RESVSWING 0.5V (500/REXT_RES VSWING 0.5V*(500W/REXT_SWING) REXT_RES controls termination resistance differential line. REXT_TERM controls termination resistance differential line. RTERM REXT_RES/10 RTERM REXT_TERM/10
Figure Voltage Differential Voltage Swing Adjust
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65100 Functional Description
seen from above figure, PanelLink technology uses current drive develop voltage differential signal receiver side transmission line. Receiver (65101) Termination Resistance description described section impedance matching circuit. Figure below shows that high voltage level voltage differential signals will AVCC, while voltage adjustable with voltage differential swing control circuit. Therefore, voltage differential voltage swing adjustable using potentiometer EXT_RES shown Figure
Adjustable Voltage Swing pull-up resistance between 65100 EXT_RES used adjust voltage swing differential signals. larger voltage swing, more reliable transmission system. result, longer cables used. However, larger voltage swing, higher power consumption 65100 65101. Adjustable Receiver Impedance order balance impedance over transmission lines between 65100 65101, control mechanism (EXT_RES) included 65101 minimize producing effects. characteristic impedance cable then needs connected between 65101 EXT_RES VCC.
AVCC
VSWING REXT-RES EXT_SWING
AVCC determines high voltage level Voltage Differential Signals. REXT_SWING determines voltage voltagethe Voltage Differential Signals. REXT_RES determines level level Voltage Therefore SWING determined Differential Signals. Therefore SWING determined VSWING AVCC (Voltage EXT_SWING
VSWING AVCC (Voltage byREXT_RES)
Figure Voltage Differential Signal Adjustment
Synchronization
Transmitter (65100) generates synchronization signal called SYNCOUT that will force clocks transmitter receiver synchronize. SYNCOUT signal generated every FLM. SYNCOUT signal synchronized phase phase internal clock determined SYNC_CONT pin. Phases refer opposite states internal divide-by-two flip-flop that part design. phase verified observing phase relationship between 2.5x clock output signals transmitter receiver. SYNC_CONT low, then SYNCOUT synchronized phase SYNC_CONT high (3.3V), then SYNCOUT synchronized phase SYNCOUT should tied high normal operations. This signal used minimize phase errors between transmitter receiver clocks that causing data errors during transmission reception.
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12/18/96
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65100 Functional Description
VSYNC SYNCOUT PLL_SYNC Figure SYNCOUT Timing with SYNC_CONT Tied HIGH (Phase
VSYNC SYNCOUT PLL_SYNC Figure SYNCOUT Timing with SYNC_CONT Tied (Phase
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12/18/96
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65101 Functional Description
65101 Functional Description
following figure shows 65101 functional block diagram:
PIXS DCKINV
Z0CONT Ext_Res Impedance Matching Circuit
Sync
Sync
CLT3 CLT2
P[35:0] DCLK
DATA RECOVERY
Sync
CHANNEL SYNC
Sync
DECODER
CLT1 CLT0
PANEL INTERFLM FACE LOGIC
Sync
Sync
HALFCK SYNCIN
CHPLL
Figure 65101 Functional Block Diagram
65101 consists five blocks: Impedance Matching Circuit, Data Recovery, Channel Synchronization, Decoder, Panel Interface. value EXT_RES resistor which will internal VCRs Then VCR's internal termination resistors.
Impedance Matching Circuit
minimize impedance matching circuit (see next section) controls channels, each with Voltage Controlled Resistor (VCR). impedance matching circuit equalizes impedance VCRs characteristic impedance transmission lines. EXT_RES should connected through resistor, this resistor value should times desired receiver termination resistor. Internal VCR's (Voltage Controlled Resistor) controlled impedance matching circuit adjusted have resistor value equivalent required termination resistance. recommended Revision 12/18/96
Data Recovery Block
Data Recovery Block receives small swing differential signal with maximum data rate Mbps from twisted pair cable. period horizontal vertical blank LOW), four special characters received which have sufficient number transitions guarantee phase byte synchronization. Data Recovery Block accomplishes phase synchronization finds frame from special characters. result, Data Recovery Block recovers 10-bit parallel data synchronized MHz.
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65101 Functional Description
Channel Synchronization Block
During "blanking" time, 65101 designed recover from synchronization error.
Decoder Block
Decoder Block receives 10-bit data synchronization signals from Channel Synchronization Block, then decodes data 8-bit data, 2-bit control signals (Display Enable) signal.
Panel Interface Logic Block
Panel Interface Logic receives bits data, 6-bit control signals 3-bit signals from Decoder Block. 65101 configured modes PIXS pin: 24-bit data with bits pixel 36-bit data with bits pixel). When PIXS LOW, panel interface logic generates bits data with bits pixel synchronized DCLK. When PIXS HIGH, panel interface logic generates bits data with bits pixel 32.5 DCLK. Both panel interface configurations send control signals well.
During Blanking Time DSTN panels require DCLK must high modifies output data follows.
Table Toggling Results Description Normal mode DCLK runs continuously (TFT) DCLK stopped (low) when (DSTN)
Panel Interface Logic
panel interface logic takes output data from Decoder Block formats data output panel. decoder generates three sets data using three clocks. Because clocks distributed symmetrically, these clocks have very small skew aligned with DCLK. mentioned previously, output data format determined state PIXS, DCKINV, pins. Table Color Color DSTN Panel Support Configuration
PIXS
DCKINV
PANEL DSTN NONE DSTN DSTN
DCLK Divide Masked during Blank Time Low) Inverted Divide Masked High during Blank Time Low) Divide Masked during Blank Time Low) Divide Masked during Blank Time Low) pixel/clock mode withcontinuous running clock Inverted pixel/clock mode withcontinuous running clock pixel/clock mode withcontinuous running clock Inverted pixel/clock mode withcontinuous running clock
Color Interface (DF0 Low)
When PIXS DCKINV pins both low, output data from decoder latched rising edge DCLK. output data format bits DCLK P[23:0] pins. rising edge DCLK used output data control signals. following timing diagram shows relationship between DCLK output data format timing when PIXS DCKINV pins low.
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12/18/96
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65101 Functional Description
DCLK ODCK
P[35:24] Q[35:24]
P[23:0] Q[23:0]
FIRST DATA
SECOND DATA
THIRD DATA
Figure Timing Diagram: Relationship Between DCLK Output Data, PIXS DCKINV
Internal ODCK DCLK
DCLK ODCK
P[35:24] Q[35:24]
P[23:0] Q[23:0]
FIRST DATA
SECOND DATA
THIRD DATA
Figure Pixel/Clock Timing Color Panels withDCKINV
When DCKINV high, DCLK signal inverted timing relationship shown above still valid. When PIXS high DCKINV low, DCLK generated dividing this mode, output data format bits DCLK bits pixel. this configuration, least significant bits each byte output data discarded (not used). first pixel 18-bit data pins P[17:0] second pixel 18-bit data pins P[35:18] shown below.
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12/18/96
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65101 Functional Description
Internal DCLK
DCLK ODCK
P[35:18] Q[35:18]
SECOND DATA
FOURTH DATA
P[17:0] Q[17:0]
FIRST DATA
THIRD DATA
Figure Timing Diagram: Relationship Between DCLK Output Data, PIXS DCKINV High
When DCKINV high, DCLK would just inverted timing relationship shown above would still valid. will modify output DCLK when (Blank Time). compatible with panels, DCLK runs continuously when tied low. compatible with STN-DD panels, DCLK inactive (low) when high low. This relationship shown timing diagrams below.
Internal ODCK DCLK
DCLK ODCK
P[35:24] Q[35:24] P[23:0] Q[23:0]
SECOND DATA FIRST DATA
FOURTH DATA THIRD DATA
Figure Pixel/Clock Timing Color Panels with DCKINV
ODCK
HSYNC
Figure Timing Diagram with
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65101 Functional Description
DCLK ODCK
HSYNC Figure Timing Diagram with High
Color DSTN Interface(DF0 High)
following timing diagrams generated Color DSTN panel support defined above table.
Internal ODCK DCLK
DCLK ODCK
Figure DCLK Timing with High, PIXS Low, andDCKINV Color DSTN Panels
Internal ODCK DCLK ODCK DCLK
Figure DCLK Timing with High, PIXS Low, andDCKINV High above setting should used Color DSTN panel support since DCLK high during (blank time).
Internal DCLK DCLK ODCK
DCLK ODCK Figure DCLK Timing with High, PIXS High, andDCKINV Color DSTN Panels
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12/18/96
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65101 Functional Description
Internal ODCK DCLK ODCK DCLK
Figure DCLK Timing with High, PIXS High, andDCKINV High Color DSTN Panels
Signal Mapping
Table shows that transmitted CHANNEL CLT0 CLT1 transmitted CHANNEL CLT2 CLT3 transmitted CHANNEL Data sent during active display time while control signals sent during blank time.
Table Signal Mapping 12/18/24-Bits Pixel Mode
65100
CHANNEL (blue) P[7:4] P[15:12] CLT0 CLT1 P[23:20] CLT2 CLT3 P[7:2] P[15:10] CLT0 CLT1 P[23:18] CLT2 CLT3 P[7:0] P[15:8] CLT0 CLT1 P[23:16] CLT2 CLT3 P[7:4] P[15:12] CLT0 CLT1 P[23:20] CLT2 CLT3
65101
P[7:2] P[15:10] CLT0 CLT1 P[23:18] CLT2 CLT3 P[7:0] P[15:8] CLT0 CLT1 P[23:16] CLT2 CLT3
CHANNEL (green)
CHANNEL (red)
Note
data mapping less than 24-bit pixel interfaces justified. 18-bit mode, Graphics Controller interface with 65100 matches 24-bit mode; however, bits channel (color) transmitted instead recommended that unused data bits tied low.
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65101 Functional Description
36-bit panels, following table represents sequence pixels sent from Graphics Controller 65100 transmitter 18-bit data (one pixel clock). data then transmitted 65101 receiver DC-free, transition minimized data. After data received with 65101, 18-bit pixels transferred panel clock cycle. Table Signal Mapping 36-Bit Mode
65100 (pixel
CHANNEL (blue) CHANNEL (green) CHANNEL (red) clock P[7:2] P[15:10] P[23:18] clock [N+1] P[7:2] P[15:10] P[23:18] clock [N+2] P[7:2] P[15:10] P[23:18] clock [N+3] P[7:2] P[15:10] P[23:18]
65101
clock P[5:0] P[11:6] P[17:12] clock P[23:18] P[29:24] P[35:30] clock[N+1] P[5:0] P[11:6] P[17:12] clock[N+1] P[23:18] P[29:24] P[35:30]
(pixel
CHANNEL (blue) CHANNEL (green) CHANNEL (red)
(pixel
CHANNEL (blue) CHANNEL (green) CHANNEL (red)
(pixel
CHANNEL (blue) CHANNEL (green) CHANNEL (red)
Note: 36-bit mode, DCLK frequency 65100 that 65101 clock. LSBs 8-bit decoded data will ignored generate (3x6) pixels. indicated above mapping table, first pixel (Pixel received through P[17:0] second pixel (Pixel received through P[35:18]. Similarly, even-numbered pixels received through P[17:0], odd-numbered pixels received through P[35:18]. LP/FLM transmitted through Channel CLT0/CLT1 transmitted through Channel CLT2/CLT3 transmitted through Channel seen from above table, data mapping less than 18-bit panel interfaces justified.
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65101 Functional Description
(Blank Page)
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Electrical Specifications
Electrical Specifications
values included following tables were made available CHIPS Silicon Image, Inc. Palo Alto, Table Absolute Maximum Conditions Symbol TSTG Parameter Supply Voltage Supply Voltage Input Voltage Output Voltage Ambient Temperature (with power applied) Storage Temperature Package Power Dissipation -0.3 -0.3 -0.3 -0.3 Typical Units
Notes: Permanent device damage occur Absolute Maximum Conditions exceeded. Functional operation should restricted conditions described under Normal Operating Conditions. Table Normal Operating Conditions Symbol VCC3 VCC5 Parameter Supply Voltage Supply Voltage Ambient Temperature (with power applied) 3.15 Typical 3.45 70.0 Units
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12/18/96
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Electrical Specifications
following table values refers normal operating conditions unless specified otherwise. Table CMOS Signals Characteristics Symbol Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input Clamp Voltage Input Current Input Leakage Current Output Short Circuit Current Conditions SUPV SUPV DVCC 3.3V DVCC 5.0V -18mA VCC, DVCC 3.3V VOUT Data VOUT 3.3V, Data VOUT Clock VOUT 3.3V, Clock DVCC 5.0V VOUT Data VOUT Data VOUT Clock VOUT Clock High Impedance Note below. -100 Typical +/-5 VCC+0.3 VCC+0.3 Units
0.25 -1.1 +/-12 10.4 21.3 23.4 37.5 20.7
Output Leakage Current Power-down Current
Notes: minimum power-down current, CMOS inputs must either GND. following three tables values refer normal operating conditions unless specified otherwise. Table Differential Receiver (65101) Specifications
Symbol Parameter Conditions Units
IOHD IOLD IOHC IOLC ICCR
High-level Output Voltage Low-level Output Voltage Output High Drive Output Drive Output High Drive Output Drive Differential Input Voltage Receiver Supply Current 3.3V
VOUT Data Controls VOUT Data Controls VOUT DCLK VOUT DCLK DCLK DCLK
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Electrical Specifications
Table Differential Transmitter (65100) Specifications Symbol ICCT Parameter Differential Output Voltage High-level Output Voltage Low-level Output Voltage Output Short Circuit Current Output Tri-State Current Transmitter Supply Current 3.3V Power-down Current Conditions VOUT VOUT DCLK DCLK Note below. Typical 3.25 2.78 2.97 Units
Note: minimum power-down current, CMOS inputs must either GND. Table Characteristics Symbol SLHT SHLT DLHT Parameter Small Swing Low-to-High Transition Time Small Swing High-to-Low Transition Time Digital Output Low-to-High Transition Time Conditions DVCC Data DVCC Data DVCC Clock DVCC Clock DVCC Data DVCC Data DVCC Clock DVCC Clock Typical Units
0.4T 0.4T 0.4T 0.4T
0.5T 0.5T 0.5T 0.5T
0.6T 0.6T 0.6T 0.6T
DHLT
Digital Output High-to-Low Transition Time
TCIP TCIH TCIL RCIP RCIH RCIL
DCLK Cycle Time DCLK High Time DCLK Time DCLK Cycle Time DCLK High Time DCLK Time DCLK jitter requirement
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Electrical Specifications
Table 65100 Specifications
Symbol Parameter Conditions Units
TSDF THDF TSDR THDR TDDF TDDR THDE TLDE TPH1 TPH2 TLPS TLPD THPD
Data, FLM, CLT[3:0] Setup Time from DCLK falling edge Data, FLM, CLT[3:0] Hold Time from DCLK falling edge Data, FLM, CLT[3:0] Setup Time from DCLK rising edge Data, FLM, CLT[3:0] Hold Time from DCLK rising edge FLM, CLT[3:0] Delay from falling edge FLM, CLT[3:0] Delay from rising edge high time time SYNCOUT Delay from asserted (Phase SYNCOUT Delay from asserted (Phase SYNCOUT Delay from de-asserted Delay from Active Outputs Disabled Delay from Inactive Outputs enabled
CEDGE DEDGE CEDGE DEDGE CEDGE DEDGE CEDGE DEDGE
8000T
SYNC_CONT SYNC_CONT
2T+7 2T+7
Table 65101 Specifications
Symbol Parameter Conditions Units
TOCKDER
TOCKDEF
TPDL TPDH TD2D TD4D
Time delay from rising edge DCLK DCKINV 15pF Data, FLM, CLT[3:0] 65101 Time delay from falling edge DCLK DCKINV 15pF Data, FLM, CLT[3:0-0] 65101 Delay from Active Outputs Disabled Delay from Inactive Outputs Enabled Delay Divide DCLK Internal DCLK Delay Divide DCLK Internal DCLK
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Timing Diagrams
Timing Diagrams
SLHT
SHLT
Figure Transmitter Small Signal Transition Times
65101 SiI101
15pF
DLHT
DHLT
Figure Receiver Digital Output Transition Times
TCIP RCIP TCIH RCIH
TCIL RCIL
Figure Transmitter/Receiver Clock Cycle/High/Low Times
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12/18/96
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Timing Diagrams
Input Timing
IDCK DCLK TSDF P[23:0] D[23:0] TSDR THDR THDF
Figure Input Data Setup/Hold Times toDCLK 65100
DCLK IDCK
VSYNC, FLM, HSYNC, CLT[3:0] CLT[3:0] TSDR TSDF THDR THDF
DCLK IDCK Figure FLM, CLT[3:0] Setup/Hold Times toDCLK 65100
VSYNC, FLM, HSYNC, CLT[3:0] CLT[3:0] TDDF
VSYNC, FLM, HSYNC, CLT[3:0] CLT[3:0] TDDR
Figure FLM, CLT[3:0] Delay Times from of65100
THDE
TLDE
Figure High/Low Times of65100
VSYNC TPH1 PLL_SYNC SYNCOUT TLPS
Figure SYNCOUT Timing 65100 with SYNC_CONT
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Timing Diagrams
VSYNC
TPH2 PLL_SYNC SYNCOUT TLPS
Figure SYNCOUT Timing 65100 with SYNC_CONT
TLPD TX0,TX1, TX2,TXC PLLCK, PLL_SYNC SYNCOUT HI-Z HI-Z THPD
Figure Output Signals Disabled/Enabled Timing from Active/Inactive from 65100
Output Timing
ODCK DCLK TOCKDER Q[35:0] P[35:0] TOCKDEF ODCK DCLK
Figure Output Data Delay fromDCLK 65101
ODCK DCLK TOCKDER TOCKDEF ODCK DCLK
Figure Output Delay fromDCLK 65101
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12/18/96
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Timing Diagrams
ODCK DCLK VSYNC, LPHSYNC, CLT[3:0] CLT[3:0] ODCK DCLK TOCKDER TOCKDEF
Figure Output FLM, CLT[3:0] Delay fromDCLK 65101
Q[35:0],DE, P[35:0], VSYNC,HSYNC, FLM, CLT[3:0],PLLCK CLT[3:0], PLLCK TPDL TPDH
Figure Output Signals Disabled/Enabled Timing from Active/Inactive 65101
Internal Internal DCLK ODCK TD2D ODCK DCLK Figure Divide-by-2 DCLK Delay Timing from InternalDCLK
Internal Internal ODCK DCLK ODCK DCLK
TD4D
Figure Divide-by-4 DCLK Delay Timing from InternalDCLK
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12/18/96
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Mechanical Specifications
Mechanical Specifications
Lead Length Lead Width 0.22 Lead Pitch 0.50
MARKING
Body Size 10.00 1.20
CHIPS Part Revision Date Assembly Code
T65100
YYWW
BOTTOM MARKING
Vendor Code
TMXXXXX
XXXXXXX.X
Body Thickness 1.00 Clearance Body Size 10.00 Footprint 12.00 Figure Transmitter (65100) 64-Pin Plastic TQFP
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12/18/96
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Footprint 12.00
Mechanical Specifications
Lead Length Lead Width 0.22 Lead Pitch 0.50
MARKING
Body Size 12.00 1.20
CHIPS Part Revision Date Assembly Code
T65101
YYWW
BOTTOM MARKING
Vendor Code
TMXXXXX
XXXXX.X
Body Thickness 1.00 Clearance Body Size 12.00 Footprint 14.00
Figure Receiver (65101) 80-Pin Plastic TQFP
Revision
12/18/96
Advance Product Information 65100/101 Subject change without notice
Footprint 14.00
Chips Technologies, Inc. 2950 Zanker Road Jose, California 95134 Phone: 408-434-0600 FAX: 408-894-2080
65100/101 PanelLink Technology High Speed Transmitter Receiver Publication No.: API33.5 Stock No.: 011033-005 Revision No.: Date: 12/18/96 Title:
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