22-Bit, Multi-Channel Chip Delta-Sigma Architecture: Order Modula

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22-Bit, Multi-Channel Chip Delta-Sigma Architecture: Order Modula

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CS5542 CS5543
22-Bit, Multi-Channel Chip
Delta-Sigma Architecture: Order Modulator 22-Bit Resolution Accuracy (fBW 250Hz): Integral Linearity: 0.001 F.S. Differential Linearity: LSBs Noise: pARMS Selectable Input Range: Full Scale 8-Channel Digital Filter Self-calibration Offset Gain Power: 8-ch system
CS5542 CS5543 chip designed complete current measurement data acquisition system. CS5542 22-Bit, 2-channel, 5th-order delta sigma modulator. CS5543 monolithic CMOS, 8-channel digital filter designed used with four CS5542's forming 8-channel system. complete system capable cascading 1024 channels. system supports 22-bit measurement resolution with output conversion rates channel. JTAG boundary-scan capability available facilitate self-test system level. Potential applications CS5542/CS5543 system environmental monitoring, process control systems, color sensing, light measurement, chemical analyzers photo-diode transducer applications.
ORDERING INFORMATION CS5542-KL 70°C CS5543-KL 70°C
28-pin PLCC 28-pin PLCC
VD1+ GND1
VD2+ GND2 VD3+
GND3
GNDL
DGND
REFGNDL Order Delta-Sigma Modulator Left Channel CAPSIZE
CAPSIZE MCLK FSYNC [2:0] CAL[1:0]
DMODE [2:0] CLKIN FEGAIN DATSEL [3:0]
Control/Sequencing
Test Access Port
ICAL
ICAL
BIAS REGULATOR
CALIBRATION DIGITAL CONTROL LOGIC
MCLK FSYNC CAL[1:0] MDATA[3:0]
C[2:0]
MDATA [3:0]
REFGNDR VREF+
VREF-
ilte
Order Delta-Sigma Modulator Right Channel
yste
GNDR
SEL0
SEL1
DATACLK FRAME
Serial
DATAIN [3:0] DATAOUT [3:0]
CS5542
CS5543
Preliminary Product Information
Crystal Semiconductor Corporation P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581
This document contains information product. Crystal Semiconductor reserves right modify this product without notice.
Copyright Crystal Semiconductor Corporation 1996 (All Rights Reserved)
DS109PP2
CS5542 CS5543 ANALOG CHARACTERISTICS:
Parameter Specified Temperature Range Accuracy Full Scale Input Current (Bipolar) CAPSIZE=0 CAPSIZE=1 Dynamic Range CAPSIZE=0 CAPSIZE=1 Differential Nonlinearity Integral Nonlinearity Full Scale Error Full Scale Drift System Offset Calibration Range Offset Drift Power Supplies Consumption Active Powerdown Power Supply Rejection: (Notes Fullscale Current Fullscale Current 2500 1.88 15.3 nA/V nA/V 1.85 13.5 nA/V nA/V Missing Codes) (Note (Note (Note (Note (Note (Note (Note (Note (Note ±0.3 0.001 Bits ppm/°C LSB/°C (Note (Note 2500 VA+, ±5%; ±5%; GNDL,GNDR, DGND= 0V;VREF+ VREF- MCLK frequency noted.) Units
Notes: Full scale current tested under conditions: CAPSIZE (CDAC with MCLK 1.024 CAPSIZE (CDAC with MCLK 2.048 MHz. Dynamic Range (Signal-to-Noise) tested with sine wave voltage driven into input resistor with capacitor connected from REFGNDR REFGNDL respectively, test each modulator. integral nonlinearity tested with CAPSIZE (CDAC with MCLK 2.048 CAPSIZE (CDAC with MCLK 1.024 MHz. Guaranteed design characterization. Specification applies after complete calibration sequence using CS5542/CS5543 combination. Drift specification CS5542/CS5543 only does include drift input components, VREF voltage, frequency change CLKIN. Specification applies only System Offset Calibration using CS5542/CS5543 chip combination after Input Offset Voltage calibration been completed with external offset applied input. supplies should quiet supplies (see data sheet text). Power supply sequence important. supplies should applied CS5542 prior same time supply. Power supply rejection tested with mVp-p sine wave applied each supply. data sheet text power supply noise requirements.
DS109PP2
CS5542 CS5543
SLOT6 (Previous Frame)
MCLK
SLOT7 (Previous Frame)
SLOT0
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
(2048 OWR)
FRAME CHANNELS SLOT-PAIRS
FSYNC (Modulator Rate) CHIP ACTIVE (Previous Frame) CHIP ACTIVE SLOT PAIR CHIP ACTIVE SLOT PAIR CHIP ACTIVE SLOT PAIR CHIP ACTIVE SLOT PAIR
MDATA3:0
INTER-CHIP HANDOFF POINT
CS5542 Frame Timing Overview
SLOT PAIR
MCLK
MDATA[3:0]
HI-Z STATE (Note
LEFT DATA
RIGHT DATA
HI-Z STATE (Note
Notes Hi-Z State shown intermediate level clarity only. capacitance would normally maintain valid logic level during Hi-Z until next time slot pair becomes active.
CS5542 MDATA3-MDATA0 Output Timing Characteristics
DS109PP2
CS5542 CS5543 CS5542 CS5543 SYSTEM SWITCHING CHARACTERISTICS: (TA= 25°C, VD1+
Parameter CS5542 Modulator Timing MCLK Frequency MCLK Duty Cycle FSYNC Frequency FSYNC set-up before MCLK rising edge FSYNC hold time after MCLK rising edge MCLK rising MDATA[3:0] valid MCLK rising MDATA[3:0] high MCLK falling MDATA[3:0] Hi-Z MCLK falling MDATA[3:0] active CS5543 System Timing CLKIN Frequency CLKIN Duty Cycle DATACLK Frequency DATACLK Duty Cycle FRAME rising CLKIN rising FRAME rising next DATACLK rising FRAME period CLKIN rising MCLK rising CLKIN falling MCLK falling CS5542 /CS5543 Interface FSYNC period MCLK falling FSYNC rising falling CS5543 CS5543 Interface DATACLK rising DATAOUT valid DATAIN set-up time before DATACLK rising DATAIN hold time after DATACLK rising 7.81 (1/Clock Period) (1/Clock Period) 1.024 3.072 2.048 6.144 1.024 MCLK/ 2.048 Number
VD2+ VD3+ ±5%; GND1 GND2 GND3 timing parameters: CLKIN= 2.048 MHz; DATACLK 6.144 MHz; MCLK 2.048 MHz; Outputs loaded with pF.) Units
DS109PP2
CS5542 CS5543
DATACLK
TCK, CLKIN FRAME DATAIN [3:0] DATAOUT [3:0] valid data valid data
DMODE [2:0], DATSEL[3:0], JTAG pins, FEGAIN MCLK FSYNC
CS5542/CS5543 System Timing Diagram
Output Word Cycle
Filter Output Time FRAME
CLKIN
DATACLK
DATAOUT [3:0]
Expanded inter-view timing FRAME
CLKIN
DATACLK DATAOUT [3:0] parity from "most remote" channel (end Frame N-3) sign from "nearest" channel (beginning Frame N-2)
Multi-Frame System Timing Diagram
DS109PP2
CS5542 CS5543 CS5543 FILTER CHARACTERISTICS: (TA=
Parameter Passband Frequency Equivalent Noise Bandwidth Stop Band Stop Band Rejection Stop Band Rejection Group Delay Group Delay Frequency (Linear Phase) Decimation Ratio (CS5543 input output) (CS5543 only) (CS5542/43 Combination) 0.016 3/OWR 25°C, VD1+ VD2+ VD3+ ±5%; GND1 GND2 GND3 Output Word Rate (OWR) CLKIN/2048) 0.536 0.536 Units
DS109PP2
CS5542 CS5543
-120
H(z),
-150
-180
-210 -240
-270
-300
Normalized Modulator Sample Frequency
Modulator Sample Frequency MCLK/16; Output Word Rate MCLK/2048 Digital Filter Total Response
-0.0
-0.3 -0.6
-0.9
-1.2
H(z),
-1.5
-1.8
-2.1
-2.4
-2.7 -3.0
Normalized Output Word Rate
CS5543 Digital Filter Passband Response
DS109PP2
CS5542 CS5543 CS5542 DIGITAL CHARACTERISTICS: 25°C, ±5%; DGND Output loaded
with Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout 600µA) Low-Level Output Voltage (Iout 800µA) Input Leakage Current (All pins except Logic Input Leakage Current only, Logic Output Leakage Current Digital Input Capacitance Digital Output Capacitance Symbol Iout Cout -1.0 -0.4 Units
CS5542 RECOMMENDED OPERATING CONDITIONS: (GNDR GNDL REFGNDR
REFGNDL DGND Parameter Operating Voltages Positive Analog Negative Analog Positive Digital VREF+ VREFVA+ VAVD+ VREF+ VREF4.75 -4.75 4.75 -2.0 -5.0 -4.0 +5.25 -5.25 +5.25 -4.1 Symbol Units
CS5542 ABSOLUTE MAXIMUM RATINGS*: (Voltages with respect
Parameter Source Transient Voltage into inputs Source Transient Current into inputs Operating Voltages Positive Analog Negative Analog Positive Digital Input Current, Except Supplies Digital Input Voltage Storage Temperature VAVD+ VIND Tstg -0.3 +0.3 -0.3 -6.0 (VA+)+0.3 (VD+)+0.3 (Note Symbol 1000 Units
Notes: Transient model through 1500 source resistance. *Warning: Operation beyond these limits result permanent damage device Normal operations guaranteed these extremes
DS109PP2
CS5542 CS5543 CS5543 POWER SUPPLY:
GND1 GND2 GND3 Parameter Consumption Active Powerdown 1700 Symbol Units 25°C; CLKIN 2.048 MHz; DATACLK 6.144 MHz, 5.25
CS5543 DIGITAL CHARACTERISTICS: 25°C,
Output loaded with Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout -600µA) Low-Level Output Voltage (Iout 800µA) Input Leakage Current Output Leakage Current Digital Input Capacitance Digital Output Capacitance Symbol Iout Cout
±5%; GND1 GND2 GND3 Units
VD+-1.0 VD+-0.4
CS5543 RECOMMENDED OPERATING CONDITIONS: (GND1 GND2 GND3
voltages with respect 0V.) Parameter Digital Supply Supply Voltage Required Maintain Calibration Information Symbol 4.75 5.25 Units
CS5543 ABSOLUTE MAXIMUM RATINGS*: (GND voltages with respect 0V.)
Parameter Power Supplies: Symbol VD1+ VD2+ VD3+ Vinp Tstg -0.3 -0.3 Units
Input Current (Except Supply Pins) Digital Input Voltage Storage Temperature
±10.0 (VD+)+0.3
*Warning: Operation beyond these limits result permanent damage device Normal operations guaranteed these extremes
DS109PP2
CS5542 CS5543
GENERAL DESCRIPTION
CS5542 monolithic CMOS dual delta-sigma modulator. Each modulator CS5542 accepts level current input, usually supplied photodiode (see Figure This current digitized CS5542 modulator filtered CS5543 digital decimation filter. Four CS5542 modulator chips combined with CS5543 filter chip provide eight channels data conversion shown Figure 8-channel blocks CS5542/CS5543 chip sets connected build 1024 channel system shown Figure CS5542/CS5543 combination supports several calibration modes data acquisition system.
Differential Voltage Reference
THEORY OPERATION CS5542/CS5543 chip designed construct multi-channel current input digitizer systems. conversion clock input (CLKIN) into CS5543 provides master clock digital filter. This clock fast 2.048 MHz. CLKIN buffered inside CS5543 passed each CS5542 modulator chips MCLK (modulator clock) signal. CS5542/ CS5543 combination provides output conversion data word rate equal CLKIN/2048.
+4.0
-4.0
.1µF
.1µF SEL0 SEL1
Note
Photodiode
VREF+ VREF-
CAPSIZE
REFGNDL
GNDL
MCLK
CS5543 Decimator
Reference -4.0 Note
Note
ICAL
CS5542
FSYNC [1:0]
28,27,26
Photodiode
[2:0]
REFGNDR GNDR
MDATA [3:0] VAVA+ DGND .1µF
25,24,21,20
AGND
DGND
.1µF
.1µF
Note Diodes connected with either polarity. shown CS5542/43 will generate more negative code photodiode outputs more current. ICAL current either polarity. magnitude will determine full scale measurement range.
Figure CS5542 Typical Connection Diagram
DS109PP2
CS5542 CS5543
INL0 INR0
ICAL
ICAL
MDATA[3:0] C[2:0] CAL[1:0] FSYNC CS5542 MCLK CAPSIZE SEL1 DGND SEL0 DGND
INL1 INR1
MDATA[3:0] C[2:0] CAL[1:0] FSYNC CS5542 MCLK CAPSIZE SEL1 DGND SEL0
CS5543
ICAL
INL2 INR2
ICAL
MDATA[3:0] C[2:0] CAL[1:0] FSYNC CS5542 MCLK CAPSIZE SEL1 SEL0 DGND
MDATA[3:0] C[2:0] CAL[1:0] FSYNC CS5542 MCLK CAPSIZE SEL1 SEL0
CAPS MCLK FSYNC CAL[1:0] C[2:0] MDATA[3:0]
FEGAIN FRAME DATCLK CLKIN DATAOUT[3:0] DATAIN[3:0] DATSEL[3:0] DMODE[2:0]
FEGAIN FRAME DATCLK CLKIN DATAOUT[3:0] DATAIN[3:0] DATSEL[3:0] DMODE[2:0]
INL3 INR3
ICAL
Supplies omitted clarity
Figure Typical 8-channel Connection Diagram
DS109PP2
CS5542 CS5543
Current Inputs DATAIN[3:0] FEGAIN FRAME DATACLK CLKIN DATSEL[3:0] DMODE[2:0] DATAOUT[3:0]
DATAIN[3:0] FEGAIN FRAME DATACLK CLKIN DATSEL[3:0] DMODE[2:0] DATAOUT[3:0]
From previous IEEE 1149.1 compliant device system
ICAL0
INL0 INR0 INL1 INR1 INL2 INR2 INL3 INR3 ICAL
DATAIN[3:0] FEGAIN RST* FRAME DATACLK CLKIN DATSEL[3:0] DMODE[2:0]
8-channel Block
IN10 IN11 IN12 IN13 IN14 IN15 ICAL1 INL0 INR0 INL1 INR1 INL2 INR2 INL3 INR3 ICAL
Host System Interface
8-channel Block
IN1016 IN1017 IN1018 IN1019 IN1020 IN1021 IN1022 IN1023 ICAL127
INL0 INR0 INL1 INR1 INL2 INR2 INL3 INR3 ICAL
8-channel Block
DATAIN[3:0] FEGAIN FRAME DATACLK CLKIN DATSEL[3:0] DMODE[2:0] DATAOUT[3:0]
DATAOUT[3:0]
next IEEE 1149.1 compliant device system
Figure Typical 1024 Connection Diagram
DS109PP2
CS5542 CS5543
CS5542 includes modulators. input current into each modulators following factors: MCLK (modulator clock) frequency, value VREF voltage modulator chip, logic value CAPSIZE input CS5542 modulator (this selects either transimpedance feedback capacitor). MCLK typically some frequency between 1.024 2.048 MHz. VREF voltage optimally Volts. voltage reference modulator actually input into both VREF+ VREF- pins +4.0 -4.0 volts. full scale input current defined following equation: (VREF) (CDAC) (MCLK/16) With VREF 4.0, MCLK 2.048 MHz, CDAC select nominal full scale current will value offset gain register contents will affect actual conversion words which output from converter with specific input current. Several calibration steps discussed later) necessary ensure that chip converts accurately. CS5542 dual modulator CS5543 multichannel filter designed interface together. CS5542 modulator uses tri-level modulator. modulator thresholds must calibrated before accurate measurements accomplished. threshold values measured digitally corrected inside CS5543 digital filter. CS5543 digital filter functions digital calibration engine communications interface addition being filter. CS5543 digital filter collects multi-bit quantized data from four dual modulator CS5542s computes offset gain corrections data, yielding 24-bit output word. 24-bit output data word includes overflow bit, parity bit,
DS109PP2
data bits bits plus sign). There several clocks which control timing multi-channel system. CLKIN (Master Clock) primary clock system. CLKIN (typically 2.048 MHz) input CS5543 filter. Inside filter CLKIN buffered passed CS5542s MCLK. each clock cycles MCLK modulator, four modulator sample passed CS5543 digital filter. digital filter computes output conversion word each 1024 modulator samples. output word rate filter therefore related CLKIN MCLK frequency ratio CLKIN/2048 (output word rate). conversion data eight CS5542 modulator channels output from four CS5543 DATAOUT pins serial-formatted, time-multiplexed fashion. DATACLK controls rate which data output from DATAOUT pins. DATACLK three times frequency CLKIN. CS5542/CS5543 chip designed support constructing serially-connected current digitization system with 1024 channels. System Initialization Calibration After power applied CS5542/CS5543 system, reset must issued CS5543 device taking low. This resets gain register (199998(H)) other registers 0.0. After returned high, release state recognized until next rising edge FRAME signal. After reset recognized, CS5542/CS5543 system must complete full calibration steps before being used measurement. Calibrations performed controlling states DTEST (Digital Test Mode Select) pins with DATSEL (Data Select Mode) pins held logic Tables illustrate commands available DTEST DATSEL
CS5542 CS5543
DATSEL[3:0]
DTEST[2:0]
FUNCTION Normal Operation Input Offset Voltage Noise System Offset Full-Scale Gain (Uses ICAL input) Full-Scale Gain (Uses INL(INR) input) Decimator Modulator Power-Down Modular Power Down
Table Operation Modes
DTEST[2:0]
DATSEL[3:0]
FUNCTION Normal Operation Tri-State Dataout [3:0] Pins Test Pattern Test Pattern Offset Register Load Offset Register Load Gain Register Load Noise Register Load Offset Register Read Offset Register Read Gain Register Read Noise Register Read Reserved
DATA TYPE (SIGN, first)
(MSW) (Note (LSW) (Note
(MSW) (LSW)
Notes: Most Significant Word Least Significant Word
Table Control Modes
pins. When entering calibration commands DTEST lines, calibration steps must follow specific sequence CS5542/CS5543 pair properly calibrated. Figure illustrates calibration sequence CS5542/CS5543 chip set. After issued, chip will normal mode. first calibration step Input
Offset Voltage mode. CS5542 designed digitize input current. This current normally sourced from photodiode input chip. Input Offset Voltage step intended remove offset front modulator. This should calibrated with photodiode current present. phototdiode replaced with resistor, voltage
System Reset
Normal
Input Offset Voltage
Noise
System Offset
INR(INL) ICAL Gain
Normal
Note: Main Current Input must idle calibration modes except Gain using INL(INR).
Figure Calibration Sequence CS5542/CS5543
DS109PP2
CS5542 CS5543
Noise Calibration Register
Parity (Note
Parity (Note
System Offset Registers
Sign Sign Sign
Upper Bits
Lower Bits
Parity (Note
Gain Registers
Integer
Decimal
Parity (Note
Reset Binary 000.11001100110011001000 199998(H) Note Parity bits odd.
Table Calibration Registers
should zeroed before calibrating Input Offset Voltage step. Input Offset Voltage mode will require filter cycles filter cycle output conversion word) complete. CS5543 will accept mode commands until filter cycles have been completed, even DTEST pins changed. After filter cycles, calibration step complete. Note that when Input Offset Voltage command initiated inside CS5543 decimator, modulators CS5542 chips connected CS5543 will execute calibration step same time. There calibration word register inside CS5543 which contains calibration data this calibration step. next calibration performed Noise Cal. This calibration step necessary calibrate quantizer threshold modulators. This ensures linearity multi-bit quantizer. Noise lasts filter cycles. Upon entering Noise mode, system offset registers
DS109PP2
gain registers unaffected. Noise step performed time performed independent other calibration steps. When this step executed, eight modulators associated with CS5543 calibrate same time. Noise step, 24-bit calibration word placed into Noise register inside CS5543. After modulators have been calibrated Noise step, System Offset step performed. current present (INR) input time System Offset performed will treated zero point converter transfer function. System Offset step lasts 1028 filter cycles. System Offset Cal, signed 43-bit result placed into System Offset registers (MSW LSW; Most Significant Word Least Significant Word) inside CS5543. After System Offset complete, next calibration step gain calibration. perform gain calibration, input signal must
CS5542 CS5543
provided into CS5542. CS5542 dual modulator designed allow possible means inputting signal necessary perform this calibration step. input method chosen will dictate whether ICAL Full-Scale Gain System Full-Scale Gain performed. input CS5542 ICAL pin. current sourced into this provide calibration current full scale point (actually full scale value will discussed later) system. current into ICAL will used calibrate gain Full-Scale Gain mode (using ICAL input) selected. Note that ICAL CS5542 shared between modulators. Each modulator will calibrated sequentially (only eight channels will active time during calibration ICAL Full-Scale Gain mode executed. CS5543 will sequentially calibrate each eight modulators associated with Each Gain requires filter cycles; therefore filter cycles will elapse ICAL Full-Scale Gain Cal. Gain Cal, 24-bit calibration word placed into Gain Register CS5543. Selection ICAL Full-Scale Gain mode enables ICAL input switch (note that normal current input remains active current will summed with ICAL current when using this mode). During ICAL Full-Scale Gain cycle, only ICAL input active time, therefore single external resistor voltage source supply current which used calibrate eight channels associated with single CS5543. Alternatively, four individual resistors supplied, each CS5542 dual channel ICAL input. magnitude calibration current should less than desired full scale current. Recall that nominal full scale input current magnitude size internal transimpedance capacitor, clock rate, VREF voltage. output code produced this current will approximately full scale. gain point calibrated with currents below nominal full scale value clock rate, size, VREF voltage. preferable keep input current calibration within nominal full scale value lower levels input calibration magnitude will exhibit slight reduction dynamic range. Full-Scale Gain mode using (INR) selected, ICAL input front each CS5542 used. Instead, gain calibrated using current input into pins. Again, current supplied should less than desired full scale value. output code this current will approximately full scale. either gain calibration mode (ICAL (INR)) magnitude input current should nominal full scale, polarity important. current sinked sourced. either case CS5543 will calibrate positive full scale point. Once calibrated, currents into pins will result positive output code, while currents pins will yield negative output code. Calibration Register Readability CS5543 registers which hold digital calibration words each eight channels. each channels, there four 24-bit registers. Noise Gain functions each result 24-bit digital calibration word, whereas System Offset function produces 48-bit calibration word which split into 24-bit registers. These registers read their contents stored into some nonvolatile storage from which they recalled reloaded desired. 48-bit Offset register contents must read
DS109PP2
CS5542 CS5543
channel DATAOUT
SIGN
channel
Parity SIGN
channel
Parity
channel DATAOUT SIGN channel DATAOUT
SIGN
Parity
SIGN
channel
Parity
channel
Parity
SIGN
channel
Parity
DATAOUT
SIGN
Parity
SIGN
Parity
Figure Data Transfer Timing
written with read cycles using different commands read either (Most Significant Word) (Least Significant Word). When reading writing calibration registers, register contents time-division multiplexed into CS5543 same manner conversion data shown Figure addition writing reading calibration registers, CS5543 provides several test modes. Some these test modes follows: DATAOUT [3:0] pins high impedance output state; either different test patterns requested output DATAOUT [3:0] pins CS5543. Table test pattern information. Commands change calibration modes control modes should issued system while calibration progress. data calibration control modes latched every falling edge CLKIN takes effect following rising edge FRAME.
Test Pattern
(all channels)
BINARY Test Pattern (All channels) A00001 0001 0000 0000 0000 0000 0001 Sign, LSB, parity
Test Pattern
(Unique each channel)
Channel
1000A0 000A01 20A000 0A0001 450000 005001 800500 000051
BINARY
0001 0000 0000 0000 0000 0001 0000 0000 0000 1010 0000 0001 0010 0000 1010 0000 0000 0000 0000 1010 0000 0000 0000 0001 0100 0101 0000 0000 0000 0000 0000 0000 0101 0000 0000 0001 1000 0000 0000 0101 0000 0000 0000 0000 0000 0000 0101 0001 Sign, LSB, parity
Table Test Patterns
DS109PP2
CS5542 CS5543
Sign
Parity
Figure Data Conversion Word Format
Bipolar Input Current Positive Full Scale1 Zero Input Negative Full Scale
Output Code (Sign Data Bits) 0000 0000 1111 0000 0000 1111 0000 0000 1111 0000 0000 1111 0000 0000 1111
Note Positive Full Scale current going into modulator. DOUT 2,097,151 [(IIN IOF)/(IFS IOF)] where DOUT digital output code from CS5543; current going into modulator during System Offset Voltage Calibration; full scale input current which always positive magnitude will absolute value current going into either INL/INR ICAL pin, divided 0.97; current going into modulator during conversion. 2,097,151
Table Output Coding CS5542/CS5543.
Conversion Coding Each channels CS5543 outputs 24bit conversion data word. word includes sign along with additional data bits, Oscillation Detect flag (OD), parity bit. format data conversion word shown Figure whenever modulator CS5542 overranged point making lose stability. Under this condition output data erroneous. whenever input magnitude exceeds full scale point greater than will cleared whenever modulator input comes back into proper range. Table illustrates output coding CS5542/CS5543 chip set. Positive current means that current flowing into (INR) produces positive output code. CS5543 Serial Data Interface serial data interface CS5543 four input signals four output signals. Data read from CS5543 output from DATAOUT[3:0]
pins. DATAOUT[0] outputs data from channels DATAOUT[1] outputs data from channels DATAOUT[2] outputs data from channels DATAOUT[3] outputs data from channels Information from DATAOUT[0] output beginning with sign channel ends with parity (odd) channel Data other DATAOUT pins follows same convention. system, multiple CS5543s connected with DATAOUT pins CS5543 connected DATAIN pins next CS5543. DATAOUT[3:0] lines will change immediately after rising edge DATACLK, latched into DATAIN[3:0] pins next rising edge DATACLK. timing diagram which shows eight channels data transfer from CS5543 another shown Figure data which transmitted either from series-connected CS5543s synchronized FRAME signal. FRAME should pulse, CLKIN cycle wide, generated falling edges
DS109PP2
CS5542 CS5543
10µF LT10195 4.02K 100µF OP27 +4.0 15µF 0.1µF 0.01µF
100µF
Figure Noise-Filtered Bandgap Reference
CLKIN. FRAME will latched into CS5543 rising edge CLKIN. This will subsequently generate FSYNC signal synchronize CS5542 modulators. System Connections eight channel digitizer system constructed using four CS5542 dual modulators with CS5543 eight-channel decimator. Figure illustrates hardware signal connections eight channel system. Digitizer blocks eight channels each cascaded connect blocks together total 1024 digitizer channels. clocks system related CLKIN master clock. Assuming that CLKIN= 2.048 MHz, converter output word rate will CLKIN/2048. data framing signal, FRAME, synchronizes digital output data modulator data. FRAME signal must occur output word rate. DATACLK must three times faster than CLKIN rate, 6.144 this example. CS5543 four DATAOUT lines. Each lines provides output data from eight channels associated with single CS5543. Data from DATAOUT line serially transferred DATAOUT 48bit blocks, consisting 24-bit words. With CS5543 linked together, each four serial lines linking DATAOUT pins DATAIN pins effect serial shift register 6144
DS109PP2
128) bits long. DATACLK used shift data each CS5543 blocks. 1024 channel system with CLKIN rate 2.048 MHz, 6.144 DATACLK will shift data 1024 channels millisecond. Analog Input CS5542 modulator optimized driven photodiode current source. Photodiodes have large output impedances. photodiode also capacitance which function size. CS5542 relies this capacitance ensure stability input stage. capacitance also affects bandwidth input circuit. cases modulator assumes that external shunt capacitance photodiode least 220pF. input source actually voltage source resistor used generate input current, capacitor should connected between input ground. resistor will additional current noise into circuit will degrade dynamic range somewhat. Voltage Reference voltages supplied VREF+ VREFpins range from ±2.0 volts ±4.1 volts with volts being preferred. VREF+ VREFvoltages should balanced have noise. Figure illustrates bandgap voltage reference well filtered provide noise source +4.0 volts.
CS5542 CS5543
Each VREF+ VREF- input CS5542 require microamp reference current. number channels which supplied from voltage reference buffer will depend upon buffer's output impedance distance between CS5542 reference circuitry. well-designed voltage reference should able supply channels CS5542s) system. Board Layout circuit board containing CS5542 modulator should have ground plane split through middle modulator with pins through over quiet analog ground plane. addition, guarding techniques should used around level inputs INL, INR, ICAL. Care must also exercised ensure that circuit card manufactured with good quality ensure leakage. After assembly, card should cleaned ensure free from surface contaminants. Clock Source CLKIN must have jitter; less than psec RMS. Note that drift CLKIN over time temperature will show gain error CS5542/CS5543 measurement system; therefore stable clock source highly desirable. Power Supply Power supply noise ripple must very within passband CS5543 digital filter. This noise ripple pass through (Electrostatic Discharge) protection diodes (INR) into transimpedance stage CS5542 modulator. With capacitance this diode about transimpedance resistor first stage about 2-10 megohm, coupling supply ripple going occur. this reason, noise ripple power supplies should enough that noise coupled into transimpedance stage should remain below noise floor converter across bandwidth
digital filter. achieve this, related noise ripple should remain below microvolts peak-to-peak. Digital Filter digital filter linear phase filter. filter group delay three conversion words equivalent noise bandwidth 0.536 output word frequency. Plots filter shown data sheet tables. Coefficients tabulated Appendix this data sheet. Joint Test Action Group (JTAG) Boundary-Scan Interface CS5543 designed large multi-channel systems. this reason chip designed support IEEE Standard Access Port BoundaryScan Architecture defined IEEE Std. 1149.11990, P1149.1. This standard defines circuitry which built into integrated circuit assist test, maintenance, support system printed circuit board level. CS5543 includes circuitry which supports this standard. highly recommended that this type test capability desired your system, that acquire copy IEEE standard which thoroughly discusses IEEE Standard Access Port Boundary-Scan Architecture will only discussed briefly here. CS5543 includes (Test Access Port) made following connections: (Test Clock), (Test Mode Select input), (Test Data Input), (Test Data Output). addition TAP, test logic includes controller, instruction register, test registers. controller synchronous finite state machine which controls sequence operations necessary implement boundaryscan architecture. Figure illustrates controller state diagram. instruction register allows instruction shifted into design.
DS109PP2
CS5542 CS5543
Test-Logic-Reset Select-DR-Scan Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR Select-IR-Scan
Run-Test/Idle
Figure Controller State Diagram
instruction register used select test performed select test data register accessed. 3-bit instructions available instruction register illustrated Table 3-bit instruction shifted first.
CODE INSTRUCTION EXTEST SAMPLE/PRELOAD IDCODE OPERATING MODE REGISTER reserved reserved reserved BYPASS
Table Boundary Scan Instructions
board interconnects. ordering same top-view packaged pinout, clockwise beginning with MDATA[3], ending with RST. TAP, power pins included part boundary-scan register. bits long. Inputs BSR, bypassing actual pin. outputs 3-state (logic high, high impedance) outputs. Their states during test controlled PRELOAD instruction. boundaryscan register, each input device represented position boundary scan register, whereas each outputs, having possibility three states, require bits each boundary-scan register. Device Identification Register designed identify manufacturer, part number, version number CS5543. format illustrated Table Data from shifted first. Note that when CS5543 reset, Instruction Register select IDCODE.
Several test registers design including Boundary-Scan Register (BSR), Device Identification Register (DIR), Operating Mode Register (OMR), Bypass Register (BR). Boundary-Scan Register allows testing
DS109PP2
CS5542 CS5543
Operating Mode Register (OMR) allows access device operating modes DATASEL DMODE pins shown figure Bypass Register allows minimum length path between pins device. This register selected whenever device does need tested during board-level test operation.
DATSEL DMODE
Operation EXTEST Before execution instruction EXTEST, SAMPLE/PRELOAD instruction must used load testing data output pins through TDI. Each output requires bits. first shifted controls output enable function. logic entered, output enabled; logic entered, output disabled. second shifted after first test data. Therefore, cycles required load testing data into boundary-scan register each output pin.
Figure Operating Mode Register
Device Identification Register
V3-V0 P15-P0 M10-M0 NAME Version Bits Part Number Bits Manufacture Number Bits Logic VALUE 0000 0101010101000011 00001100100
FUNCTION Version Number Device Part Number Device Manufacture Number Always Logic
Table Device Identification Register
DS109PP2
CS5542 CS5543
CS5542 DESCRIPTIONS
CAPSIZE VREFVREF+ GNDL REFGNDL REFGNDR GNDR
ICAL
MDATA3
MDATA2
CS5542
DGND MDATA1 MDATA0 CAL1 CAL0 MCLK FSYNC SEL1
VIEW
VASEL0
Power Supplies
GNDL Ground Left, Left modulator analog ground integrators through REFGNDL Reference Ground Left, Analog ground left modulator integrator summing node. GNDR Ground Right, Right modulator analog ground integrators through REFGNDR Reference Ground Right, Analog ground right modulator integrator summing node. Positive Analog Supply, Positive analog supply voltage. Nominally volts. Negative Analog Supply, Negative analog supply voltage. Nominally volts. Digital Supply, Digital supply voltage. Nominally volts.
DS109PP2
CS5542 CS5543
CS5542 DESCRIPTIONS
DGND Digital Ground, Digital ground.
Digital Input PinsMCLK Modulator Clock Input, modulator clock input provides necessary clock operation modulator. MCLK operates times modulator sample rate. MCLK 2048 times output word rate. FSYNC Frame Sync, transition from high level this input supplied CS5543, will reset internal master timing CS5542 synchronize data with each output word. CAL[1:0] Calibration Control, Pins mode operation CS5542 selected through calibration control pins CS5543 summarized table below.
CAL1
CAL0
Mode Selected Normal Operation, Noise CAL, Offset Input offset voltage calibrate Unused code Full Scale gain calibrate
Normal Calibration Sequence Input Offset Noise CAL(Dark) Offset CAL(Dark) Gain Normal Operation
SEL[1:0] Time Slot Selections, Pins 15,14 binary code applied SEL0 SEL1 will determine time slot pair associated with CS5542. Each four CS5542's connected single CS5543 must have unique code assigned combination SEL0 SEL1. CAPSIZE Full Scale Input Range Select, When CAPSIZE CDAC when CAPSIZE CDAC
DS109PP2
CS5542 CS5543
CS5542 DESCRIPTIONS
Power Down, When asserted CS5542 will enter power-down state. C[2:0] ICAL Input Select, Pins array CS5542's (eight channels), C2-C0 will select which channel receive d.c. current applied ICAL pins.
Digital Outputs PinsMDATA[3:0] Modulator Data Outputs, Pins tri-level modulator data output MDATA3 MDATA0 decimation CS5543.
Modulator Output Coding Table Overload MDATA3 MDATA2 zero MDATA_1 MDATA0 Value Meaning Normal operation Normal operation Normal operation Modulator Overload Modulator Overload Modulator Overload
shown table above, constant number zeros ones exist output states. This provides data-independent noise invariant coding maximize isolation between channels.
Analog Input Pins VREF-,VREF+ Differential Voltage Reference Inputs, Pins differential voltage reference these pins operates voltage reference CS5542. Nominally, -4.0 respectively. ICAL Full-Scale Current Calibration Input, ICAL needs supplied full-scale gain calibration. INL, Input Left Input Right, Pins left right modulator current input pins.
DS109PP2
CS5542 CS5543
CS5543 DESCRIPTIONS
DATAIN[0] DATAIN[1] DATAIN[2] DATAIN[3] CAL[0]
DATAOUT[0] DATAOUT[1] DATAOUT[2] DATAOUT[3] GND3 VD3+
DATACLK FRAME CLKIN DATSEL[0] DATSEL[1] DATSEL[2] DATSEL[3] DTEST[0] DTEST[1] DTEST[2] FEGAIN VD2+ GND2
CAL[1] FSYNC MCLK GND1 VD1+ CAPS MDATA[0] MDATA[1] MDATA[2] MDATA[3]
CS5543
VIEW
Power Supply
VD1+, VD2+, VD3+ Digital Power Supplies, Pins Digital supply voltages. Nominally Volts. GND1, GND2, GND3 Digital Ground, Pins Digital grounds.
DSM-DSD Interface Pins
C[2:0] ICAL Channel Select (Outputs), Pins array CS5542's (eight channels), C2-C0 will select which channel receive d.c. current applied ICAL pins during full-scale gain calibration.
DS109PP2
CS5542 CS5543
CS5543 DESCRIPTIONS
CAL[1:0] Calibration Control (Outputs), Pins mode operation CS5542 selected through calibration Control pins. table pin-out section CS5542 data sheet details. FSYNC Frame Sync (Output), transition from high level CS5542's input will reset internal master timing CS5542 synchronize data with each output word from CS5543. MCLK Modulator Clock (Output), modulator clock output provides necessary clock operation modulator. CAPSIZE Full Scale Input Range Select (Output), Controls CAPSIZE input CS5542. This determines size sampling capacitor used CS5542. Power Down (Output), When asserted CS5542 will enter power-down state. MDATA[3:0] Modulator Data Inputs (Inputs), Pins tri-level modulator data input CS5543 MDATA3 MDATA0 decimation. table pin-out section CS5542 data sheet details.
Test Access Port Pins
-Test Mode Select (Input), Controls state-to-state operation controller. Test Data Input (Input) Serially inputs data Test Access Port. Test Data Output (Output), Serially outputs data from Test Access Port. Test Clock (Input), clock Test Access Port, shorted MCLK
Control Pins
Output Enable (Input), Enables disables (tri-states) output pins CS5543. FEGAIN Front-End Gain Select (Input), Selects Front-End Capacitor Gain Ratio. full calibration necessary following change this input.
DS109PP2
CS5542 CS5543
CS5543 DESCRIPTIONS
DMODE[2:0] Digital Mode Select (Inputs), Pins Selects operation mode CS5543. DATSEL[3:0] Data Selection Mode (Inputs), Pins Selects Data placed DATAOUT[3:0] pins. Chip Reset (Input), Resets internal logic registers.
DSD-System Interface Pins
DATACLK Serial Data Clock (Input), Clock signal generated system controller which governs serial output data timing from CS5543. CLKIN Master System Clock (Input), CMOS compatible clock input this governs non-serial data timing. FRAME Framing Signal (Input), Synchronizes DATACLK MCLK each frame output data from CS5543. DATAOUT[3:0] Serial Output Data (Outputs), Pins 41-44. CS5543 serial output data. DATAIN[3:0] Serial Data Inputs (Inputs), Pins 1-4. CS5543 serial input data from serial output adjacent CS5543 multi-decimator system.
DS109PP2
CS5542 CS5543
Filter Coefficients
h(0)=h(383)= h(1)=h(382)= h(2)=h(381)= h(3)=h(380)= h(4)=h(379)= h(5)=h(378)= h(6)=h(377)= h(7)=h(376)= h(8)=h(375)= h(9)=h(374)= h(10)=h(373)= -107 h(11)=h(372)= -133 h(12)=h(371)= -163 h(13)=h(370)= -199 h(14)=h(369)= -240 h(15)=h(368)= -287 h(16)=h(367)= -342 h(17)=h(366)= -404 h(18)=h(365)= -475 h(19)=h(364)= -556 h(20)=h(363)= -647 h(21)=h(362)= -750 h(22)=h(361)= -865 h(23)=h(360)= -995 h(32)=h(351)= -2988 h(33)=h(350)= -3327 h(34)=h(349)= -3695 h(35)=h(348)= -4094 h(36)=h(347)= -4524 h(37)=h(346)= -4988 h(38)=h(345)= -5487 h(39)=h(344)= -6021 h(40)=h(343)= -6594 h(41)=h(342)= -7205 h(42)=h(341)= -7856 h(43)=h(340)= -8549 h(44)=h(339)= -9283 h(45)=h(338)= -10060 h(46)=h(337)= -10881 h(47)=h(336)= -11745 h(48)=h(335)= -12654 h(49)=h(334)= -13608 h(50)=h(333)= -14605 h(51)=h(332)= -15646 h(52)=h(331)= -16730 h(53)=h(330)= -17856 h(54)=h(329)= -19023 h(55)=h(328)= -20228 h(64)=h(319)= -32337 h(65)=h(318)= -33741 h(66)=h(317)= -35134 h(67)=h(316)= -36508 h(68)=h(315)= -37856 h(69)=h(314)= -39167 h(70)=h(313)= -40431 h(71)=h(312)= -41638 h(72)=h(311)= -42777 h(73)=h(310)= -43834 h(74)=h(309)= -44798 h(75)=h(308)= -45655 h(76)=h(307)= -46389 h(77)=h(306)= -46987 h(78)=h(305)= -47431 h(79)=h(304)= -47706 h(80)=h(303)= -47793 h(81)=h(302)= -47674 h(82)=h(301)= -47330 h(83)=h(300)= -46742 h(84)=h(299)= -45888 h(85)=h(298)= -44749 h(86)=h(297)= -43301 h(87)=h(296)= -41523 h(88)=h(295)= -39391 h(89)=h(294)= -36881 h(90)=h(293)= -33970 h(91)=h(292)= -30633 h(92)=h(291)= -26845 h(93)=h(290)= -22580 h(94)=h(289)= -17812 h(95)=h(288)= -12515 h(96)=h(287)= -6663 h(97)=h(286)= -229 h(98)=h(285)= 6812 h(99)=h(284)= 14489 h(100)=h(283)= 22828 h(101)=h(282)= 31855 h(102)=h(281)= 41596 h(103)=h(280)= 52077 h(104)=h(279)= 63323 h(105)=h(278)= 75361 h(106)=h(277)= 88214 h(107)=h(276)= 101906 h(108)=h(275)= 116461 h(109)=h(274)= 131900 h(110)=h(273)= 148246 h(111)=h(272)= 165518 h(112)=h(271)= 183736 h(113)=h(270)= 202918 h(114)=h(269)= 223081 h(115)=h(268)= 244240 h(116)=h(267)= 266410 h(117)=h(266)= 289602 h(118)=h(265)= 313827 h(119)=h(264)= 339094 h(120)=h(263)= 365410 h(121)=h(262)= 392781 h(122)=h(261)= 421209 h(123)=h(260)= 450696 h(124)=h(259)= 481241 h(125)=h(258)= 512840 h(126)=h(257)= 545489 h(127)=h(256)= 579178 h(128)=h(255)= 613898 h(129)=h(254)= 649637 h(130)=h(253)= 686379 h(131)=h(252)= 724107 h(132)=h(251)= 762800 h(133)=h(250)= 802436 h(134)=h(249)= 842990 h(135)=h(248)= 884434 h(136)=h(247)= 926737 h(137)=h(246)= 969867 h(138)=h(245)= 1013788 h(139)=h(244)= 1058463 h(140)=h(243)= 1103850 h(141)=h(242)= 1149907 h(142)=h(241)= 1196589 h(143)=h(240)= 1243847 h(144)=h(239)= 1291632 h(145)=h(238)= 1339892 h(146)=h(237)= 1388572 h(147)=h(236)= 1437615 h(148)=h(235)= 1486965 h(149)=h(234)= 1536559 h(150)=h(233)= 1586337 h(151)=h(232)= 1636234 h(152)=h(231)= 1686186 h(153)=h(230)= 1736126 h(154)=h(229)= 1785986 h(155)=h(228)= 1835697 h(156)=h(227)= 1885189 h(157)=h(226)= 1934391 h(158)=h(225)= 1983233 h(159)=h(224)= 2031641 h(160)=h(223)= 2079544 h(161)=h(222)= 2126869 h(162)=h(221)= 2173544 h(163)=h(220)= 2219496 h(164)=h(219)= 2264653 h(165)=h(218)= 2308943 h(166)=h(217)= 2352295 h(167)=h(216)= 2394640 h(168)=h(215)= 2435908 h(169)=h(214)= 2476030 h(170)=h(213)= 2514942 h(171)=h(212)= 2552576 h(172)=h(211)= 2588870 h(173)=h(210)= 2623763 h(174)=h(209)= 2657194 h(175)=h(208)= 2689106 h(176)=h(207)= 2719443 h(177)=h(206)= 2748154 h(178)=h(205)= 2775188 h(179)=h(204)= 2800497 h(180)=h(203)= 2824037 h(181)=h(202)= 2845767 h(182)=h(201)= 2865647 h(183)=h(200)= 2883642 h(184)=h(199)= 2899720 h(185)=h(198)= 2913852 h(186)=h(197)= 2926013 h(187)=h(196)= 2936181 h(188)=h(195)= 2944337 h(189)=h(194)= 2950467 h(190)=h(193)= 2954560 h(191)=h(192)= 2956609
h(24)=h(359)= -1139 h(56)=h(327)= -21471 h(25)=h(358)= -1299 h(57)=h(326)= -22747 h(26)=h(357)= -1477 h(58)=h(325)= -24055 h(27)=h(356)= -1674 h(59)=h(324)= -25391 h(28)=h(355)= -1891 h(60)=h(323)= -26751 h(29)=h(354)= -2129 h(61)=h(322)= -28131 h(30)=h(353)= -2391 h(62)=h(321)= -29526 h(31)=h(352)= -2676 h(63)=h(320)= -30930
DS109PP2
28-pin PLCC
MILLIMETERS INCHES
4.20
4.45
4.57 0.165 0.175 0.180
2.29 0.33
2.79 0.41
3.04 0.090 0.110 0.120 0.53 0.013 0.016 0.021
12.32 12.45 12.57 0.485 0.490 0.495
D1/E1 11.43 11.51 11.58 0.450 0.453 0.456 D2/E2 9.91 10.41 10.92 0.390 0.410 0.430
1.19 1.27 1.35 0.047 0.050 0.053
D2/E2

22-Bit, Multi-Channel Chip Delta-Sigma Architecture: Order Modula

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