64/100-Pin General Purpose 32-Bit Flash Microcontrollers 2008 Mic
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PIC32MX3XX/4XX Family Data Sheet
64/100-Pin General Purpose 32-Bit Flash Microcontrollers
2008 Microchip Technology Inc.
DS61143E
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Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2008, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS61143E-page
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
High-Performance MIPS-Based 32-bit Flash Microcontroller
64/100-Pin General Purpose
High-Performance 32-bit RISC CPU:
MIPS32® M4K32-bit Core with 5-Stage Pipeline Maximum Frequency 1.56 DMIPS/MHz (Dhrystone 2.1) Performance Wait State Flash Access Single-Cycle Multiply High-Performance Divide Unit MIPS16eMode Smaller Code Size User Kernel Modes Enable Robust Embedded System Sets Core Register Files (32-bit) Reduce Interrupt Latency Prefetch Cache Module Speed Execution from Flash Separate PLLs Clocks I2CModules UART Modules with: RS-232, RS-485 support IrDA® with On-Chip Hardware Encoder Decoder Parallel Master Slave Port (PMP/PSP) with 8-bit 16-bit Data Address Lines Hardware Real-Time Clock/Calendar (RTCC) Five 16-bit Timers/Counters (two 16-bit pairs combine create 32-bit timers) Five Capture Inputs Five Compare/PWM Outputs Five External Interrupt Pins High-Speed Pins Capable Toggling High-Current Sink/Source mA/18 Pins Configurable Open-Drain Output Digital Pins
Microcontroller Features:
Operating Voltage Range 2.3V 3.6V 512K Flash Memory (plus additional 12KB Boot Flash) SRAM Memory Pin-Compatible with Most PIC24/dsPIC® Devices Multiple Power Management Modes Multiple Interrupt Vectors with Individually Programmable Priority Fail-Safe Clock Monitor Mode Configurable Watchdog Timer with On-Chip Low-Power Oscillator Reliable Operation
Debug Features:
Programming Debugging Interfaces: 2-Wire Interface with Unintrusive Access Real-time Data Exchange with Application 4-wire MIPS Standard Enhanced JTAG interface Unintrusive Hardware-Based Instruction Trace IEEE 1149.2 Compatible (JTAG) Boundary Scan
Peripheral Features:
Atomic SET, CLEAR INVERT Operation Select Peripheral Registers 4-Channel Hardware Controller with Automatic Data Size Detection Compliant Full Speed Device On-The-Go (OTG) Controller Dedicated Channel Crystal Oscillator Internal Oscillators
Analog Features:
16-Channel 10-bit Analog-to-Digital Converter: ksps Conversion Rate Conversion Available During Sleep, Idle Analog Comparators 5.5V Tolerant Input Pins (digital pins only)
2008 Microchip Technology Inc.
DS61143E-page
PIC32MX3XX/4XX
FIGURE PIC32MX PACKAGE OUTLINE DRAWING
TQFP 64-Pin TQFP 100-Pin
TABLE
PIC32MX GENERAL PURPOSE FEATURES
General Purpose Programmable Channels Comparators PMP/PSP PMP/PSP
Device
Pins
Program/ Data Memory (KB)
Timers/ Capture/ Compare
EUART/ SPI/ I2C
VREG
Trace
10-bit (ch)
PIC32MX320F032H PIC32MX320F064H PIC32MX320F128H PIC32MX340F128H PIC32MX340F256H PIC32MX340F512H PIC32MX320F128L PIC32MX340F128L PIC32MX360F256L PIC32MX360F512L
32/8 64/16 128/16 128/32 256/32 512/32 128/16 128/32 256/32 512/32
5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5
2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2
TABLE
PIC32MX FEATURES
Dedicated Channels Programmable Channels Comparators
Device
Pins
Program/Data Memory (KB)
Timers/ Capture/ Compare
EUART/ 10-bit SPI/ (ch)
VREG
Trace
PIC32MX420F032H PIC32MX440F128H PIC32MX440F256H PIC32MX440F512H PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L
32/8 128/32 256/32 512/32 128/32 256/32 512/32
5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5
2/1/2 2/2/2 2/1/2 2/1/2 2/2/2 2/2/2 2/2/2
DS61143E-page
2008 Microchip Technology Inc.
JTAG
JTAG
PIC32MX3XX/4XX
Diagram (64-Pin General Purpose)
64-Pin TQFP (General Purpose)
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1
PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/RTCC/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 SCL1/RG2 SDA1/RG3 U1RTS/BCLK1/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
PIC32MX3XXH
2008 Microchip Technology Inc.
PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/CVREFOUT/PMA13/AN10/RB10 TDO/PMA12/AN11/RB11 TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMALL/PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5
DS61143E-page
PIC32MX3XX/4XX
Diagram (100-Pin General Purpose)
100-Pin TQFP (General Purpose)
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 PMD10/RF1 PMD11/RF0 ENVREG VCAP/VDDCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 PMD13/CN19/RD13 PMD12/IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 TMS/RA0 INT1/RE8 INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0
PIC32MX3XXL
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/RD11 IC3/PMCS2/PMA15/RD10 IC2/RD9 IC1/RTCC/RD8 INT4/RA15 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKI/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
DS61143E-page
PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/CVREF-/RA9 PMA6/VREF+/CVREF+/RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 CVREFOUT/PMA13/AN10/RB10 PMA12/AN11/RB11 TCK/RA1 U2RTS/BCLK2/RF13 U2CTS/RF12 PMA11/AN12/RB12 PMA10/AN13/RB13 PMALH/PMA1/AN14/RB14 PMALL/PMA0/AN15/OCFB/CN12/RB15 CN20/U1CTS/RD14 U1RTS/BCLK1/CN21/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
Diagram (64-Pin USB)
64-Pin TQFP (USB)
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 OC4/U1TX/RD3 OC3/U1RX/RD2 OC2/U1RTS/BCLK1/RD1
PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VBUSON/C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/CN4/RB2
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/SCL1/RD10 IC2/U1CTS//INT2/SDA1/RD9 IC1/RTCC/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
PIC32MX4XXH
2008 Microchip Technology Inc.
PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/CVREFOUT/PMA13/AN10/RB10 TDO/PMA12/AN11/RB11 TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMALL/PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5
DS61143E-page
PIC32MX3XX/4XX
Diagram (100-Pin USB)
100-Pin TQFP (USB)
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 PMD10/RF1 PMD11/RF0 ENVREG VCAP/VDDCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 PMD13/CN19/RD13 PMD12/IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 SDI1/T5CK/RC4 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 TMS/RA0 INT1/RE8 INT2/RE9 VBUSON/C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/CN4/RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0
PIC32MX4XXL
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 IC3/SCKI/PMCS2/PMA15/RD10 IC2/SS1/RD9 IC1/RTCC/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKI/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS U1TX/RF8 U1RX/RF2 USBID/RF3
PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/CVREF-/RA9 PMA6/VREF+/CVREF+/RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 CVREFOUT/PMA13/AN10/RB10 PMA12/AN11/RB11 TCK/RA1 U2RTS/BCLK2/RF13 U2CTS/RF12 PMA11/AN12/RB12 PMA10/AN13/RB13 PMALH/PMA1/AN14/RB14 PMALL/PMA0/AN15/OCFB/CN12/RB15 CN20/U1CTS/RD14 U1RTS/BCLK1/CN21/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5
DS61143E-page
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
Table Contents
High-Performance MIPS-Based 32-bit Flash Microcontroller 64/100-Pin General Purpose Device Overview PIC32MX MCU. Instruction Oscillators. Resets Memory Organization Flash Program Memory. Interrupts Prefetch Cache. 10.0 Direct Memory Access (DMA) Controller 11.0 On-The-Go. 12.0 Ports 13.0 Timer1 14.0 Timers 15.0 Input Capture. 16.0 Output Compare. 17.0 Serial Peripheral Interface (SPI). 18.0 Inter-Integrated Circuit (I2CTM) 19.0 Universal Asynchronous Receiver Transmitter (UART) 20.0 Parallel Master Port. 21.0 Real-Time Clock Calendar (RTCC). 22.0 Analog-Digital Converter 23.0 Power Saving 24.0 Comparator 25.0 Comparator Reference. 26.0 Watchdog Timer 27.0 Special Features 28.0 Programming Diagnostics 29.0 Development Support. 30.0 Electrical Characteristics 31.0 Packaging Information. Index Worldwide Sales Service
2008 Microchip Technology Inc.
DS61143E-page
PIC32MX3XX/4XX
VALUED CUSTOMERS
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Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) When contacting sales office, please specify which device, revision silicon data sheet (include literature number) using.
Customer Notification System
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DS61143E-page
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
64/100-Pin General Purpose USB, 32-bit Flash Microcontrollers
DEVICE OVERVIEW
1.2.1
Core Features
32-BIT RISC ARCHITECTURE
This document contains device specific information following devices: PIC32MX320F032H PIC32MX320F064H PIC32MX320F128H PIC32MX320F128L PIC32MX340F128H PIC32MX340F128L PIC32MX340F256H PIC32MX340F512H PIC32MX360F256L PIC32MX360F512L PIC32MX420F032H PIC32MX440F256H PIC32MX440F128H PIC32MX440F128L PIC32MX440F512H PIC32MX460F256L PIC32MX460F512L
Central PIC32MX3XX/4XX devices 32-bit MIPS32 core, offering wide range features, including following: 1.56 DMIPS/MHz 32-bit Address Data paths 32-bit Linear (program space) addressing thirty-two element 32-bit core register files Single-cycle multiply high-performance divide unit 32-bit integer math 32-bit instructions, optimized high-level languages, such `C'.
Power-Saving Technology
devices PIC32MX family incorporate range features that significantly reduce power consumption during operation. features include: On-the-Fly Clock Switching: device clock changed under software control four clock sources during operation. Instruction-Based Power-Saving Modes: microcontroller suspend operations, selectively shut down core while leaving peripherals active, with single instruction software.
This family introduces line Microchip devices: 32-bit RISC microcontroller family with broad peripheral feature enhanced computational performance. PIC32MX3XX/4XX family offers migration option those high-performance applications which outgrowing their 16-bit platforms.
Easy Migration
Communications
PIC32MX family microcontrollers designed provide easy migration path application needs change. consistent pinout scheme used throughout entire family aids migrating next larger device. This true when moving between devices with same count, even jumping from 64-pin 100-pin devices. PIC32MX family peripheral compatible with Microchip PIC24FJ128GA010 devices.
PIC32MX incorporates range serial communication peripherals handle range application requirements. devices equipped with independent UARTs with built-in IrDA encoder/decoders. There also independent modules, independent modules that support both Master Slave modes operation.
10-bit Converter
Converter features ksps maximum sample rate. This configurable module incorporates userselectable scan list auto-convert functions allow acquisitions without processor intervention. Multiple trigger sources user-selectable: timer event, external pin, manual auto-convert.
2008 Microchip Technology Inc.
DS61143E-page
PIC32MX3XX/4XX
External Interface
Parallel Master Port Parallel Slave Port enables 8/16bit parallel data communications Master mode with address lines; 8-bit Slave modes also supported.
Real-Time Clock/Calendar
This module implements full-featured clock calendar with alarm functions hardware, freeing timer resources program memory space core application.
Oscillator Options Features
devices PIC32MX family offer four different oscillator options, allowing users range choices developing application hardware. These include: Primary Oscillator (POSC) with External Crystal modes using crystals ceramic resonators. External Clock modes with selectable peripheral clock output. Fast Internal Oscillator (FRC) with nominal output. On-board postscalers and/or provide clock speeds ranging from maximum specified frequency. Secondary Oscillator (SOSC) designed operate with external 32.768 crystal. This oscillator also used with Timer1 integrated RTCC. Internal Low-Power oscillator (LPRC) having fixed output, which provides low-power option timing-insensitive applications. oscillator block also provides stable reference source user-controlled Fail-Safe Clock Monitor. This option constantly monitors main clock source against reference signal provided internal oscillator enables controller switch internal oscillator, allowing continued low-speed operation safe application shutdown.
DS61143E-page
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
Device Features, Block Diagrams Pinout Tables
DEVICE FEATURES, BLOCK DIAGRAMS PINOUT TABLES
PIC32MX320F032H PIC32MX320F064H PIC32MX320F128H PIC32MX340F256H PIC32MX320F128L PIC32MX360F256L PIC32MX360F512L 512K Instruction, Data POR, BOR, MCLR, WDT, (Software Reset), (Configuration Mismatch) (PWRT, OST, Lock) MIPS32® Enhanced Architecture (Release MIPS16eCode Compression Packages 64-pin TQFP 100-pin TQFP
TABLE 1-1:
Features
Operating Frequency Program Memory (Bytes) Data Memory (Bytes) Interrupt Sources/Vectors Ports Total Pins Channels Timers: Total number (16-bit) 32-bit (paired 16-bit) 32-bit core timer Input Capture Channels Output Compare/PWM Channels Input Change Interrupt Notification Serial Communications: Enhanced UART (3-wire/4-wire)
2C
128K
256K Ports Ports 128K 256K
Yes, 8-bit only Yes, 8-bit/16-bit
Parallel Communications (PMP/PSP) JTAG Boundary Scan JTAG Debug Program ICSP2-Wire Debug Program Instruction Trace Hardware Break Points 10-bit Analog-to-Digital Module (input channels) Analog Comparators Internal Resets (and delays) Instruction Support
2008 Microchip Technology Inc.
DS61143E-page
PIC32MX3XX/4XX
TABLE 1-2: DEVICE FEATURES PIC32MX3XXFXXX GENERAL PURPOSE FAMILY
PIC32MX340F128H PIC32MX340F512H PIC32MX340F128L 128K Ports Yes, 8-bit only Instruction, Data POR, BOR, MCLR, WDT, (Software Reset), (Configuration Mismatch) (PWRT, OST, Lock) MIPS32® Enhanced Architecture (Release MIPS16eCode Compression Packages 64-pin TQFP 100-pin TQFP Yes, 8-bit/16-bit
2008 Microchip Technology Inc.
Features
Operating Frequency Program Memory (Bytes) Data Memory (Bytes) Interrupt Sources/Vectors Ports Total Pins Channels Timers: Total number (16-bit) 32-bit (paired 16-bit) 32-bit core timer Input Capture Channels Output Compare/PWM Channels Input Change Interrupt Notification Serial Communications: Enhanced UART (3-wire/4-wire)
2C
128K 512K Ports
Parallel Communications (PMP/PSP) JTAG Boundary Scan JTAG Debug Program ICSP2-Wire Debug Program Instruction Trace Hardware Break Points 10-bit Analog-to-Digital Module (input channels) Analog Comparators Internal Resets (and delays)
Instruction Support
DS61143E-page
PIC32MX3XX/4XX
TABLE 1-3: DEVICE FEATURES PIC32MX4XXFXXX FAMILY
PIC32MX420F032H PIC32MX440F128H PIC32MX440F256H PIC32MX440F512H PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L 512K Instruction, Data POR, BOR, MCLR, WDT, (Software Reset), (Configuration Mismatch) (PWRT, OST, Lock) MIPS32 Enhanced Architecture (Release MIPS16eCode Compression Packages 64-pin TQFP 100-pin TQFP
DS61143E-page
Features
Operating Frequency Program Memory (Bytes) Data Memory (Bytes) Interrupt Sources Vectors Ports Total Pins Channels Timers: Total number (16-bit) 32-bit (from paired 16-bit timers) 32-bit Core Timer Input Capture Channels Output Compare/PWM Channels Input Change Interrupt Notification Serial Communications: Enhanced UART (3-wire/4-wire) I2CParallel Communications (PMP/PSP) JTAG Boundary Scan JTAG Debug Program ICSP 2-wire Debug Program Instruction Trace Hardware Break Points: 10-bit Analog-to-Digital Module (input channels) Analog Comparators Internal Resets (and Delays) Instruction Support
128K 256K
512K Ports Ports 128K 256K
Yes, 8-bit only Yes, 8-bit/16-bit
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 1-1: PIC32MX3XX BLOCK DIAGRAM (GENERAL PURPOSE)
VDDCORE/VCAP OSC2/CLKO OSC1/CLKI OSC/SOSC Oscillators FRC/LPRC Oscillators DIVIDERS Precision Band Reference SYSCLK Timing Generation PBCLK ENVREG Voltage Regulator
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(3)
VDD, MCLR
Peripheral Clocked SYSCLK CN1-22(1) PORTA(1,4) JTAG BSCAN Interrupt Controller OC1-5 EJTAG DMAC(2) MIPS32® M4KCPU Core PORTC(1) PORTD
Peripheral Clocked PBCLK
PORTB
IC1-5
Matrix
SPI1,2(1)
I2C1,2 Prefetch Module(2) Peripheral Bridge PMP(1)
PORTE(1)
Data
PORTF(1)
128-bit Wide Program Flash Memory Flash Controller
UART1,2
PORTG(1)
Comparators
Peripheral Clocked PBCLK
Timer1
Timer2
Timer3
Timer4
Timer5
RTCC
10-bit
Note
pins features implemented device pinout configurations. Table port descriptions. Some features available certain devices. functionality provided when on-board voltage regulator enabled. PORTA present 64-pin devices
DS61143E-page
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 1-2: PIC32MX4XX BLOCK DIAGRAM (USB)
VDDCORE/VCAP OSC2/CLKO OSC1/CLKI OSC/SOSC Oscillators FRC/LPRC Oscillators DIVIDERS PLL-USB USBCLK SYSCLK Timing Generation PBCLK Precision Band Reference ENVREG Voltage(1) Regulator
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(2)
VDD, MCLR
Peripheral Clocked SYSCLK CN1-22(1) PORTA(1,4) JTAG BSCAN Priority Interrupt Controller EJTAG DMAC(1) MIPS Core PORTC(1) PORTD(1) Matrix PORTE(1) Pre-Fetch Module(1)
Data
Peripheral Clocked PBCLK
PORTB
1,2(1)
Peripheral Bridge PMP(1)
PORTF(1)
128-bit wide Program Flash Memory Flash Controller
UART
PORTG(1)
Comparators
Peripheral Clocked PBCLK
Timer1
Timer2
Timer3
Timer4
Timer5
RTCC
10-bit
Note
pins features implemented device pinout configurations. Table port descriptions. Some features available certain device variants. functionality provided when on-board voltage regulator enabled. PORTA present devices
2008 Microchip Technology Inc.
DS61143E-page
PIC32MX3XX/4XX
TABLE 1-4:
Function 64-pin AN10 AN11 AN12 AN13 AN14 AN15 AVDD AVSS BCLK1 BCLK2 C1INC1IN+ C1OUT C2INC2IN+ C2OUT CLKI CLKO Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS GENERAL PURPOSE
Number Input Buffer Positive Supply Analog Modules Ground Reference Analog Modules UART1 IrDA® Baud Clock UART2 IrDA Baud Clock Comparator Negative Input Comparator Positive Input Comparator Output Comparator Negative Input Comparator Positive Input Comparator Output Main Clock Input Connection System Clock Output Analog Inputs Description
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-4:
Function 64-pin CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 CVREFCVREF+ CVREFOUT EMUC1 EMUD1 EMUC2 EMUD2 ENVREG INT0 INT1 INT2 INT3 INT4 MCLR Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS GENERAL PURPOSE (CONTINUED)
Number Input Buffer Master Clear (Device Reset) Input. Bring this line cause Reset. External Interrupt Inputs Comparator Reference Voltage (Low) Input Comparator Reference Voltage (High) Input Comparator Voltage Reference Output In-Circuit Emulator Clock Input/Output In-Circuit Emulator Data Input/Output In-Circuit Emulator Clock Input/Output In-Circuit Emulator Data Input/Output Enable On-Chip Voltage Regulator Input Capture Inputs Interrupt-on-Change Inputs Interrupt-on-Change Inputs Description
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-4:
Function 64-pin OCFA OCFB OSC1 OSC2 PGC1 PGD1 PGC2 PGD2 PMALL PMALH PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMA14 PMA15 PMCS1 PMCS2 Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS GENERAL PURPOSE (CONTINUED)
Number Input Buffer Parallel Master Port Chip Select Strobe Parallel Master Port Chip Select Strobe Output Compare Fault Input Output Compare Fault Input Main Oscillator Input Connection Main Oscillator Output Connection. In-Circuit Debugger ICSPProgramming Clock In-Circuit Debugger ICSP Programming Data In-Circuit Debugger ICSPProgramming Clock In-Circuit Debugger ICSP Programming Data Parallel Master Port Address Latch Enable low-byte (Multiplexed Master modes) Parallel Master Port Address Latch Enable high-byte (Multiplexed Master modes) Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes) Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes) Parallel Master Port Address (Demultiplexed Master modes) Description Output Compare/PWM Outputs
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-4:
Function 64-pin PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15 PMENB PMRD PMRD/PMWR PMWR Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS GENERAL PURPOSE (CONTINUED)
Number Input Buffer ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL Parallel Master Port Enable Strobe (Master Mode Parallel Master Port Read Strobe (Master Mode Parallel Master Port Read/Write Strobe (Master Mode Parallel Master Port Write Strobe (Master Mode Description Parallel Master Port Data (Demultiplexed Master mode) Address/Data (Multiplexed Master modes)
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-4:
Function 64-pin RA10 RA14 RA15 RB10 RB11 RB12 RB13 RB14 RB15 RC12 RC13 RC14 RC15 Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS GENERAL PURPOSE (CONTINUED)
Number Input Buffer PORTC Digital PORTA Digital Notes: 100-pin devices, JTAG program/debug port multiplexed with port pins RA0, RA1, RA5. Reset, these pins controlled JTAG port. these pins general purpose I/O, user's application code must clear JTAGEN (DDPCON<3>) these pins JTAG program/debug, user's application code must maintain JTAGEN specific 100-pin devices, instruction TRACE port multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 RG14. Power-on Reset, these pins general purpose pins. maintain these pins general purpose pins, user's application code must maintain TROEN (DDPCON<2>) these pins instruction TRACE pins, TROEN must PORTB Digital Note: 64-pin devices, JTAG program/debug port multiplexed with port pins RB10, RB11, RB12 RB13. Reset, these pins controlled JTAG port. these pins general purpose I/O, user's application code must clear JTAGEN (DDPCON<3>) these pins JTAG program/debug, user's application code must maintain JTAGEN Description
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-4:
Function 64-pin RD10 RD11 RD12 RD13 RD14 RD15 RF12 RF13 Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS GENERAL PURPOSE (CONTINUED)
Number Input Buffer PORTF Digital PORTE Digital PORTD Digital Description
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-4:
Function 64-pin RG12 RG13 RG14 RG15 RTCC SCK1 SCK2 SCL1 SCL2 SDA1 SDA2 SDI1 SDI2 SDO1 SDO2 SOSCI SOSCO T1CK T2CK T3CK T4CK T5CK TRCLK TRD0 TRD1 TRD2 TRD3 Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS GENERAL PURPOSE (CONTINUED)
Number Input Buffer
Description PORTG Digital Note: specific 100-pin devices, Instruction TRACE port multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13, RG14. power-on-reset, these pins general purpose pins. maintain these pins general purpose pins, user's application code must maintain TROEN (DDPCON<2>) these pins Instruction TRACE pins, TROEN must
Real-Time Clock Alarm Output SPI1 Serial Clock Output SPI2 Serial Clock Output I2C1 Synchronous Serial Clock Input/Output I2C2 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output I2C2 Data Input/Output SPI1 Serial Data Input SPI2 Serial Data Input SPI1 Serial Data Output SPI2 Serial Data Output Secondary Oscillator/Timer1 External Clock Input Secondary Oscillator/Timer1 External Clock Output Slave Select Input/Frame Select Output (SPI1) Slave Select Input/Frame Select Output (SPI2) Timer1 External Clock Input Timer2 External Clock Input Timer3 External Clock Input Timer4 External Clock Input Timer5 External Clock Input JTAG Test Clock/Programming Clock Input JTAG Test Data/Programming Data Input JTAG Test Data Output JTAG Test Mode Select Input Trace Clock Trace Data Trace Data Trace Data Trace Data
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-4:
Function 64-pin U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX VDDCAP VDDCORE VREFVREF+ Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS GENERAL PURPOSE (CONTINUED)
Number Input Buffer UART1 Clear Send Input UART1 Request Send Output UART1 Receive UART1 Transmit Output UART2 Clear Send Input UART2 Request Send Output UART Receive Input UART2 Transmit Output Positive Supply Peripheral Digital Logic pins External Filter Capacitor Connection (regulator enabled) Positive Supply Microcontroller Core Logic (regulator disabled) Reference Voltage (Low) Input Reference Voltage (High) Input Ground Reference Logic pins Description
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-5:
Function 64-pin AN10 AN11 AN12 AN13 AN14 AN15 AVDD AVSS BCLK1 BCLK2 C1INC1IN+ C1OUT C2INC2IN+ C2OUT CLKI CLKO Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS
Number Input Buffer Positive Supply Analog Modules Ground Reference Analog Modules UART1 IrDA® Baud Clock UART2 IrDA® Baud Clock Comparator Negative Input Comparator Positive Input Comparator Output Comparator Negative Input Comparator Positive Input Comparator Output Main Clock Input Connection System Clock Output Analog Inputs Description
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-5:
Function 64-pin CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 CVREFCVREF+ CVREFOUT DEMUC1 EMUD1 EMUC2 EMUD2 ENVREG Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS (CONTINUED)
Number Input Buffer Comparator Reference Voltage (Low) Input Comparator Reference Voltage (High) Input Comparator Voltage Reference Output DIn-Circuit Emulator Clock Input/Output In-Circuit Emulator Data Input/Output In-Circuit Emulator Clock Input/Output In-Circuit Emulator Data Input/Output Enable On-Chip Voltage Regulator Input Capture Inputs Interrupt-on-Change Inputs Interrupt-on-Change Inputs Description
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-5:
Function 64-pin INT0 INT1 INT2 INT3 INT4 MCLR OCFA OCFB OSC1 OSC2 PGC1 PGD1 PGC2 PGD2 PMALL PMALH Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS (CONTINUED)
Number Input Buffer Output Compare Fault Input Output Compare Fault Input Main Oscillator Input Connection Main Oscillator Output Connection In-Circuit Debugger ICSPProgramming Clock In-Circuit Debugger ICSP Programming Data In-Circuit Debugger ICSPProgramming Clock In-Circuit Debugger ICSP Programming Data Parallel Master Port Address Latch Enable low-byte (Multiplexed Master modes) Parallel Master Port Address Latch Enable high-byte (Multiplexed Master modes) Master Clear (Device Reset) Input Bring this line cause Reset. Output Compare/PWM Outputs External Interrupt Inputs Description
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-5:
Function 64-pin PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMA14 PMA15 PMCS1 PMCS2 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15 PMENB PMRD PMRD/PMWR PMWR Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS (CONTINUED)
Number Input Buffer ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL Parallel Master Port Enable Strobe (Master mode Parallel Master Port Read Strobe (Master mode Parallel Master Port Read/Write Strobe (Master mode Parallel Master Port Write Strobe (Master mode Address Address Parallel Master Port Chip Select Strobe Parallel Master Port Chip Select Strobe Parallel Master Port Data (Demultiplexed Master mode) Address/Data (Multiplexed Master modes) Description Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes) Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes) Parallel Master Port Address (Demultiplexed Master modes)
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-5:
Function 64-pin RA10 RA14 RA15 RB10 RB11 RB12 RB13 RB14 RB15 RC12 RC13 RC14 RC15 Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS (CONTINUED)
Number Input Buffer PORTC Digital PORTA Digital Notes: 100-pin devices, JTAG program/debug port multiplexed with port pins RA0, RA1, RA5. Reset, these pins controlled JTAG port. these pins general purpose I/O, user's application code must clear JTAGEN (DDPCON<3>) these pins JTAG program/debug, user's application code must maintain JTAGEN specific 100-pin devices, instruction TRACE port multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 RG14. Power-on Reset, these pins general purpose pins. maintain these pins general purpose pins, user's application code must maintain TROEN (DDPCON<2>) these pins instruction TRACE pins, TROEN must PORTB Digital Note: 64-pin devices, JTAG program/debug port multiplexed with port pins RB10, RB11, RB12 RB13. Reset, these pins controlled JTAG port. these pins general purpose I/O, user's application code must clear JTAGEN (DDPCON<3>) these pins JTAG program/debug, user's application code must maintain JTAGEN Description
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-5:
Function 64-pin RD10 RD11 RD12 RD13 RD14 RD15 RF12 RF13 Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS (CONTINUED)
Number Input Buffer PORTF Digital PORTE Digital PORTD Digital Description
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-5:
Function 64-pin RG12 RG13 RG14 RG15 RTCC SCK1 SCK2 SCL1 SCL2 SDA1 SDA2 SDI1 SDI2 SDO1 SDO2 SOSCI SOSCO T1CK T2CK T3CK T4CK T5CK TRCLK TRD0 TRD1 TRD2 TRD3 Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS (CONTINUED)
Number Input Buffer SPI2 Serial Data Output Secondary Oscillator/Timer1 External Clock Input Secondary Oscillator/Timer1 External Clock Output Slave Select Input/Frame Select Output (SPI1) Slave Select Input/Frame Select Output (SPI2) Timer1 External Clock Input Timer2 External Clock Input Timer3 External Clock Input Timer4 External Clock Input Timer5 External Clock Input JTAG Test Clock/Programming Clock Input JTAG Test Data/Programming Data Input JTAG Test Data Output JTAG Test Mode Select Input Trace Clock Trace Data Trace Data Trace Data Trace Data SPI2 Serial Data Input
Description PORTG Digital Note: specific 100-pin devices, instruction TRACE port multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 RG14. Power-on Reset, these pins general purpose pins. maintain these pins general purpose pins, user's application code must maintain TROEN (DDPCON<2>) these pins instruction TRACE pins, TROEN must
Real-Time Clock Alarm Output SPI2 Serial Clock Output I2C1 Synchronous Serial Clock Input/Output I2C2 Synchronous Serial Clock Input/Output I2C1 Data Input/Output I2C2 Data Input/Output
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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TABLE 1-5:
Function 64-pin U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX VDDCAP VDDCORE VREFVREF+ VBUS VUSB VBUSON USBID Legend: Note: 100-pin
PIC32MX3XX/4XX PINOUT DESCRIPTIONS (CONTINUED)
Number Input Buffer UART1 Clear Send Input UART1 Request Send Output UART1 Receive UART1 Transmit Output UART2 Clear Send Input UART2 Request Send Output UART Receive Input UART2 Transmit Output Positive Supply Peripheral Digital Logic pins External Filter Capacitor Connection (regulator enabled) Positive Supply Microcontroller Core Logic (regulator disabled) Comparator Reference Voltage (Low) Input Comparator Reference Voltage (High) Input Ground Reference Logic pins Power Monitor Internal Transceiver Supply Host Power Control Output Detect Description
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer some cases, pins multiplexed with more than peripheral. general, dominant output control multiplexed determined order peripheral output names assigned (read from left right). Multiplexed peripheral inputs have priority.
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NOTES:
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Note:
PIC32MX
This data sheet summarizes features PIC32MX3XX/4XX Family devices. intended comprehensive reference source. Refer "PIC32MX Family Reference Manual" (DS61132) detailed description PIC32MX mcu. Resources MIPS32® M4K® Processor Core available mips32-m4k/#.
module heart PIC32MX3XX/4XX Family processor. fetches instructions, decodes each instruction, fetches source operands, executes each instruction writes results instruction execution proper destinations.
Features
Autonomous Multiply/Divide Unit Maximum issue rate 32x16 multiply clock Maximum issue rate 32x32 multiply every other clock Early-in iterative divide. Minimum maximum clock latency (dividend (rs) sign extension-dependent) Power Control Minimum frequency: Low-Power mode (triggered WAIT instruction) Extensive local gated clocks EJTAG Debug Instruction Trace Support single stepping Virtual instruction data address/value breakpoints tracing with trace compression
5-stage pipeline 32-bit Address Data Paths MIPS32 Enhanced Architecture (Release Multiply-Accumulate Multiply-Subtract Instructions Targeted Multiply Instruction Zero/One Detect Instructions WAIT Instruction Conditional Move Instructions (MOVN, MOVZ) Vectored interrupts Programmable exception vector base Atomic interrupt enable/disable shadow registers minimize latency interrupt handlers field manipulation instructions MIPS16eCode Compression 16-bit encoding 32-bit instructions improve code density Special PC-relative instructions efficient loading addresses constants SAVE RESTORE macro instructions setting tearing down stack frames within subroutines Improved support handling 16-bit data types Simple Fixed Mapping Translation (FMT) mechanism Simple Dual Interface Independent 32-bit address data busses Transactions aborted improve interrupt latency
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Architecture Overview
PIC32MX3XX/4XX Family core contains several logic blocks working together parallel, providing efficient high performance computing engine. following blocks included with core: Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal interfaces Power Management MIPS16e Support Enhanced JTAG (EJTAG) Controller
FIGURE 2-1:
BLOCK DIAGRAM
EJTAG Trace
Trace Off-Chip Debug
Interface
Dual
System Coprocessor
Power Mgmt
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Matrix
Execution Core (RF/ALU/Shift)
PIC32MX3XX/4XX
2.2.1 EXECUTION UNIT 2.2.2 MULTIPLY/DIVIDE UNIT (MDU)
PIC32MX3XX/4XX Family core execution unit implements load/store architecture with single-cycle operations (logical, shift, add, subtract) autonomous multiply/divide unit. core contains thirty-two 32-bit general purpose registers used integer operations address calculation. additional register file shadow (containing thirty-two registers) added minimize context switching overhead during interrupt/exception processing. register file consists read ports write port fully bypassed minimize operation latency pipeline. execution unit includes: 32-bit adder used calculating data address Address unit calculating next instruction address Logic branch determination branch target address calculation Load aligner Bypass multiplexers used avoid stalls when executing instructions streams where data producing instructions followed closely consumers their results Leading Zero/One detect unit implementing instructions Arithmetic Logic Unit (ALU) performing bitwise logical operations Shifter Store Aligner PIC32MX3XX/4XX Family core includes multiply/divide unit (MDU) that contains separate pipeline multiply divide operations. This pipeline operates parallel with integer unit (IU) pipeline does stall when pipeline stalls. This allows operations partially masked system stalls and/or other integer unit instructions. high-performance consists 32x16 booth recoded multiplier, result/accumulation registers LO), divide state machine, necessary multiplexers control logic. first number shown (`32' 32x16) represents operand. second number (`16' 32x16) represents operand. PIC32MX core only checks value latter (rt) operand determine many times operation must pass through multiplier. 16x16 32x16 operations pass through multiplier once. 32x32 operation passes through multiplier twice. supports execution 16x16 32x16 multiply operation every clock cycle; 32x32 multiply operations issued every other clock cycle. Appropriate interlocks implemented stall issuance back-to-back 32x32 multiply operations. multiply operand size automatically determined logic built into MDU. Divide operations implemented with simple clock iterative algorithm. early-in detection checks sign extension dividend (rs) operand. bits wide, iterations skipped. 16bit-wide iterations skipped, 24-bitwide iterations skipped. attempt issue subsequent instruction while divide still active causes pipeline stall until divide operation completed. Table lists repeat rate (peak issue rate cycles until operation reissued) latency (number cycles until result available) PIC32MX core multiply divide instructions. approximate latency repeat rates listed terms pipeline clocks.
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TABLE 2-1: PIC32MX3XX/4XX FAMILY CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES REPEAT RATES
Opcode MULT/MULTU, MADD/MADDU, MSUB/MSUBU DIV/DIVU Operand Size (mul (div bits bits bits bits bits bits bits bits MIPS architecture defines that result multiply divide operation placed registers. Using Move-From-HI (MFHI) MoveFrom-LO (MFLO) instructions, these values transferred general purpose register file. addition HI/LO targeted operations, MIPS32 architecture also defines multiply instruction, MUL, which places least significant results primary register file instead HI/LO register pair. avoiding explicit MFLO instruction, required when using register, supporting multiple destination registers, throughput multiply-intensive operations increased. other instructions, multiply-add (MADD) multiply-subtract (MSUB), used perform multiply-accumulate multiply-subtract operations. MADD instruction multiplies numbers then adds product current contents registers. Similarly, MSUB instruction multiplies operands then subtracts product from registers. MADD MSUB operations commonly used algorithms. Latency Repeat Rate
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2.2.3 SYSTEM CONTROL COPROCESSOR (CP0)
MIPS architecture, responsible virtual-to-physical address translation, exception control system, processor's diagnostics capability, operating modes (kernel, user, debug), whether interrupts enabled disabled. Configuration information, such presence options like MIPS16e, also available accessing registers, listed Table 2-2.
TABLE 2-2:
COPROCESSOR REGISTERS
Function Reserved PIC32MX3XX/4XX Family core Enables access RDHWR instruction selected hardware registers Reports address most recent address-related exception Processor cycle count Reserved PIC32MX3XX/4XX Family core Timer interrupt control Processor status control Interrupt system status control Shadow register status control Provides mapping from vectored interrupt shadow Cause last general exception Program counter last exception Processor identification revision Exception vector base register Configuration register Configuration register Configuration register Configuration register Reserved PIC32MX3XX/4XX Family core Debug control exception status Program counter last debug exception Reserved PIC32MX3XX/4XX Family core Program counter last error Debug handler scratchpad register
Register Register Number Name 17-22 25-29 Note Reserved HWREna BadVAddr(1) Count(1) Reserved Compare(1) Status(1) IntCtl(1) SRSCtl(1) SRSMap(1) Cause(1)
PRId EBASE Config Config1 Config2 Config3 Reserved Debug
DEPC(2) Reserved ErrorEPC(1) DESAVE(2)
Registers used exception processing. Registers used during debug.
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Coprocessor also contains logic identifying managing exceptions. Exceptions caused variety sources, including alignment errors data, external events, program errors. Table shows exception types order priority.
TABLE 2-3:
Exception Reset DINT Interrupt AdEL DDBL DDBS AdEL AdES DDBL
PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES
Description Assertion MCLR Power-On Reset (POR) EJTAG Debug Single Step EJTAG Debug Interrupt. Caused assertion external EJ_DINT input, setting EjtagBrk register Assertion signal Assertion unmasked hardware software interrupt signal EJTAG debug hardware instruction break matched Fetch address alignment error Fetch reference protected address Instruction fetch error EJTAG Breakpoint (execution SDBBP instruction) Execution SYSCALL instruction Execution BREAK instruction Execution Reserved Instruction Execution coprocessor instruction coprocessor that enabled Execution CorExtend instruction when CorExtend enabled Execution arithmetic instruction that overflowed Execution trap (when trap condition true) EJTAG Data Address Break (address only) EJTAG Data Value Break Store (address value) Load address alignment error Load reference protected address Store address alignment error Store protected address Load store error EJTAG data hardware breakpoint matched load data compare
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2.2.4 INTERRUPT HANDLING 2.2.5 SHADOW REGISTERS
PIC32MX3XX/4XX Family core includes support peripheral interrupts, software interrupts, timer interrupt. PIC32MX uses MIPS External Interrupt Controller (EIC) mode, which redefines which interrupts handled provide full support external interrupt controller handling prioritization vectoring interrupts. This presence this mode denoted VEIC Config3 register. PIC32MX core, VEIC always indicate presence external interrupt controller. Note: Although mode designated "External", interrupt controller on-chip. Release MIPS32 Architecture optionally removes need save restore GPRs entry high priority interrupts exceptions, provide specified processor modes with same capability. This done introducing multiple copies GPRs, called "shadow sets", allowing privileged software associate shadow with entry kernel mode interrupt vector exception. normal GPRs logically considered shadow zero. PIC32MX3XX/4XX Family core implements sets registers, normal GPRs, shadow set. This indicated SRSCtlHSS field.
interrupt controller specifies which shadow should used upon entry particular vector. shadow registers further improve interrupt latency avoiding need save context when invoking interrupt handler.
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Modes Operation
PIC32MX3XX/4XX Family core supports three modes operation: user mode, kernel mode debug mode. User mode most often used applications programs. Kernel mode typically used handling exceptions operating system kernel functions, including management device accesses. additional Debug mode used during system bring-up software development. Refer EJTAG specification more information Debug mode.
FIGURE 2-2:
PIC32MX3XX/4XX FAMILY CORE VIRTUAL ADDRESS
0xFFFFFFFF
Fixed Mapped
0xFF400000 0xFF3FFFFF 0xFF200000 0xF1FFFFFF 0xE0000000 0xDFFFFFFF
Memory/EJTAG(1) Fixed Mapped
kseg3
Kernel Virtual Address Space Fixed Mapped, Kernel Virtual Address Space Unmapped, Uncached Kernel Virtual Address Space Unmapped,
kseg2
0xC0000000 0xBFFFFFFF
kseg1
0xA0000000 0x9FFFFFFF
kseg0
0x80000000 0x7FFFFFFF
User Virtual Address Space Fixed Mapped, 2048
kuseg
0x00000000
Note This space mapped memory user kernel mode, EJTAG module Debug mode.
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2.3.1 FIXED MAPPING TRANSLATION
PIC32MX3XX/4XX Family core provides simple Fixed Mapping Translation (FMT) mechanism that smaller simpler than full Translation Lookaside Buffer (TLB) found other MIPS cores. Like TLB, performs virtual-to-physical address translation provides attributes different segments. Those segments that unmapped implementation (kseg0 kseg1) translated identically FMT. Figure shows implemented PIC32MX core.
FIGURE 2-3:
ADDRESS TRANSLATION DURING MEMORY ACCESS
Virtual Address Instruction Address Calculator
Physical Address
Instn SRAM SRAM Interface Data SRAM
Physical Address
Data Address Calculator Virtual Address
general, also determines cacheability each segment. These attributes controlled bits Config register. Table shows encoding (bits 30:28), (bits 27:25), (bits 2:0) fields Config register. PIC32MX core passes these Config fields Prefetch Cache module determine cacheability Program Memory Flash accesses. Table shows cacheability virtual address segments controlled these fields.
TABLE 2-4:
CACHE COHERENCY ATTRIBUTES
Cache Coherency Attribute Uncached Cacheable
Config Register Fields K23,
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PIC32MX3XX/4XX Family core, translation exceptions taken, although address errors still possible.
TABLE 2-5:
Segment useg/kuseg
CACHEABILITY SEGMENTS WITH FIXED MAPPING TRANSLATION
Virtual Address Range 0x0000_0000-0x7FFF_FFFF Cacheability Controlled field (bits 27:25) Config register. Figure mapping. This segment always uncached when Controlled field (bits 2:0) Config register. Figure mapping. Always uncacheable. Controlled field (bits 30:28) Config register. Figure mapping. Controlled field (bits 30:28) Config register. Figure mapping.
kseg0 kseg1 kseg2 kseg3
0x8000_0000- 0x9FFF_FFFF 0xA000_0000-0xBFFF_FFFF 0xC000_0000-0xDFFF_FFFF 0xE000_0000-0xFFFF_FFFF
performs simple translation from virtual addresses physical addresses. This mapping shown Figure 2-4.
FIGURE 2-4:
MEMORY (ERL PIC32MX3XX/4XX FAMILY CORE
Virtual Address kseg3 0xE000_0000 kseg2 0xC000_0000 kseg1 0xA000_0000 kseg0 0x8000_0000 useg/kuseg Physical Address kseg3 0xE000_0000 kseg2 0xC000_0000
useg/kuseg
0x4000_0000 reserved 0x2000_0000 kseg0/kseg1
0x0000_0000
0x0000_0000
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When useg kuseg become unmapped (virtual address identical physical address) uncached. This behavior same there TLB. This mapping shown Figure 2-5.
FIGURE 2-5:
PIC32MX3XX/4XX FAMILY CORE MEMORY (ERL
Virtual Address kseg3 0xE000_0000 kseg2 0xC000_0000 kseg1 0xA000_0000 kseg0 0x8000_0000 0x8000_0000 reserved Physical Address kseg3 0xE000_0000 kseg2 0xC000_0000
useg/kuseg
useg/kuseg
kseg0/kseg1 0x0000_0000 0x0000_0000
2.3.2
DUAL INTERNAL INTERFACES
2.3.3
MIPS16E EXECUTION
SRAM interface includes dual instruction data interfaces. dual interface enables independent connection instruction data devices. yields highest performance, since pipeline generate simultaneous requests which then serviced parallel. internal buses connected Matrix unit, which switch fabric that provides this parallel operation.
When core operating MIPS16e mode, instruction fetches only require bits data returned. improved efficiency, however, core will fetch bits instruction data whenever address word-aligned. Thus sequential MIPS16e code, fetches only occur every other instruction, resulting better performance reduced system power.
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Power Management
2.5.1 DEBUG REGISTERS
PIC32MX3XX/4XX Family core offers number power management features, including low-power design, active power management, power-down modes operation. core static design that supports slowing halting clocks, which reduces system power consumption during idle periods. Three debug registers (DEBUG, DEPC, DESAVE) have been added MIPS Coprocessor (CP0) register set. DEBUG register shows cause debug exception used setting singlestep operations. DEPC, Debug Exception Program Counter, register holds address which debug exception taken. This used resume program execution after debug operation finishes. Finally, DESAVE, Debug Exception Save, register enables saving general purpose registers used during execution debug exception handler. exit debug mode, Debug Exception Return (DERET) instruction executed. When this instruction executed, system exits debug mode, allowing normal execution application system code resume.
2.4.1
INSTRUCTION-CONTROLLED POWER MANAGEMENT
mechanism invoking power-down mode through execution WAIT instruction. more information power management, Section 23.0 "Power Saving".
2.4.2
LOCAL CLOCK GATING
majority power consumed PIC32MX3XX/4XX Family core clock tree clocking registers. PIC32MX family uses extensive local gated-clocks reduce this dynamic power consumption.
2.5.2
EJTAG HARDWARE BREAKPOINTS
EJTAG Debug Support
PIC32MX3XX/4XX Family core provides Enhanced JTAG (EJTAG) interface software debug application kernel code. addition standard user mode kernel modes operation, PIC32MX3XX/4XX Family core provides Debug mode that entered after debug exception (derived from hardware breakpoint, single-step exception, etc.) taken continues until debug exception return (DERET) instruction executed. During this time, processor executes debug exception handler routine. EJTAG interface operates through Test Access Port (TAP), serial communication port used transferring test data PIC32MX3XX/4XX Family core. addition standard JTAG instructions, special instructions defined EJTAG specification define what registers selected they used.
There several types simple hardware breakpoints defined EJTAG specification. These stop normal operation force system into debug mode. There types simple hardware breakpoints implemented PIC32MX3XX/4XX Family core: Instruction breakpoints Data breakpoints. PIC32MX3XX/4XX Family core data instruction breakpoints Instruction breaks occur instruction fetch operations, break virtual address. mask applied virtual address breakpoints range instructions. Data breakpoints occur load/store transactions. Breakpoints virtual address values, similar Instruction breakpoint. Data breakpoints load, store, both. Data breakpoints also based value load/store operation. Finally, masks applied both virtual address load/store value.
2.5.3
INSTRUCTION TRACING
PIC32MX3XX/4XX Family core includes Trace support real-time tracing instruction addresses. trace information collected off-chip memory, post-capture processing trace regeneration software. Off-chip trace memory accessed through special trace probe that consists data pins plus clock.
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Initialization
2.6.2 COPROCESSOR STATE
Software required initialize following parts device after Reset event: General Purpose Registers Coprocessor State Miscellaneous states need initialized prior leaving boot code. There various exceptions which blocked which cleared Reset. These cleared avoid taking spurious exceptions when leaving boot code.
2.6.1
GENERAL PURPOSE REGISTERS
register file powers unknown state with exception which always Initializing rest register file required proper operation hardware. Depending software environment however, several registers need initialized. Some these are: Stack Pointer Global Pointer Frame Pointer
TABLE 2-6:
Register Cause Config
INITIALIZATION
Action (Watch Pending), SW0/1 (Software Interrupts) should cleared. Typically, fields should desired Cache Coherency Algorithm (CCA) value prior accessing corresponding memory regions. core, values treated identically, hardware reset value these fields need modified. Should known value Timer Interrupts used. Should known value Timer Interrupts used. write compare will also clear pending Timer Interrupts (thus, Count should before Compare avoid unexpected interrupts). Desired state device should set. Other registers should written before they read. Some registers explicitly writable, only updated by-product instruction execution taken exception. Uninitialized bits should masked after reading these registers.
Count(1) Compare(1)
Status Other state
Note When Count register equal Compare register, timer interrupt signaled. There mask interrupt controller disable passing this interrupt desired.
Configuration
module EJTAG pins that configured user-available pins. EJTAG used debug, important make sure that software does clear DDPCON<JTAGEN>.
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NOTES:
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INSTRUCTION
Note: PIC32MX3XX/4XX family instruction complies with MIPS32 Release instruction architecture. PIC32MX does support following features: CoreExtend instructions Coprocessor instructions Coprocessor instructions Table provides summary instructions that implemented PIC32MX3XX/4XX family core. Refer "MIPS32® Architecture Programmers Volume MIPS32® Instruction Set" www.mips.com more information.
TABLE 3-1:
Instruction ADDI ADDIU ADDIUPC ADDU ANDI BEQL
PIC32MX3XX/4XX INSTRUCTION
Description Integer Integer Immediate Unsigned Integer Immediate Unsigned Integer Immediate (MIPS16eonly) Unsigned Integer Logical Logical Immediate Unconditional Branch (Assembler idiom for: offset) Branch Link (Assembler idiom for: BGEZAL offset) Branch Equal Branch Equal Likely Function Immed Immed Immed (016 Immed) (int)offset GPR[31> (int)offset (int)offset (int)offset else Ignore Next Instruction !Rs[31> (int)offset GPR[31> !Rs[31> (int)offset GPR[31> !Rs[31> (int)offset else Ignore Next Instruction !Rs[31> (int)offset else Ignore Next Instruction !Rs[31> (int)offset !Rs[31> (int)offset else Ignore Next Instruction
BGEZ BGEZAL
Branch Greater Than Equal Zero Branch Greater Than Equal Zero Link
BGEZALL
Branch Greater Than Equal Zero Link Likely
BGEZL
Branch Greater Than Equal Zero Likely
BGTZ BGTZL
Branch Greater Than Zero Branch Greater Than Zero Likely
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TABLE 3-1:
Instruction BLEZ BLEZL
PIC32MX3XX/4XX INSTRUCTION (CONTINUED)
Description Branch Less Than Equal Zero Branch Less Than Equal Zero Likely Function Rs[31> (int)offset Rs[31> (int)offset else Ignore Next Instruction Rs[31> (int)offset GPR[31> Rs[31> (int)offset GPR[31> Rs[31> (int)offset else Ignore Next Instruction Rs[31> (int)offset else Ignore Next Instruction (int)offset (int)offset else Ignore Next Instruction Break Exception NumLeadingOnes(Rs) NumLeadingZeroes(Rs) Software User's Manual DEPC Exit Debug Mode Status; StatusIE (int)Rs (int)Rt (int)Rs (int)Rt (uns)Rs (uns)Rt (uns)Rs (uns)Rt Stop instruction execution until execution hazards cleared Status; StatusIE SR[2> ErrorEPC else SR[1> SR[2> ExtractField(Rs, pos, size)
BLTZ BLTZAL
Branch Less Than Zero Branch Less Than Zero Link
BLTZALL
Branch Less Than Zero Link Likely
BLTZL
Branch Less Than Zero Likely
BNEL
Branch Equal Branch Equal Likely
BREAK COP0 DERET DIVU
Breakpoint Count Leading Ones Count Leading Zeroes Coprocessor Operation Return from Debug Exception Atomically Disable Interrupts Divide Unsigned Divide Execution Hazard Barrier
ERET
Atomically Enable Interrupts Return from Exception
Extract Field
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TABLE 3-1:
Instruction JALR JALR.HB JALRC JR.HB Insert Field Unconditional Jump Jump Link Jump Link Register Jump Link Register with Hazard Barrier Jump Link Register Compact execute instruction jump delay slot (MIPS16eonly) Jump Register Jump Register with Hazard Barrier
PIC32MX3XX/4XX INSTRUCTION (CONTINUED)
Description Function InsertField(Rs, pos, size) PC[31:28> offset<<2 GPR[31> PC[31:28> offset<<2 Like JALR, also clears execution instruction hazards Like also clears execution instruction hazards
Jump Register Compact execute instruction jump delay slot (MIPS16e only) Load Byte Unsigned Load Byte Load Halfword Unsigned Load Halfword Load Linked Word (byte)Mem[Rs+offset> (ubyte))Mem[Rs+offset> (half)Mem[Rs+offset> (uhalf)Mem[Rs+offset> Mem[Rs+offset> LLAdr offset immediate Mem[Rs+offset> Mem[PC+offset> Architecture Reference Manual Architecture Reference Manual (int)Rs (int)Rt (uns)Rs (uns)Rt CPR[0, sel> then then (int)Rs (int)Rt (uns)Rs (uns)Rt CPR[0, Sel> =Unpredictable ((int)Rs (int)Rt)31.0 (int)Rs (int)Rd (uns)Rs (uns)Rd
LWPC MADD MADDU MFC0 MFHI MFLO MOVN MOVZ MSUB MSUBU MTC0 MTHI MTLO MULT MULTU
Load Upper Immediate Load Word Load Word, relative Load Word Left Load Word Right Multiply-Add Multiply-Add Unsigned Move From Coprocessor Move From Move From Move Conditional Zero Move Conditional Zero Multiply-Subtract Multiply-Subtract Unsigned Move Coprocessor Move Move Multiply with register write Integer Multiply Unsigned Multiply
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TABLE 3-1:
Instruction RDHWR RDPGPR RESTORE ROTR ROTRV SAVE
PIC32MX3XX/4XX INSTRUCTION (CONTINUED)
Description Operation (Assembler idiom for: Logical Logical Logical Immediate Read Hardware Register Read from Previous Shadow Restore registers deallocate stack frame (MIPS16eonly) Rotate Word Right Rotate Word Right Variable Store Byte Store Conditional Word ~(Rs Immed Allows unprivileged access registers enabled HWREna register SGPR[SRSCtlPSS, Architecture Reference Manual Rtsa-1.0 Rt31.sa Function
RtRs-1.0 Rt31.Rs Save registers allocate stack frame (MIPS16e only) Architecture Reference Manual (byte)Mem[Rs+offset> mem[Rs+offset> Trap Debug Handler (byte)Rs (half)Rs (half)Mem[Rs+offset> Rs[4:0> (int)Rs (int)Rt else (int)Rs (int)Immed else (uns)Rs (uns)Immed else (uns)Rs (uns)Immed else (int)Rt (int)Rt Rs[4:0> (uns)Rt (uns)Rt Rs[4:0> (int)Rs (int)Rd (uns)Rs (uns)Rd Mem[Rs+offset> Architecture Reference Manual
SDBBP SLLV
Software Debug Break Point Sign-Extend Byte Sign-Extend Half Store Half Shift Left Logical Shift Left Logical Variable Less Than
SLTI
Less Than Immediate
SLTIU
Less Than Immediate Unsigned
SLTU
Less Than Unsigned
SRAV SRLV SSNOP SUBU
Shift Right Arithmetic Shift Right Arithmetic Variable Shift Right Logical Shift Right Logical Variable Superscalar Inhibit Operation Integer Subtract Unsigned Subtract Store Word Store Word Left
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TABLE 3-1:
Instruction SYNC SYSCALL TEQI TGEI TGEIU TGEU TLTI TLTIU TLTU TNEI WAIT WRPGPR WSBH XORI Store Word Right Synchronize System Call Trap Equal Trap Equal Immediate Trap Greater Than Equal Trap Greater Than Equal Immediate Trap Greater Than Equal Immediate Unsigned Trap Greater Than Equal Unsigned Trap Less Than Trap Less Than Immediate Trap Less Than Immediate Unsigned Trap Less Than Unsigned Trap Equal Trap Equal Immediate Wait Interrupts Write Previous Shadow Word Swap Bytes Within Halfwords Exclusive Exclusive Immediate Zero-extend byte (MIPS16eonly) Zero-extend half (MIPS16e only)
PIC32MX3XX/4XX INSTRUCTION (CONTINUED)
Description Function Architecture Reference Manual Software User's Manual SystemCallException TrapException (int)Immed TrapException (int)Rs (int)Rt TrapException (int)Rs (int)Immed TrapException (uns)Rs (uns)Immed TrapException (uns)Rs (uns)Rt TrapException (int)Rs (int)Rt TrapException (int)Rs (int)Immed TrapException (uns)Rs (uns)Immed TrapException (uns)Rs (uns)Rt TrapException TrapException (int)Immed TrapException Stall until interrupt occurs SGPR[SRSCtlPSS, Rt23.16 Rt31.24 Rt7.0 Rt15.8 (uns)Immed (ubyte) (uhalf)
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NOTES:
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Note:
OSCILLATORS
This data sheet summarizes features PIC32MX3XX/4XX family devices. intended comprehensive reference source. Refer "PIC32MX Family Reference Manual" (DS61132) detailed description this peripheral.
This section describes PIC32MX3XX/4XX oscillator system operation. PIC32MX oscillator system following modules features: total four external internal oscillator options clock sources On-chip with user-selectable input divider, multiplier, output divider boost operating frequency select internal external oscillator sources On-chip user-selectable divisor postscaler select oscillator sources Software-controllable switching between various clock sources Fail-Safe Clock Monitor (FSCM) that detects clock failure permits safe application recovery shutdown simplified diagram oscillator system shown Figure 4-1.
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Figure 4-1:
PIC32MX3XX/4XX FAMILY CLOCK DIAGRAM
Primary Oscillator (POSC) OSCI UFIN UFRCEN UPLLEN PBCLK available OSCO certain clock modes Oscillator typical TUN<5:0> Input Divider FPLLIDIV<2:0> COSC<2:0> Postscaler Peripherals PBCLK Clock MHz)
UFIN PLLDIV<2:0>
OSCO
XTPLL, HSPLL, ECPLL, FRCPLL
Output Divider PLLODIV<2:0>
PBDIV<2:0>
Multiplier PLLMULT<2:0> Select Peripherals
Postscaler
FRCDIV
FRCDIV<2:0> LPRC Oscillator LPRC typical
Secondary Oscillator (SOSC) 32.768 SOSCO SOSCEN FSOSCEN SOSCI Clock Control Logic Fail-Safe Clock Monitor FSCM FSCM Event SOSC
NOSC<2:0> COSC<2:0> OSWEN FSCMEN<1:0> WDT, PWRT Timer1, RTCC
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Control Registers
Oscillator module consists following Special Function Registers (SFRs): OSCCON: Control Register Oscillator module OSCCONCLR, OSCCONSET, OSCCONINV: Atomic Manipulation Write-only Registers OSCCON register OSCTUN: Tuning Register Oscillator module OSCTUNCLR, OSCTUNSET, OSCTUNINV: Atomic Manipulation Write-only Registers OSCTUN register Oscillator module also associated bits interrupt control: following Interrupt Flag Status bits (IFS1<14>) Clock Fail FSCMIF IFS1 Interrupt register Interrupt Enable Control bits (IEC1<14>) Clock Fail FSCMIE IEC1 Interrupt register Interrupt Priority Control bits (FSCMIP<12:10>) Clock Fail IPC8 Interrupt register Interrupt Subpriority Control bits (FSCMIP<9:8>) Clock Fail IPC8 Interrupt register following tables provide brief summaries Oscillator-module-related registers. Corresponding registers appear after summaries, followed detailed description each register.
TABLE 4-1:
Virtual Address BF80_F000
OSCILLATOR SUMMARY
Name OSCCON 31:24 23:16 15:8 31/23/15/7 CLKLOCK ULOCK 30/22/14/6 SOSCRDY COSC<2:0> LOCK SLPEN 29/21/13/5 28/20/12/ 27/19/11/ 26/18/10/2 25/17/9/1 FRCDIV<2:0> PLLMULT<2:0> NOSC<2:0> UFRCEN SOSCEN OSWEN 24/16/8/0
PLLODIV<2:0> PBDIV<1:0>
BF80_F004 BF80_F008 BF80_F00C BF80_F010
OSCCONCLR OSCCONSET OSCCONINV OSCTUN
31:0 31:0 31:0 31:24 23:16 15:8
Write clears selected bits OSCCON, read yields undefined value Write sets selected bits OSCCON, read yields undefined value Write inverts selected bits OSCCON, read yields undefined value TUN<5:0>
BF80_F014 BF80_F018 BF80_F01C
OSCTUNCLR OSCTUNSET OSCTUNINV
31:0 31:0 31:0
Write clears selected bits OSCTUN, read yields undefined value Write sets selected bits OSCTUN, read yields undefined value Write inverts selected bits OSCTUN, read yields undefined value
TABLE 4-2:
Virtual Address BF80_0000
WATCHDOG TIMER SUMMARY(1)
Name 31/23/15/7 15:8 30/22/14/6 29/21/13/5 28/20/12/ 27/19/11/ 26/18/10/2 25/17/9/1 24/16/8/0
WDTCON
Note
This summary table contains partial register definitions that only pertain Oscillator peripheral. Refer "PIC32MX Family Reference Manual" (DS61132) detailed description these registers.
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TABLE 4-3:
Virtual Address BF88_1070 BF88_1040 BF88_1110
OSCILLATOR INTERRUPT REGISTER SUMMARY(1)
Name IEC1 IFS1 IPC8 15:8 15:8 23:16 31/23/15/7 RTCCIE RTCCIF 30/22/14/6 FSCMIE FSCMIF 29/21/13/5 I2C2MIE I2C2MIF 28/20/12/4 I2C2SIE I2C2SIF 27/19/11/3 I2C2BIE I2C2BIF FSCMIP<2:0> 26/18/10/2 U2TXIE U2TXIF 25/17/9/1 U2RXIE U2RXIF 24/16/8/0 U2EIE U2EIF
FSCMIS<1:0>
Note
This summary table contains partial register definitions that only pertain Oscillator peripheral. Refer "PIC32MX Family Reference Manual" (DS61132) detailed description these registers.
TABLE 4-4:
Virtual Address BFC0_2FF8
DEVCFG: DEVICE CONFIGURATION REGISTER SUMMARY(1,
Name DEVCFG1 23:16 15:8 31/23/15/7 FWDTEN 30/22/14/6 29/21/13/5 FPBDIV<1:0> FSOSCEN FPLLMULT<2:0> 28/20/12/4 27/19/11/3 26/18/10/2 FWDTPS<4:0> OSCIOFNC POSCMD<1:0> FNOSC<2:0> FPLLODIV<2:0> FUPLLIDIV<2:0> FPLLIDIV<2:0> 25/17/9/1 24/16/8/0
FCKSM<1:0> IESO FUPLLEN
BFC0_2FF4
DEVCFG2 23:16 15:8
Note
FUPLLEN FPLLODIV<2:0> only available PIC32MX4XX family variants. This summary table contains partial register definitions that only pertain Oscillator peripheral. Refer "PIC32MX Family Reference Manual" (DS61132) detailed description these registers.
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REGISTER 4-1:
R/W-0 CLKLOCK Legend: Readable Unimplemented 31-30 29-27 Writable Programmable Reserved Value POR: (`0', `1', Unknown) ULOCK LOCK R/W-0 SLPEN R/W-0 R/W-0 UFRCEN R/W-x SOSCEN COSC<2:0> R/W-x R/W-x NOSC<2:0> R/W-x OSWEN SOSCRDY R/W-x R/W-x R/W-x R/W-x PLLMULT<2:0> R/W-x
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-x R/W-x PLLODIV<2:0> R/W-x R/W-0 R/W-0 FRCDIV<2:0> R/W-x R/W-1
PBDIV<1:0>
Reserved: Write `0'; ignore read PLLODIV<2:0>: Output Divider output divided output divided output divided output divided output divided output divided output divided output divided Note: Reset these bits value FPLLODIV configuration bits (DEVCFG2<18:16>) FRCDIV<2:0>: Fast Internal Clock Divider bits divided divided divided divided divided divided divided (default setting) divided Reserved: Write `0'; ignore read SOSCRDY: Secondary Oscillator Ready Indicator Indicates that Secondary Oscillator running stable Secondary oscillator either turned still warming Reserved: Write `0'; ignore read
26-24
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REGISTER 4-1:
20-19
OSCCON: OSCILLATOR CONTROL REGISTER
PBDIV<1:0>: Peripheral Clock Divisor PBCLK SYSCLK divided (default) PBCLK SYSCLK divided PBCLK SYSCLK divided PBCLK SYSCLK divided Note: Reset these bits value FPBDIV Configuration bits (DEVCFG1<13:12>). PLLMULT<2:0>: Multiplier bits Clock multiplied Clock multiplied Clock multiplied Clock multiplied Clock multiplied Clock multiplied Clock multiplied Clock multiplied Note: Reset these bits value FPLLMULT Configuration bits (DEVCFG2<6:4>). Reserved: Write `0'; ignore read COSC<2:0>: Current Oscillator Selection bits Fast Internal Oscillator divided OSCCON<FRCDIV> bits Fast Internal Oscillator divided Low-Power Internal Oscillator (LPRC) Secondary Oscillator (SOSC) Primary Oscillator with module (XTPLL, HSPLL ECPLL) Primary Oscillator (XT, Fast Oscillator with module divided (FRCPLL) Fast Oscillator (FRC) Note: Reset these bits value FNOSC Configuration bits (DEVCFG1<2:0>). Reserved: Write `0'; ignore read NOSC<2:0>: Oscillator Selection bits Fast Internal Oscillator divided OSCCON<FRCDIV> bits Fast Internal Oscillator divided Low-Power Internal Oscillator (LPRC) Secondary Oscillator (SOSC) Primary Oscillator with module (XTPLL, HSPLL ECPLL) Primary Oscillator (XT, Fast Internal Oscillator with module Postscaler (FRCPLL) Fast Internal Oscillator (FRC) Note: Reset these bits value FNOSC Configuration bits (DEVCFG1<2:0>). CLKLOCK: Clock Selection Lock Enable FSCM enabled (FCKSM1 Clock selections locked. Clock selections locked modified FSCM disabled (FCKSM1 Note: Clock selections never locked modified. ULOCK: Lock Status Indicates that module lock module start-up timer satisfied Indicates that module lock module start-up timer progress disabled LOCK: Lock Status module lock module start-up timer satisfied module lock, start-up timer running disabled
18-16
14-12
10-8
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REGISTER 4-1:
OSCCON: OSCILLATOR CONTROL REGISTER
SLPEN: Sleep Mode Enable Device will enter Sleep mode when WAIT instruction executed Device will enter Idle mode when WAIT instruction executed Clock Fail Detect FSCM (Fail Safe Clock Monitor) detected clock failure clock failure been detected UFRCEN: Clock Enable Enable clock source clock source primary oscillator clock source SOSCEN: 32.768 Secondary Oscillator (SOSC) Enable Enable Secondary Oscillator Disable Secondary Oscillator Note: Reset these bits value FSOSCEN Configuration (DEVCFG1<5>). OSWEN: Oscillator Switch Enable Initiate oscillator switch selection specified NOSC2:NOSC0 bits Oscillator switch complete
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REGISTER 4-2:
Legend: Readable Unimplemented 31:6 Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCTUN: TUNING REGISTER
R/W-0
TUN<5:0>
Reserved: Write `0'; ignore read TUN<5:0>: Oscillator Tuning bits 011111 Maximum frequency. 011110 000001 000000 Center frequency. Oscillator runs calibrated frequency. 111111 100001 100000 Minimum frequency.
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REGISTER 4-3:
R/W-0 Legend: Readable Unimplemented Writable Programmable Reserved Value POR: (`0', `1', Unknown) WDTPS<4:0>
WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0 WDTCLR
Watchdog Timer Enable Enables enabled device configuration Disable enabled software Notes: read this will result enabled device configuration software. LPRC oscillator will automatically enabled when this set.
Note: Shaded names this register control other PIC32MX3XX/4XX peripherals related oscillator.
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REGISTER 4-4:
R/W-0 RTCCIE R/W-0 SPI2RXIE Legend: Readable Unimplemented Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-0 SPI2TXIE R/W-0 SPI2EIE R/W-0 CMP2IE R/W-0 CMP1IE R/W-0 PMPIE R/W-0 AD1IE R/W-0 FSCMIE R/W-0 I2C2MIE R/W-0 I2C2SIE R/W-0 I2C2BIE R/W-0 U2TXIE R/W-0 U2RXIE R/W-0 DMA3IE R/W-0 DMA2IE R/W-0 DMA1IE
IEC1: INTERRUPT ENABLE CONTROL REGISTER
R/W-0 USBIE R/W-0 FCEIE R/W-0 DMA0IE R/W-0 U2EIE R/W-0 CNIE
FSCMIE: Fail-Safe Clock Monitor Interrupt Enable Interrupt enabled Interrupt disabled
Note: Shaded names this Interrupt register control other PIC32MX3XX/4XX peripherals related oscillator.
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REGISTER 4-5:
R/W-0 RTCCIF R/W-0 SPI2RXIF Legend: Readable Unimplemented Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-0 SPI2TXIF R/W-0 SPI2EIF R/W-0 CMP2IF R/W-0 CMP1IF R/W-0 PMPIF R/W-0 AD1IF R/W-0 FSCMIF R/W-0 I2C2MIF R/W-0 I2C2SIF R/W-0 I2C2BIF R/W-0 U2TXIF R/W-0 U2RXIF R/W-0 DMA3IF R/W-0 DMA2IF R/W-0 DMA1IF
IFS1: INTERRUPT FLAG STATUS REGISTER
R/W-0 USBIF R/W-0 FCEIF R/W-0 DMA0IF R/W-0 U2EIF R/W-0 CNIF
FSCMIF: Fail-Safe Clock Monitor Interrupt Flag Interrupt request occured interrupt request occurred
Note: Shaded names this Interrupt register control other PIC32MX3XX/4XX peripherals related oscillator.
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PIC32MX3XX/4XX
REGISTER 4-6:
Legend: Readable Unimplemented 12-10 Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/W-0 R/W-0 I2C2IP<2:0> R/W-0 R/W-0 R/W-0 R/W-0 FSCMIP<2:0> R/W-0 R/W-0 R/W-0 R/W-0 RTCCIP<2:0> R/W-0 R/W-0
IPC8: INTERRUPT PRIORITY CONTROL REGISTER
R/W-0 R/W-0 DMA0IP<2:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMA0IS<1:0>
RTCCIS<1:0>
FSCMIS<1:0>
I2C2IS<1:0>
FSCMIP<2:0>: Fail-Safe Clock Monitor Interrupt Priority bits Interrupt priority Interrupt priority Interrupt priority Interrupt priority Interrupt priority Interrupt priority Interrupt priority Interrupt disabled FSCMIS<1:0>: Fail-Safe Clock Monitor Interrupt Subpriority bits Interrupt subpriority Interrupt subpriority Interrupt subpriority Interrupt subpriority
Note: Shaded names this Interrupt register control other PIC32MX3XX/4XX peripherals related oscillator.
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2008 Microchip Technology Inc.
PIC32MX3XX/4XX
REGISTER 4-7:
R/P-1 FWDTEN R/P-1 R/P-1 IESO Legend: Readable Unimplemented 15-14 Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/P-1 FSOSCEN R/P-1 FNOSC2 R/P-1 FNOSC1 R/P-1 R/P-1 R/P-1 R/P-1 OSCIOFNC R/P-1 R/P-1 R/P-1 FWDTPS4 R/P-1 FWDTPS3 R/P-1 FWDTPS2 R/P-1 FWDTPS1
DEVCFG1 BOOT CONFIGURATION REGISTER
R/P-1 FWDTPS0 R/P-1 R/P-1 FNOSC0
FCKSM<1:0>
FPBDIV<1:0>
POSCMD<1:0>
FCKSM<1:0>: Fail-safe Clock Monitor (FSCM) Clock Switch Configuration bits FSCM Clock Switching disabled Clock Switching enabled, FSCM disabled Clock Switching FSCM enabled FPBDIV<1:0>: Peripheral Clock divisor default value PBCLK SYSCLK divided PBCLK SYSCLK divided PBCLK SYSCLK divided PBCLK SYSCLK divided OSCIOFNC: CLKO Enable Configuration CLKO output signal active OSCO pin; primary oscillator must disabled configured External Clock mode (EC) CLKO active (POSCMD<1:0> CLKO output disabled POSCMD<1:0>: Primary Oscillator Configuration bits Primary Oscillator Disabled mode Mode Mode IESO: Internal External Clock Switchover Select Internal External Clock Switchover mode enabled; Two-Speed Start-up mode Internal External Clock Switchover mode disabled; Single-Speed Start-up mode FSOSCEN: Secondary Oscillator Enable Enable secondary oscillator Disable secondary oscillator
13-12
2008 Microchip Technology Inc.
DS61143E-page
PIC32MX3XX/4XX
REGISTER 4-7:
DEVCFG1 BOOT CONFIGURATION REGISTER
FNOSC<2:0>: Clock Oscillator Select bits Fast Oscillator with divide-by-N (FRCDIV) Divided (FRCDIV16) Low-Power Oscillator (LPRC) Secondary Oscillator (SOSC) Primary Oscillator with (XTPLL, HSPLL, ECPLL) Primary Oscillator without (XT, Fast Oscillator with Fast Oscillator (FRC)
DS61143E-page
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
REGISTER 4-8:
R/P-1 FUPLLEN Legend: Readable Unimplemented 18-16 Writable Programmable Reserved Value POR: (`0', `1', Unknown) R/P-1 R/P-1 FPLLMULT<2:0> R/P-1 R/P-1 R/P-1 FPLLIDIV<2:0> R/P-1 R/P-1 FUPLLIDIV<2:0> R/P-1 R/P-1 R/P-1 FPLLODIV<2:0> R/P-1
DEVCFG2 BOOT CONFIGURATION REGISTER
R/P-1
FPLLODIV<2:0>: Default postscaler PLL. output divided output divided output divided output divided output divided output divided output divided output divided (default setting) FUPLLEN: Enable Enable Disable bypass FUPLLIDIV<2:0>: Input Divider bits divider divider divider divider divider divider divider divider FPLLMULT<2:0>: Default Multiplier Value bits multiplier multiplier multiplier multiplier multiplier multiplier multiplier multiplier
10-8
2008 Microchip Technology Inc.
DS61143E-page
PIC32MX3XX/4XX
REGISTER 4-8:
DEVCFG2 BOOT CONFIGURATION REGISTER
FPLLIDIV<2:0>: Default Input Divider Value bits Divide Divide Divide Divide Divide Divide Divide Divide
DS61143E-page
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
Operation: Clock Generation Clock Sources
PIC32MX3XX/4XX device internal clocks: clock clock. They derived from currently selected clock source. clock source chosen from available internal external clock sources. Some these clock sources have Phase Locked Loops (PLLs), programmable output dividers, input dividers scale input frequency suit application. clock source changed on-the-fly software. oscillator control register locked hardware, must unlocked series writes before software perform clock switch. There three main clocks PIC32MX3XX/4XX device: System Clock (SYSCLK) used some peripherals Peripheral Clock (PBCLK) used most peripherals Clock (USBCLK) used peripheral PIC32MX3XX/4XX clocks derived from following sources: Primary Oscillator (POSC) OSCI OSCO pins Secondary Oscillator (SOSC) SOSCI SOSCO pins Internal Fast Oscillator (FRC) Internal Low-Power Oscillator (LPRC) Each clock sources unique configurable options, such PLL, input divider and/or output divider, that detailed their respective sections. There four internal clocks, depending specific device. clocks derived from currently selected oscillator source. Note: Clock sources peripherals that external clocks, such RTCC Timer covered their respective sections.
2008 Microchip Technology Inc.
DS61143E-page
PIC32MX3XX/4XX
4.2.1 SYSTEM CLOCK (SYSCLK) GENERATION
SYSCLK primary clock used select peripherals such DMA, Interrupt Controller, Prefetch Cache. SYSCLK derived from four clock sources: POSC, SOSC, FRC, LPRC. Some clock sources have specific clock multipliers and/or divider options. clock scaling applied other than user specified values. SYSCLK source selected device configuration changed software during operation. ability switch clock sources during operation allows application reduce power consumption reducing clock speed. Refer Table list SYSCLK sources.
TABLE 4-5:
CLOCK SELECTION CONFIGURATION VALUES
Oscillator Mode Oscillator Source Internal Internal Internal Secondary Primary Primary Primary Primary Primary Primary Internal Internal POSCMD<1:0> FNOSC2: FNOSC0 Notes
Fast Oscillator with Postscaler (FRCDIV) Fast Oscillator divided (FRCDIV16) Low-Power Oscillator (LPRC) Secondary (Timer1/RTCC) Oscillator (SOSC) Primary Oscillator (HS) with Module (HSPLL) Primary Oscillator (XT) with Module (XTPLL) Primary Oscillator (EC) with Module (ECPLL) Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast Oscillator with Module (FRCPLL) Fast Oscillator (FRC) Note
OSCO function PBCLK Digital determined OSCIOFNC Configuration bit. When required Oscillator mode configured these noted options. Default Oscillator mode unprogrammed (erased) device. When using modes input divider must chosen such that resulting frequency applied range MHz. this mode, input divider forced provide input PLL. This parameter cannot modified satisfies requirements described Note
DS61143E-page
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
4.2.1.1 Primary Oscillator (POSC)
POSC operating modes, summarized Table 4-6. first three modes each combined with module form last three modes. Figure 4-2, Figure 4-3, Figure show various POSC configurations. primary oscillator connected OSCI OSCO pins device family. primary oscillator configured external clock input, external crystal resonator. XTPLL, HSPLL modes External Crystal Resonator Controller Oscillator modes. modes functionally very similar. primary difference gain internal inverter oscillator circuit (see Figure 4-2). mode medium-power, medium-frequency mode medium inverter gain. mode higher power provides highest oscillator frequencies highest inverter gain. OSCO provides crystal/resonator feedback both Oscillator modes hence available input output these modes. XTPLL HSPLL modes have Phase Locked Loop (PLL) with user selectable input divider, multiplier, output divider provide wide range output frequencies. oscillator circuit will consume more current when enabled. External Clock modes, ECPLL, allow system clock derived from external clock source. These modes configure OSCI high-impedance input that driven CMOS driver. external clock used drive system clock directly (EC) ECPLL module with prescale postscaler used change input clock frequency (ECPLL). External Clock modes also disable internal feedback buffer, allowing OSCO used other functions. External Clock mode, OSCO used additional device (see Figure 4-4) PBCLK output (see Figure 4-3). Note: When using modes, input divider must chosen such that resulting frequency applied range MHz.
TABLE 4-6:
HSPLL XTPLL ECPLL
PRIMARY OSCILLATOR OPERATING MODES
Description MHz-40 crystal MHz-10 resonator External clock input (0-80 MHz) MHz-40 crystal, enabled MHz-10 resonator, enabled External clock input (5-80 MHz), enabled
Oscillator Mode
Note: clock applied after applicable prescalers, postscalers, multipliers must exceed maximum allowable processor frequency.
FIGURE 4-2:
CRYSTAL CERAMIC RESONATOR OPERATION (XT, XTPLL, HSPLL OSCILLATOR MODE)
OSCI C1(3) XTAL OSCO RS(1) C2(3) RF(2)
Internal Logic
Enable
PIC32MX3XX/4XX
Note
series resistor, required strip crystals. internal feedback resistor, typically range Refer "PIC32MX Family Reference Manual" (DS61132) help determining best oscillator components.
2008 Microchip Technology Inc.
DS61143E-page
PIC32MX3XX/4XX
FIGURE 4-3: EXTERNAL CLOCK INPUT OPERATION WITH CLOCK-OUT (EC, ECPLL MODE) 4.2.1.3 Oscillator Start-up Timer
order ensure that crystal oscillator ceramic resonator) started stabilized, Oscillator Start-up Timer (OST) provided. simple 10-bit counter that counts 1024 TOSC cycles before releasing oscillator clock rest system. This time-out period designated TOST. amplitude oscillator signal must reach thresholds oscillator pins before begin count cycles. TOST interval required every time oscillator restart (i.e., POR, wake-up from Sleep mode). Oscillator Start-up Timer applied modes primary oscillator, well secondary oscillator, Section 4.2.1.5 "Secondary Oscillator (SOSC)".
Clock from Ext. System PBCLK
OSCI PIC32MX3XX/4XX OSCO (Clock Out)
FIGURE 4-4:
EXTERNAL CLOCK INPUT OPERATION WITH CLOCK-OUT ECPLL MODE)
Clock from Ext. System
OSCI PIC32MX3XX/4XX (OSCO)
4.2.1.2
Primary Oscillator (POSC) Configuration
configure POSC, following steps should performed: Select POSC default oscillator device Configuration register, DEVCFG1, setting FNOSC<2:0> 010, without PLL; FNOSC<2:0> 011, with PLL. Select desired mode (HS, EC), using POSCMD<1:0> DEVCFG1 register. used: Select appropriate Configuration bits input divider scale input frequency between using FPLLIDIV<2:0> DEVCFG2 register. Select desired multiplier ratio using FPLLMULT<2:0> DEVCFG2 register. runtime, select desired output divider using OSCCON<29:27> PLLODIV register provide desired clock frequency. default value DEVCFG1 register.
DS61143E-page
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
4.2.1.4 System Clock Phase Locked Loop (PLL)
system clock provides user configurable input divider, multiplier, output divider which used with Primary Oscillator modes with Internal Fast Oscillator (FRC) mode create variety clock frequencies from single clock source. Input divider, multiplier, output divider control initial value bits contained DEVCFG2 device Configuration register. multiplier output divider bits also contained OSCCON register. part device Reset, values from device configuration register, DEVCFG2, copied OSCCON register. This allows user preset input divider provide appropriate input frequency initial multiplier when programming device. runtime multiplier, divider output divider changed software scale clock frequency suit application. input divider cannot changed time. This prevent applying input frequency outside specified limits PLL. configure following steps required: Calculate input divider, multiplier, output divider values. input divider initial multiplier value DEVCFG2 register when programming part. runtime multiplier output divider changed suit application.
Combinations input divider, multiplier output divider provide combined multiplier approximately 0.006 times input frequency. reliable operation output module must exceed maximum clock frequency device. input divider value should chosen limit input frequency range MHz. time required provide stable output, Status LOCK (OSCCON<5>) provided. When clock input changed, this driven (`0'). After achieved lock start-up timer expired, set. will upon expiration timer even achieved lock.
2008 Microchip Technology Inc.
DS61143E-page
PIC32MX3XX/4XX
TABLE 4-7: MULTIPLIER OUTPUT SELECTED OUTPUT DIVIDER VALUES
Multiplication factor PLLODIV PLLMULT <2:0> <2:0> PLLODIV PLLMULT Multiplier Postscaler Multiplication <2:0> <2:0> factor Multiplier Postscaler
10.5 3.75 4.25 4.75 5.25 1.875 2.125 2.250 2.375 2.625
`000' `000' `000' `000' `000' `000' `000' `000' `001' `001' `001' `001' `001' `001' `001' `001' `010' `010' `010' `010' `010' `010' `010' `010' `011' `011' `011' `011' `011' `011' `011' `011'
`000' `001' `010' `011' `100' `101' `110' `111' `000' `001' `010' `011' `100' `101' `110' `111' `000' `001' `010' `011' `100' `101' `110' `111' `000' `001' `010' `011' `100' `101' `110' `111'
.938 1.063 1.125 1.188 1.250 1.313 .4688 .5313 .5625 .5938 .6250 .6563 .7500 .234 .250 .266 .281 .297 .313 .328 .375 .05859 .06250 .06641 .07031 .07422 .07813 .08203 .09375
`100' `100' `100' `100' `100' `100' `100' `100' `101' `101' `101' `101' `101' `101' `101' `101' `110' `110' `110' `110' `110' `110' `110' `110' `111' `111' `111' `111' `111' `111' `111' `111'
`000' `001' `010' `011' `100' `101' `110' `111' `000' `001' `010' `011' `100' `101' `110' `111' `000' `001' `010' `011' `100' `101' `110' `111' `000' `001' `010' `011' `100' `101' `110' `111'
DS61143E-page
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
4.2.1.4.1 Lock Status
4.2.1.5
Secondary Oscillator (SOSC)
LOCK (OSCCON<5>) read-only Status that indicates lock status PLL. automatically after typical time delay achieve lock, also designated TLOCK. does stabilize properly during start-up, LOCK reflect actual status lock, does detect when loses lock during normal operation. LOCK cleared Power-on Reset clock switches when selected destination clock source. remains clear when clock source using selected. Refer Electrical Characteristics section specific device data sheet further information lock interval. 4.2.1.4.2 Lock Status
Secondary Oscillator (SOSC) designed specifically low-power operation with external 32.768 crystal. oscillator located SOSCO SOSCI device pins serves secondary crystal clock source low-power operation. also drive Timer1 and/or Real-Time Clock/Calendar module Real-Time Clock applications. 4.2.1.5.1 Enabling SOSC Oscillator
SOSC hardware enabled FSOSCEN Configuration (DEVCFG1<5>). Once SOSC enabled, software control modifying SOSCEN (OSCCON<1>). Setting SOSCEN enables oscillator; SOSCO SOSCI pins controlled oscillator cannot used port other functions. Note: unlock sequence required before write OSCCON occur. Refer Section 4.2.6.2 "Oscillator Switching Sequence" more information.
ULOCK (OSCCON<6>) read-only status that indicates lock status PLL. automatically after typical time delay achieve lock, also designated TLOCK. does stabilize properly during start-up, LOCK reflect actual status lock, does detect when loses lock during normal operation. ULOCK cleared Power-on Reset. remains clear when clock source using selected. Refer Electrical Characteristics section specific device data sheet further information lock interval. 4.2.1.4.3 Primary Oscillator Start-up from Sleep Mode
Secondary Oscillator requires warm-up period before used clock source. When oscillator enabled, warm-up counter increments 1024. When counter expires SOSCRDY (OSCCON<22>) `1'. 4.2.1.5.2 SOSC Continuous Operation
SOSC always enabled when SOSCEN (OSCCON<1>) set. Leaving oscillator running times allows fast switch system clock lower power operation. Returning faster main oscillator will still require oscillator start-up time crystal type source and/or uses PLL. addition, oscillator will need remain running times Real-Time Clock applications required Timer1.
ensure reliable wake-up from Sleep, care must taken properly design primary oscillator circuit. This because load capacitors have both partially charged some quiescent value phase differential wake-up minimal. Thus, more time required achieve stable oscillation. Remember also that lowvoltage, high temperatures lower frequency clock modes also impose limitations loop gain, which turn, affects start-up. Each following factors increases start-up time: Low-frequency design (with Gain Clock mode) Quiet environment (such battery operated device) Operating shielded (away from noisy area) voltage High temperature Wake-up from Sleep mode
2008 Microchip Technology Inc.
DS61143E-page
PIC32MX3XX/4XX
EXAMPLE 4-1: ENABLING SOSC
ensure OSCCON Write Key1 Write Key2 OSCCON locked SYSKEY SYSKEY unlocked SYSKEY 0x12345678; SYSKEY 0xAA996655; SYSKEY 0x556699AA;
OSCCONSET
make desired change request clock switch Relock SYSKEY Write value other than Key1 Key2 OSCCON relocked
SYSKEY 0x12345678;
4.2.1.6
Internal Fast Oscillator (FRC)
4.2.1.6.3
Oscillator Tune Register (OSCTUN)
oscillator fast nominal), user trimmable, internal oscillator with user selectable input divider, multiplier, output divider. 4.2.1.6.1 Postscaler Mode (FRCDIV)
Oscillator Tuning register OSCTUN allows user fine tune oscillator over range approximately ±12% (typical). Each increment decrement changes factory calibrated frequency oscillator fixed amount.
Users limited nominal output they wish fast internal oscillator clock source. additional mode, FRCDIV, implements selectable output divider that allows choice lower clock frequency from different options, plus direct output. output divider configured using FRCDIV<2:0> bits (OSCCON<26:24>). Assuming nominal output, available lower frequency options range from (divide-by-2) (divide-by-256). range frequencies allows users ability save power time application simply changing FRCDIV bits. FRCDIV mode selected whenever COSC bits (OSCCON<14:12>) `111'. 4.2.1.6.2 Oscillator with Mode (FRCPLL)
4.2.1.7
Internal Low-Power Oscillator (LPRC)
LPRC oscillator separate from FRC. oscillates nominal frequency 31.25 kHz. LPRC oscillator clock source Power-up Timer (PWRT), Watchdog Timer (WDT), Fail Safe Clock Monitor (FSCM) reference circuits. also used provide low-frequency clock source option device those applications where power consumption critical, timing accuracy required.
output also combined with user selectable multiplier output divider produce SYSCLK across wide range frequencies. mode selected whenever COSC bits (OSCCON<14:12>) `001'. Note: this mode, input divider forced provide input PLL. This parameter cannot modified.
desired multiplier output divider values chosen provide desired device frequency
DS61143E-page
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
4.2.1.7.1 Enabling LPRC Oscillator
4.2.3
Since serves PWRT clock source, LPRC oscillator disabled Power-on Reset whenever on-board voltage regulator enabled. After PWRT expires, LPRC oscillator will remain following true: Fail-Safe Clock Monitor enabled. enabled. LPRC oscillator selected system clock (COSC2:COSC0 100). none above true, LPRC will shut after PWRT expires.
Clock (USBCLK) Generation
USBCLK derived from internal oscillator, POSC, from POSC. normal operation, module requires exact clock. When using PLL, output internally divided obtain clock. clock source used detect activity bring module SUSPEND mode. Once module SUSPEND mode, starts using clock sources. internal oscillator used normal module operation. 4.2.3.0.1 Clock Phase Locked Loop (UPLL)
4.2.2
PERIPHERAL CLOCK (PBCLK) GENERATION
PBCLK derived from System Clock (SYSCLK) divided PBDIV<1:0> (OSCCON<20:19>). PBCLK Divisor bits PBDIV<1:0> allow postscalers 1:1, 1:2, 1:4, 1:8. Refer individual peripheral module section(s) information regarding which specific peripheral uses. Notes: When PBDIV divisor ratio `1:1' SYSCLK PBCLK equivalent frequency. PBCLK frequency never greater than processor clock frequency. effect changing PBCLK frequency individual peripherals should taken into account when selecting changing PBDIV value. Performing back-to-back operations PBCLK peripheral registers when divisor will cause stall number cycles. This stall occurs prevent operation from occurring before pervious completed. length stall determined ratio PBCLK synchronizing time between busses. Changing PBCLK frequency effect SYSCLK peripherals operation.
clock provides user configurable input divider which used with primary oscillator modes with Internal Fast Oscillator (FRC) mode create variety clock frequencies from clock source. actual source must able provide stable clock required specifications. UPLL enable Input divider bits contained DEVCFG2 device configuration register. input UPLL must limited only. Appropriate input divider must selected ensure that UPLL input MHz. configure UPLL following steps required: Enable setting FUPLLEN DEVCFG2 register. Based source clock, calculate UPLL input divider value such that input UPLL input divider FUPLLIDIV bits DEVCFG2 register when programming part. Lock Status
4.2.3.0.2
ULOCK (OSCCON<6>) read-only status that indicates lock status PLL. automatically after typical time delay achieve lock, also designated TULOCK. does stabilize properly during start-up, ULOCK reflect actual status lock, does detect when loses lock during normal operation. ULOCK cleared Power-on Reset. remains clear when clock source using selected. Refer Electrical Characteristics section specific device data sheet further information lock interval.
2008 Microchip Technology Inc.
DS61143E-page
PIC32MX3XX/4XX
4.2.3.0.3 Using Internal Oscillator with internal oscillator available clock source detect activity during SUSPEND mode bring module SUSPEND mode. enable usage, UFRCEN (OSCCON<2>) must before putting module SUSPEND mode. FSCM module takes following actions when switching oscillator: COSC bits (OSCCON<14:12>) loaded with `000'. OSCCON<3> indicate clock failure OSWEN control (OSCCON<0>) cleared cancel pending clock switches.
4.2.4
TWO-SPEED START-UP
Two-Speed Start-up mode used reduce device start-up latency when using External Crystal POSC modes, including PLL. Two-Speed Start-up uses clock SYSCLK source until Primary Oscillator (POSC) stabilized. After user selected oscillator stabilized, clock source will switch POSC. This allows begin running code, lower speed, while oscillator stabilizing. When POSC start-up criteria automatic clock switch occurs switch POSC. This mode enabled device Configuration bits FCKSM<1:0> (DEVCFG1<15:14>). Two-Speed Startup operates after Power-on Reset (POR) exit from SLEEP. Software determine oscillator source currently reading COSC<2:0> bits OSCCON register. Note: Watchdog Timer (WDT), enabled, will continue count same rate regardless SYSCLK frequency. Care must taken service during Two-Speed Start-up, taking into account change SYSCLK.
enable FSCM following steps should performed: Enable FSCM device Configuration register, DEVCFG1, configuring FCKSM<1:0> bits `00'. Clock Switching enabled, FSCM disabled Clock Switching FSCM enabled Select desired mode using FNOSC<2:0> DEVCFG1. Select POSC default oscillator device Configuration register, DEVCFG1 configuring FNOSC<2:0> without with PLL. Select appropriate Configuration bits input divider scale input frequency between using FPLLIDIV<2:0> (DEVCFG2<2:0>). When using FRCPLL mode, input divider forced provide input PLL. This parameter cannot modified. Select desired multiplier using FPLLMULT<2:0> (DEVCFG2<6:4>). Select desired output divider using FPLLODIV<2:0> (DEVCFG2<18:16>).
used:
Note:
4.2.5
FAIL-SAFE CLOCK MONITOR OPERATION
Fail-Safe Clock Monitor (FSCM) designed allow continued device operation current oscillator fails. intended with Primary Oscillator (POSC) automatically switches oscillator POSC failure detected. switch Fast Internal Oscillator (FRC) oscillator allows continued device operation ability retry POSC execute code appropriate clock failure. FSCM mode controlled FCKSM<1:0> bits device Configuration register, DEVCFG1. POSC modes used with FSCM. When clock failure detected with FSCM enabled FSCM Interrupt Enable FSCMIE (IEC1<14>) set, clock source will switched from POSC FRC. Oscillator Fail interrupt will generated, with (OSCCON<3>) set. This interrupt user-settable priority FSCMIP<2:0> (IPC8<12:10>) subpriority FSCMIS<1:0> (IPC8<9:8>). clock source will remain until device Reset clock switch performed. Failure enable FSCM interrupt will inhibit actual clock switch.
FSCM interrupt desired when FSCM event occurs, following steps should performed during start-up code: Clear FSCM interrupt (IFS1<14>). FSCMIF
Interrupt priority FSCMIP<2:0> (IPC8<12:10>) subpriority FSCMIS<1:0> (IPC8<9:8>). FSCM Interrupt Enable FSCMIE (IEC1<14>) Watchdog Timer, enabled, will continue count same rate regardless SYSCLK frequency. Care must taken service after Fail-Safe Clock Monitor event, taking into account change SYSCLK.
Note:
DS61143E-page
2008 Microchip Technology Inc.
PIC32MX3XX/4XX
4.2.5.1 FSCM Delay
Note: POR, wake from Sleep mode event, nominal delay (TFSCM) inserted before FSCM begins monitor system clock source. Refer Section "Resets" FSCM delay timing information. TFSCM interval applied whenever FSCM enabled HSPLL, XTPLL, SOSC Oscillator modes selected system clock. Note: Please refer Electrical Characteristics section TFSCM specification values. device does prevent changin
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