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Low Noise, Precision Instrumentation Amplifier AMP01

PIN CONFIGURATIONS 18-Lead Cerdip

Low Noise, Precision Instrumentation Amplifier AMP01
PIN CONFIGURATIONS 18-Lead Cerdip
RG 1 RG 2 -IN 3 VOOS NULL 4 VOOS NULL 5 TEST PIN 6 SENSE 7 REFERENCE 8 OUTPUT 9
18 +IN 17 VIOS NULL 16 VIOS NULL 15 RS 14 RS 13 +VOP 12 V+ 11
AMP01
10 -VOP
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
TOP VIEW (Not to Scale) MAKE NO ELECTRICAL CONNECTION
AMP01 BTC / 883 28-Terminal LCC
VIOS NULL
NC 5 VOOS NULL 6 NC 7 VOOS NULL 8 NC 9 TEST PIN 10 NC 11
VIOS NULL NC RS RS +VOP NC V+
AMP01
TOP VIEW (Not to Scale)
SENSE
MAKE NO ELECTRICAL CONNECTION
20-Lead SOL
RG TEST PIN -IN VOOS NULL VOOS NULL TEST PIN SENSE REFERENCE OUTPUT
RG TEST PIN +IN VIOS NULL VIOS NULL
AMP01
TOP VIEW 15 R S (Not to Scale) 14 RS 7
-VOP 10
MAKE NO ELECTRICAL CONNECTION
+VOP V+ V-
AMP01-SPECIFICATIONS
Symbol VIOS TCVIOS VOOS TCVOOS PSR
Input Offset Voltage Trim Range Output Offset Voltage Trim Range INPUT CURRENT Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT Input Resistance Input Voltage Range Common-Mode Rejection IB TCIB IOS TCIOS RIN IVR CMR
NOTES 1 VIOS and VOOS nulling has minimal affect on TCV IOS and TCVOOS respectively. 2 Refer to section on common-mode rejection. Specifications subject to change without notice.
REV. C
AMP01 ELECTRICAL CHARACTERISTICS grades, 0 C T +70 C for G grade, unless otherwise noted)
Symbol VIOS TCVIOS VOOS TCVOOS PSR
Input Offset Voltage Trim Range Output Offset Voltage Trim Range INPUT CURRENT Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT Input Resistance Input Voltage Range Common-Mode Rejection
NOTES 1 Sample tested. 2 VIOS and VOOS nulling has minimal affect on TCV IOS and TCVOOS, respectively. 3 Refer to section on common-mode rejection. Specifications subject to change without notice.
REV. C
Min AMP01A / E Typ Max Min AMP01B / F / G Typ Max Units
Parameter GAIN Gain Equation Accuracy
Symbol Conditions
Temperature Coefficient OUTPUT RATING Output Voltage Swing
GTC VOUT
Positive Current Limit Negative Current Limit Capacitive Load Stability Thermal Shutdown Temperature NOISE Voltage Density, RTI
Noise Current Density, RTI Input Noise Voltage
nV / Hz nV / Hz nV / Hz nV / Hz pA / Hz µV p-p µV p-p µV p-p µV p-p pA p-p kHz kHz kHz kHz V / µs µs µs µs µs
Input Noise Current DYNAMIC RESPONSE Small-Signal Bandwidth (-3 dB) Slew Rate Settling Time
NOTES 1 Guaranteed by design. 2 Gain tempco does not include the effects of gain and scale resistor tempco match. 3 -55°C TA +125°C for A / B grades, -25°C TA +85°C for E / F grades, 0°C TA 70°C for G grades. Specifications subject to change without notice.
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Parameter SENSE INPUT Input Resistance Input Current Voltage Range REFERENCE INPUT Input Resistance Input Current Voltage Range Gain to Output
Symbol Conditions RIN IIN
Referenced to V- (Note 1)
RIN IIN
Referenced to V- (Note 1)
NOTE 1 Guaranteed by design. Specifications subject to change without notice.
DICE CHARACTERISTICS
RG RG -INPUT VOOS NULL VOOS NULL TEST PIN SENSE REFERENCE OUTPUT
V- (OUTPUT) V- V+ V+ (OUTPUT) RS RS VIOS NULL VIOS NULL +INPUT
MAKE NO ELECTRICAL CONNECTION
ORDERING GUIDE Model AMP01AX AMP01BX AMP01BTC / 883 AMP01EX AMP01FX AMP01GS Temperature Range -55°C to +125°C -55°C to +125°C -55°C to +125°C -25°C to +85°C -25°C to +85°C 0°C to +70°C Package Description 18-Lead Cerdip 18-Lead Cerdip 28-Terminal LCC 18-Lead Cerdip 18-Lead Cerdip 20-Lead SOIC Package Options Q-18 Q-18 E-28A Q-18 Q-18 R-20
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AMP01 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
REV. C
Parameter Input Offset Voltage Output Offset Voltage Offset Referred to Input vs. Positive Supply
Symbol Conditions VIOS VOOS PSR
Offset Referred to Input vs. Negative Supply
Input Bias Current Input Offset Current Input Voltage Range Common Mode Rejection
IB IOS IVR CMR
Gain Equation Accuracy Output Voltage Swing Output Current Limit Output Current Limit Quiescent Current VOUT VOUT VOUT IQ
NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
V+ VIOS NULL A1 250 -IN +IN REFERENCE R1 47.5k RGAIN A2 RSCALE R2 2.5k VOOS NULL R4 2.5k V- A3 R3 47.5k 250 Q1 Q2 +VOP OUTPUT -VOP
SENSE
Figure 1. Simplified Schematic
REV. C
Parameter Input Offset Voltage Drift Output Offset Voltage Drift Input Bias Current Drift Input Offset Current Drift Nonlinearity Voltage Noise Density Current Noise Density Voltage Noise Current Noise
Symbol TCVIOS TCVOOS TCIB TCIOS en in en p-p in p-p
Small-Signal Bandwidth (-3 dB) BW Slew Rate SR Settling Time tS
NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. C
AMP01-Typical Performance Characteristics
INPUT OFFSET VOLTAGE - V
8 INPUT OFFSET VOLTAGE - V 6 4 2 0 -2 -4 -6 0 25 50 75 100 125 150 TEMPERATURE - C 3 4 UNIT NO. 1 2
OUTPUT OFFSET VOLTAGE - mV
10 15 5 POWER SUPPLY VOLTAGE - Volts
-5 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE - C
Figure 2. Input Offset Voltage vs. Temperature
Figure 3. Input Offset Voltage vs. Supply Voltage
Figure 4. Output Offset Voltage vs. Temperature
OUTPUT OFFSET VOLTAGE CHANGE - mV
INPUT BIAS CURRENT - nA
5 10 15 20 POWER SUPPLY VOLTAGE - Volts
10 15 5 POWER SUPPLY VOLTAGE - Volts
Figure 5. Output Offset Voltage Change vs. Supply Voltage
Figure 6. Input Bias Current vs. Temperature
Figure 7. Input Bias Current vs. Supply Voltage
INPUT OFFSET CURRENT - nA
140 COMMON-MODE REJECTION - dB
COMMON-MODE REJECTION - dB
0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE - C
100 1 10 100 1k VOLTAGE GAIN - G 10k
Figure 8. Input Offset Current vs. Temperature
Figure 9. Common-Mode Rejection vs. Voltage Gain
Figure 10. Common-Mode Rejection vs. Frequency
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AMP01
COMMON-MODE INPUT VOLTAGE - Volts
POWER SUPPLY REJECTION - dB
100 1k FREQUENCY - Hz
Figure 11. Common-Mode Voltage Range vs. Temperature
Figure 12. Positive PSR vs. Frequency
Figure 13. Negative PSR vs. Frequency
18 16 OUITPUT VOLTAGE - Volts 14 12 10 8 6 4 2 0 10 100 1k LOAD RESISTANCE - 10k
PEAK-TO-PEAK AMPLITUDE - Volts
OUTPUT IMPEDANCE -
10k 100k FREQUENCY - Hz
1k 10k 100k FREQUENCY - Hz
Figure 14. Maximum Output Voltage vs. Load Resistance
Figure 15. Maximum Output Swing vs. Frequency
Figure 16. Closed-Loop Output Impedance vs. Frequency
-40 1 10 100 1k 10k FREQUENCY - Hz 100k 1M
100 1k FREQUENCY - Hz
1k LOAD RESISTANCE -
Figure 17. Closed-Loop Voltage Gain vs. Frequency
Figure 18. Total Harmonic Distortion vs. Frequency
Figure 19. Total Harmonic Distortion vs. Load Resistance
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AMP01
0 1 10 100 VOLTAGE GAIN - G 1k
0 100p
10 1n 10n 100n LOAD CAPACITANCE - F 1 1 10 100 VOLTAGE GAIN - G 1k
Figure 20. Slew Rate vs. Voltage Gain
Figure 21. Slew Rate vs. Load Capacitance
POSITIVE SUPPLY CURRENT - mA
100 1k FREQUENCY - Hz
1 1 10 100 VOLTAGE GAIN - G 1k
5 10 15 POWER SUPPLY VOLTAGE - Volts
Figure 23. Voltage Noise Density vs. Frequency
Figure 24. RTI Voltage Noise Density vs. Gain
Figure 25. Positive Supply Current vs. Supply Voltage
NEGATIVE SUPPLY CURRENT - mA
POSITIVE SUPPLY CURRENT - mA
5 10 15 POWER SUPPLY VOLTAGE - Volts
0 25 50 75 100 125 150 TEMPERATURE - C
Figure 26. Negative Supply Current vs. Supply Voltage
Figure 27. Positive Supply Current vs. Temperature
Figure 28. Negative Supply Current vs. Temperature
REV. C
AMP01
INPUT AND OUTPUT OFFSET VOLTAGES GAIN
TCV OOS G
AMP01
9 OUTPUT
8 11 REFERENCE
Figure 29. Basic AMP01 Connections for Gains 0.1 to 10, 000
INPUT BIAS AND OFFSET CURRENTS
Input transistor bias currents are additional error sources that can degrade the input signal. Bias currents flowing through the signal source resistance appear as an additional offset voltage. Equal source resistance on both inputs of an IA will minimize offset changes due to bias current variations with signal voltage and temperature. However, the difference between the two bias currents, the input offset current, produces a nontrimmable error. The magnitude of the error is the offset current times the source resistance. A current path must always be provided between the differential inputs and analog ground to ensure correct amplifier operation. Floating inputs, such as thermocouples, should be grounded close to the signal source for best common-mode rejection.
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AMP01
RESISTANCE -
RS 10k
ACTIVE GUARD DRIVE
100 1 10 100 VOLTAGE GAIN 1k 10k
COMMON-MODE REJECTION
Rejection of common-mode noise and line pick-up can be improved by using shielded cable between the signal source and the IA. Shielding reduces pick-up, but increases input capacitance, which in turn degrades the settling-time for signal changes. Further, any imbalance in the source resistance between the inverting and noninverting inputs, when capacitively loaded, converts the common-mode voltage into a differential voltage. This effect reduces the benefits of shielding. AC common-mode rejection is improved by "bootstrapping" the input cable capacitance to the input signal, a technique called "guard driving." This technique effectively reduces the input capacitance. A single guard-driving signal is adequate at gains above 100 and should be the average value of the two inputs. The value of external gain resistor RG is split between two resistors RG1 and RG2 the center tap provides the required signal to drive the buffer amplifier (Figure 31).
GROUNDING
Ideally, an instrumentation amplifier responds only to the difference between the two input signals and rejects commonmode voltages and noise. In practice, there is a small change in output voltage when both inputs experience the same commonmode voltage change the ratio of these voltages is called the common-mode gain. Common-mode rejection (CMR) is the logarithm of the ratio of differential-mode gain to commonmode gain, expressed in dB. CMR specifications are normally measured with a full-range input voltage change and a specified source resistance unbalance. The current-feedback design used in the AMP01 inherently yields high common-mode rejection. Unlike resistive feedback designs, typified by the three-op-amp IA, the CMR is not degraded by small resistances in series with the reference input. A slight, but trimmable, output offset voltage change results from resistance in series with the reference input. The common-mode input voltage range, CMVR, for linear operation may be calculated from the formula:
The majority of instruments and data acquisition systems have separate grounds for analog and digital signals. Analog ground may also be divided into two or more grounds which will be tied together at one point, usually the analog power-supply ground. In addition, the digital and analog grounds may be joined, normally at the analog ground pin on the A-to-D converter. Following this basic grounding practice is essential for good circuit performance (Figure 32). Mixing grounds causes interactions between digital circuits and the analog signals. Since the ground returns have finite resistance and inductance, hundreds of millivolts can be developed between the system ground and the data acquisition components. Using separate ground returns minimizes the current flow in the sensitive analog return path to the system ground point. Consequently, noisy ground currents from logic gates do not interact with the analog signals. Inevitably, two or more circuits will be joined together with their grounds at differential potentials. In these situations, the differential input of an instrumentation amplifier, with its high CMR, can accurately transfer analog information from one circuit to another.
SENSE AND REFERENCE TERMINALS
The sense terminal completes the feedback path for the instrumentation amplifier output stage and is normally connected directly to the output. The output signal is specified with respect to the reference terminal, which is normally connected to analog ground.
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AMP01
C3 0.047 F RS 10k 15 +IN +15V 7 GUARD DRIVE 6 741 3 4 -15V -IN 3 2 RG3 200 RG2 200 RG1 400 1 18 RS 14 RS 6 13 12 RG V+ 7 9 8 R5 OUTPUT SENSE NC +15V
AMP01
2 RG VIOS NULL 16 VOOS NULL 4 17 10 5
SOLDER LINK
VR1 100k REFERENCE R3
VR2 100k
SIGNAL GROUND C4 0.047 F GROUND + C6 10 F C2 0.047 F
Figure 31. AMP01 Evaluation Circuit Showing Guard-Drive Connection
ANALOG POWER SUPPLY +15V 0V -15V 0V
DIGITAL POWER SUPPLY +5V
4.7 F + C C C C DIGITAL GROUND C C C
AMP01
ANALOG GROUND SMP-11 SAMPLE AND HOLD
DIGITAL GROUND ADC
DIGITAL DATA OUTPUT
OUTPUT REFERENCE
HOLD CAPACITOR
Figure 32. Basic Grounding Practice
REV. C
AMP01
DRIVING 50 LOADS
combination of these unique features in an instrumentation amplifier allows low-level transducer signals to be conditioned and directly transmitted through long cables in voltage or current form. Increased output current brings increased internal dissipation, especially with 50 loads. For this reason, the power-supply connections are split into two pairs pins 10 and 13 connect to the output stage only and pins 11 and 12 provide power to the input and following stages. Dual supply pins allow dropper resistors to be connected in series with the output stage so excess power is dissipated outside the package. Additional decoupling is necessary between pins 10 and 13 to ground to maintain stability when dropper resistors are used. Figure 34 shows a complete circuit for driving 50 loads.
Output currents of 50 mA are guaranteed into loads of up to 50 and 26 mA into 500 . In addition, the output is stable and free from oscillation even with a high load capacitance. The
IN4148 DIODES ARE OPTIONAL. DIODES LIMIT THE OUTPUT
VOLTAGE EXCURSION IF SENSE AND / OR REFERENCE LINES BECOME DISCONNECTED FROM THE LOAD. SENSE
9 TWISTED PAIRS REMOTE LOAD
AMP01
REFERENCE
OUTPUT GROUND V-
Figure 33. Remote Load Sensing
+15V RS 5k 14 R1 130 1W C1 0.047 F 15 12 SENSE 0.047 F
13 7 9 8 10 11 REFERENCE C2 0.047 F R2 130 1W VOUT 3V MAX 50 LOAD
AMP01
0.047 F -15V
Figure 34. Driving 50 Loads
RESISTERS R1 AND R2 REDUCE IC DISSIPATION
REV. C
AMP01
HEATSINKING
External series resistors could be added to guard against higher voltage levels at the input, but resistors alone increase the input noise and degrade the signal-to-noise ratio, especially at high gains. Protection can also be achieved by connecting back-to-back 9.1 V Zener diodes across the differential inputs. This technique does not affect the input noise level and can be used down to a gain of 2 with minimal increase in input current. Although voltage-clamping elements look like short circuits at the limiting voltage, the majority of signal sources provide less than 50 mA, producing power levels that are easily handled by low-power Zeners. Simultaneous connection of the differential inputs to a low impedance signal above 10 V during normal circuit operation is unlikely. However, additional protection involves adding 100 current-limiting resistors in each signal path prior to the voltage clamp, the resistors increase the input noise level to just 5.4 nV / Hz (refer to Figure 35). Input components, whether multiplexers or resistors, should be carefully selected to prevent the formation of thermocouple junctions that would degrade the input signal.
OPTIONAL PROTECTION
RESISTORS, SEE TEXT. 100 1W +IN 9.1V 1W ZENERS 100 1W +15V LINEAR INPUT RANGE, 5V MAXIMUM DIFFERENTIAL PROTECTION TO 30V
OVERVOLTAGE PROTECTION
AMP01
Figure 35. Input Overvoltage Protection for Gains 2 to 10, 000
POWER SUPPLY CONSIDERATIONS
Achieving the rated performance of precision amplifiers in a practical circuit requires careful attention to external influences. For example, supply noise and changes in the nominal voltage directly affect the input offset voltage. A PSR of 80 dB means that a change of 100 mV on the supply, not an uncommon value, will produce a 10 µV input offset change. Consequently, care should be taken in choosing a power unit that has a low output noise level, good line and load regulation, and good temperature stability.
REV. C
AMP01
ROUT TRIM 13 SENSE 7 9 8 10 REFERENCE
R2 200 R1 100
AMP01
Figure 36. High Compliance Bipolar Current Source with 13-Bit Linearity
15 RS 12 V+ 13 R3 100 7 R2 200 ROUT TRIM 2 9 8 R5 2.21k 4 REF-02 6
1 RG 2.75k 2
AMP01
R6 500 ZERO TRIM R1 100
-IN 0V
0.047 F
IOUT 4mA TO 20mA
Figure 37. 13-Bit Linear 4-20 mA Transmitter Constructed by Adding a Voltage Reference. Thermocouple Signals Can Be Accepted Without Preamplification.
REV. C
AMP01
+15V + 0.047 F 10 F
10k 14 +IN 18 RS 15 RS 2N4921 12 V+ 0.047 F SENSE 7 9 8 REFERENCE
AMP01
VOUT ( 10V INTO 10 )
2N4918
Q1, Q2......J110 Q3, Q4, Q5..J107 IC1 ........CMP-04 IC2 ........OP15GZ +IN -IN 200k 47k 47k Q3 47k 47k +15V 6 7 IC2 4 -15V 3 4 6 8 10 2.7k
18 1 20k 2k 196 Q4 Q5 RG
Q2 Q1 2 3 RG VIOS NULL 17 16 VOOS NULL 4 11 5
IC1 12
27k +15V
9 G100
11 G1000
TTL COMPATIBLE INPUTS
Figure 39. The AMP01 Makes an Excellent Programmable-Gain Instrumentation Amplifier. Combined Gain-Switching and Settling Time to 13 Bits Falls Below 100 µ s. Linearity Is Better than 12 Bits over a Gain Range 1 to 1000.
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+ -15V
RS 10k +15V 14 RS 15 RS 12 V+ 13 SENSE 7 9 V- 10 8 REFERENCE GND 0.047 F
0.047 F
AMP01
0.047 F 100k 100k
AMP01
RS 10k 14 +IN 18 RS 15 RS 1 12 V+ 1.5k 5k 470pF 3 4 7 OP37 6 +15V 0.047 F 0V
AMP01
3 0.047 F 0V
-15V RL + OUTPUT DIFFERENTIAL COMMON-MODE OUTPUT REFERENCE ( 5V MAX)
8 18 VIN 1 R1 390 2 RG RS RS 14 15 V- 11 RG REF 7 SENSE 12 V+
AMP01
R2 4.95k 0.047 F +
REV. C
AMP01
NC NC R2 220k
R1 VIN 0.01 F
7 SENSE 8 REF 9 VOUT
AMP01
20V p-p INTO 500
/ / 1000pF.
R2 GAIN (G) + 10 F 0.047 F + +15V -15V 10 F 0.047 F
R1 4.7k VIN
680pF 18
8 REF 7 SENSE 12 V+ 0.047 F
AMP01
R2 4.7k 0.047 F +
Figure 43. Stability with Large Capacitive Loads Combined with High Output Current Capability make the AMP01 Ideal for Line Driving Applications. Offset Voltage Drift Approaches the TCVIOS Limit, (0.3 µ V / °C).
REV. C
AMP01
eOUT 100 G
Figure 44. Noise Test Circuit (0.1 Hz to 10 Hz)
200 10T
AMP01
0.047 F V+ V-
0.047 F
Figure 45. Settling-Time Test Circuit
REV. C
AMP01
SENSE 7 9 8 REFERENCE 15k 7.5k
13 4 DAC-08 1, 2 16 3
0.047 F R1 100 0.01 F 7.5k TTL INPUT "OFFSET" 0V TTL INPUT "ZERO" -15V
Figure 46. Instrumentation Amplifier with Auto-Zero
+18V 10k 0.047 F 14 18 1 10k 2 3 RG 11 0.047 F -18V RG RS 15 12 RS SENSE 13 7 9 8 10 VOUT
AMP01
Figure 47. Burn-In Circuit
REV. C
AMP01
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
18-Lead Cerdip (Q-18)
0.005 (0.13) MIN
0.098 (2.49) MAX
PIN 1 0.960 (24.38) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.78) SEATING 0.030 (0.76) PLANE 15 0
28-Terminal Ceramic Leadless Chip Carrier (E-28A)
0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.088 (2.24) 0.054 (1.37)
0.300 (7.62) BSC 0.150 (3.51) BSC
0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC 45 TYP
0.458 (11.63) 0.442 (11.23) 0.458 SQ (11.63) MAX SQ
BOTTOM VIEW
0.200 (5.08) BSC
20-Lead Wide Body (R-20)
8 0.0500 0.0192 (0.49) 0 (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE BSC 0.0091 (0.23)
REV. C
PRINTED IN U.S.A.
C3103a-0-6 / 98