The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

14/12-Bit, 250/210 MSPS ADCs With LVDS Parallel CMOS Outputs FEAT


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



ADS6149/ADS6129 ADS6148/ADS6128
14/12-Bit, 250/210 MSPS ADCs With LVDS Parallel CMOS Outputs
FEATURES
Maximum Sample Rate: MSPS 14-Bit Resolution ADS614X 12-Bit Resolution ADS612X Total Power Dissipation MSPS Double Data Rate (DDR) LVDS Parallel CMOS Output Options Programmable Fine Gain SNR/SFDR Trade-off Offset Correction Supports Input Clock Amplitude Down mVPP Differential Internal External Reference Support 48-QFN Package (7mm 7mm) Compatible with ADS5547 Family
DESCRIPTION
ADS614X (ADS612X) family 14-bit (12-bit) converters with sampling rates MSPS. combines high dynamic performance power consumption compact package. This makes well-suited multicarrier, wide band-width communications applications. ADS614X/2X fine gain options that used improve SFDR performance lower full-scale input ranges. includes offset correction loop that used cancel offset. Both LVDS (Double Data Rate) parallel CMOS digital output interfaces available. lower sampling rates, automatically operates scaled down power with loss performance. includes internal references while traditional reference pins associated decoupling capacitors have been eliminated. Nevertheless, device also driven with external reference. device specified over industrial temperature range (-40°C 85°C).
MSPS ADS614X 14-Bit Family ADS612X 12-Bit Family ADS6149 ADS6129 MSPS ADS6148 ADS6128
APPLICATIONS
Multicarrier, Wide Band-Width Communications Wireless Multi-carrier Communications Infrastructure Software Defined Radio Power Amplifier Linearization 802.16d/e Test Measurement Instrumentation High Definition Video Medical Imaging Radar Systems
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2008, Texas Instruments Incorporated
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
These devices have limited built-in protection. leads should shorted together device placed conductive foam during storage handling prevent electrostatic damage gates.
ADS614X BLOCK DIAGRAM
DRGND DRVDD AGND AVDD
LVDS Interface CLKP CLKM CLOCKGEN CLKOUTP CLKOU
D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M Sample Hold 14-Bit Serializer D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M Reference Control Interface D12_D13_P D12_D13_M
OVR_SDOUT ADS6149/48
RESET
SDATA
MODE
SCLK
B0095-06
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
ADS612X BLOCK DIAGRAM
DRGND DRVDD AGND AVDD
LVDS Interface CLKP CLKM CLOCKGEN CLKOUTP CLKOU
D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M Sample Hold 12-Bit Serializer D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M Reference Control Interface
OVR_SDOUT
ADS6129/28
RESET
SDATA
MODE
SCLK
B0095-07
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
PACKAGE/ORDERING INFORMATION
PRODUCT ADS614x ADS6149 QFN-48 ADS6148 ADS612x ADS6129 QFN-48 ADS6128 -40°C 85°C NiPdAu AZ6128 AZ6129 ADS6129IRGZR ADS6129IRGZT ADS6128IRGZR ADS6128IRGZT Tape reel -40°C 85°C NiPdAu AZ6148 AZ6149 ADS6149IRGZR ADS6149IRGZT ADS6148IRGZR ADS6148IRGZT Tape reel PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE LEAD/BALL FINISH PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY
thermal size package, mechanical drawings this data sheet. 25.41° (0LFM flow), 16.5° when used with 2oz. copper trace soldered directly JEDEC standard four layer (7.62 7.62 PCB. most current package ordering information, Package Option Addendum this document, website www.ti.com. PREVIEW device status
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
SUPPLIES AVDD DRVDD Analog supply voltage Digital supply voltage Differential input voltage range Input common-mode voltage Voltage applied external reference mode CLOCK INPUT Input clock sample rate ADS6149 ADS6129 ADS6148 ADS6128 Sine wave, ac-coupled Input Clock amplitude differential (VCLKP-VCLKM) Input clock duty cycle DIGITAL OUTPUTS Maximum external load capacitance from each output DRGND Differential load resistance between LVDS output pairs (LVDS mode) Operating free-air temperature LVPECL, ac-coupled LVDS, ac-coupled LVCMOS, single-ended, ac-coupled MSPS ±0.1 0.05 UNIT
ANALOG INPUTS
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
ELECTRICAL CHARACTERISTICS ADS614X ADS612X
Typical values 25°C, AVDD DRVDD clock duty cycle, -1dBFS differential analog input, internal reference mode unless otherwise noted. values across full temperature range TMIN -40°C TMAX 85°C, AVDD DRVDD
PARAMETER ANALOG INPUT Differential input voltage range Differential input resistance dc), Figure Differential input capacitance, Figure Analog Input Bandwidth Analog Input common mode current (per input pin) Common mode output voltage output current capability ACCURACY Offset error Temperature coefficient offset error Variation offset error with supply EGREF EGCHAN Gain error internal reference inaccuracy alone Gain error channel alone Temperature coefficient EGCHAN POWER SUPPLY IAVDD Analog supply current Output buffer supply current, LVDS interface with external termination Output buffer supply current, CMOS interface MHz, 10-pF external load capacitance Analog power Digital power LVDS interface Digital power CMOS interface, MHz, 10-pF external load capacitance Global power down Standby -1.25 0.005 ±0.2 .001 1.25 0.005 .001 mV/°C mV/V %/°C µA/MSPS ADS6149/ADS6129 MSPS ADS6148/ADS6128 MSPS UNIT
IDRVDD
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
ELECTRICAL CHARACTERISTICS ADS6149 ADS6148
Typical values 25°C, AVDD DRVDD clock duty cycle, -1dBFS differential analog input, internal reference mode unless otherwise noted. values across full temperature range TMIN -40°C TMAX 85°C, AVDD DRVDD
PARAMETER Signal noise ratio, LVDS SINAD Signal noise distortion ratio, LVDS ENOB Effective number bits Differential non-linearity Integrated non-linearity -0.95 ADS6149 MSPS 73.4 72.7 72.3 71.3 73.2 72.4 71.9 70.6 11.4 ±0.4 ADS6148 MSPS 73.4 72.7 72.3 71.2 73.3 72.4 71.8 70.9 68.2 11.5 ±0.4 dBFS dBFS UNIT
ELECTRICAL CHARACTERISTICS ADS6129 ADS6128
Typical values 25°C, AVDD DRVDD clock duty cycle, -1dBFS differential analog input, internal reference mode unless otherwise noted. values across full temperature range TMIN -40°C TMAX 85°C, AVDD DRVDD
PARAMETER SNR, Signal noise ratio, LVDS SINAD Signal noise distortion ratio, LVDS ENOB, Effective number bits Differential non-linearity Integrated non-linearity 10.8 -0.5 -2.5 66.5 67.5 ADS6129 MSPS 70.7 70.5 70.1 69.5 67.8 70.6 70.4 69.8 69.2 67.2 11.2 ±0.2 ADS6128 MSPS 70.9 70.5 70.1 69.5 67.9 70.8 70.4 69.8 69.3 67.3 11.2 ±0.2 dBFS dBFS UNIT
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
ELECTRICAL CHARACTERISTICS ADS614x ADS612x
Typical values 25°C, AVDD DRVDD clock duty cycle, -1dBFS differential analog input, internal reference mode unless otherwise noted. values across full temperature range TMIN -40°C TMAX 85°C, AVDD DRVDD
PARAMETER SFDR Spurious Free Dynamic Range Total Harmonic Distortion HD2, Second Harmonic Distortion Third Harmonic Distortion Worst Spur Other than second, third harmonics 2-Tone inter-modulation distortion MHz, MHz, Each tone dBFS MHz, MHz, Each tone dBFS Recovery within final value) 6-dB overload with sine wave input mVpp signal AVDD supply ADS6149/ADS6129 MSPS ADS6148/ADS6128 MSPS 88.5 dBFS clock cycles UNIT
Input overload recovery PSRR power supply rejection ratio
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
DIGITAL CHARACTERISTICS ADS614x ADS612x
specifications refer condition where digital outputs switching, permanently valid logic level AVDD DRVDD
PARAMETER DIGITAL INPUTS RESET, SCLK, SDATA, High-level input voltage Low-level input voltage High-level input current Low-level input current Input capacitance DIGITAL OUTPUTS CMOS INTERFACE (Pins OVR_SDOUT) High-level output voltage Low-level output voltage Output capacitance (internal device) DIGITAL OUTPUTS LVDS INTERFACE (Pins D0_D1_P/M D12_D13_P/M) VODH, High-level output voltage VODL, Low-level output voltage
TEST CONDITIONS
ADS6149/ADS6148/ ADS6129/ADS6128
UNIT
digital inputs support 1.8V 3.3V CMOS logic levels SDATA, SCLK SDATA, SCLK VHIGH 3.3V VHIGH 3.3V VLOW VLOW
DRVDD -425 -350 -275
VOCM, Output common-mode voltage Output capacitance Capacitance inside device, from either output ground
SCLK, SDATA, function digital input pins serial configuration mode. SDATA, SCLK have internal pull-down resistor internal pull-up resistor DRVDD. OVR_SDOUT CMOS output logic levels, determined DRVDD voltage. With external termination
Dn_Dn+1_P Dn_Dn+1_P Logic VODL -350 Dn_Dn+1_M Dn_Dn+1_M VOCM
Logic VODH
T0399-0
Figure LVDS Voltage Levels
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
TIMING REQUIREMENTS LVDS CMOS MODES
Typical values 25°C, AVDD 3.3V, DRVDD 1.8V, sampling frequency MSPS, sine wave input clock, CLOAD (2), RLOAD (3), SPEED mode disabled, unless otherwise noted. values across full temperature range TMIN -40°C TMAX 85°C, AVDD 3.3V, DRVDD 1.7V 1.9V.
PARAMETER Aperture delay Aperture jitter Time valid data after coming STANDBY mode Wake-up time Time valid data after coming GLOBAL mode Time valid data after stopping restarting input clock Latency LVDS MODE tPDI
TEST CONDITIONS
UNIT
clock cycles clock cycles
Default, after reset
Data setup time Data hold time Clock propagation delay tdelay LVDS clock duty cycle
Data valid
zero-crossing CLKOUTP
0.25
Zero-crossing CLKOUT data becoming invalid Input clock rising edge cross-over output clock rising edge cross-over MSPS Sampling frequency MSPS Duty cycle differential clock, (CLKOUTP-CLKOUTM) MSPS Sampling frequency MSPS Rise time measured from -100 Fall time measured from -100 MSPS Sampling frequency MSPS Rise time measured from -100 Fall time measured from -100 MSPS Sampling frequency MSPS Time valid data after becomes active Input clock rising edge cross-over start data valid Time interval valid data Input clock rising edge cross-over output clock rising edge cross-over MSPS Sampling frequency MSPS Duty cycle differential clock, (CLKOUT) MSPS Sampling frequency MSPS Rise time measured from DRVDD, Fall time measured from DRVDD, MSPS Sampling frequency MSPS Rise time measured from DRVDD, Fall time measured from DRVDD, MSPS Sampling frequency MSPS Time valid data after becomes active
tdelay
tRISE, tFALL tCLKRISE, tCLKFALL tSTART tPDI
Data rise time, Data fall time Output clock rise time, Output clock fall time Output enable (OE) data delay
0.08
0.14
0.08
0.14
PARALLEL CMOS MODE Input clock data delay Data valid time Clock propagation delay tdelay Output clock duty cycle tRISE, tFALL tCLKRISE, tCLKFALL Data rise time, Data fall time Output clock rise time, Output clock fall time Output enable (OE) data delay
0.78 tdelay
Timing parameters specified design characterization tested production. CLOAD effective external single-ended load capacitance between each output ground RLOAD differential load resistance between LVDS output pair. higher frequencies, tPDI greater than clock period overall latency latency Measurements done with transmission line characteristic impedance between device load. Setup hold time specifications take into account effect jitter output data clock. Data valid refers LOGIC HIGH +100mV LOGIC -100mV. MSPS, recommended external clock data capture device output clock signal (CLKOUT). Data valid refers LOGIC HIGH 1.26V LOGIC 0.54V.
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
LVDS Timings Lower Sampling Frequencies
SAMPLING FREQUENCY, MSPS <100 Enable SPEED mode 100, Enable SPEED mode SETUP TIME, tPDI, HOLD TIME,
CMOS Timings Lower Sampling Frequencies
Timings specified with respect input clock SAMPLING FREQUENCY, MSPS tSTART, DATA VALID TIME,
Timings specified with respect CLKOUT SAMPLING FREQUENCY, MSPS <100 Enable SPEED mode Enable SPEED mode SETUP TIME, tPDI, HOLD TIME,
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
N+18 N+20
Sample Input Signal
N+19
Input Clock
CLKP CLKM
CLKOUCLKOUTP LVDS Output Data DXP, Clock Cycles* tPDI
Even Bits D0,D2,D4,. Bits D1,D3,D5,
N-18
N-17
N-16
N-15
tPDI CLKOUT Clock Cycles* N-14
Parallel CMOS
Output Data
N-18
N-17
N-16
N-15
This latency. higher sampling frequencies, tPDI clock cycle. Then, overall latency latency latency clock cycles low-latency mode.
T0105-09
Figure Latency Diagram
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
Input Clock
CLKP CLKM tPDI
Output Clock
CLKOUTP CLKOUth
Output Data Pair
Dn_Dn+1_P, Dn_Dn+1_M
Bits D4,.
T0106-07
Dn+1 Bits
Figure LVDS Mode Timing
CLKM CLKP tPDI Output Clock
Input Clock
CLKOUT
Output Data
Input Clock
CLKM CLKP tSTART
Output Data
Bits
T0107-05
Figure CMOS Mode Timing
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
DEVICE CONFIGURATION
ADS614X/2X configured independently using either parallel interface control serial interface programming.
PARALLEL CONFIGURATION ONLY
device parallel configuration mode, keep RESET tied HIGH (DRVDD). Now, pins DFS, MODE, SDATA used directly control certain modes ADC. device easily configured connecting parallel pins correct voltage levels described Table Table There need apply reset. this mode, SDATA function parallel interface control pins. Frequently used functions controlled this mode standby, selection between LVDS/CMOS output format, internal/external reference, two's complement/straight binary output format position output clock edge. Table briefly describes modes controlled parallel pins. Table Parallel Functions
MODE SDATA TYPE CONTROL Analog Analog Analog Digital CONTROLS MODES Data format LVDS/CMOS output interface. Internal external reference, speed mode enable CLKOUT edge programmability. Global power-down (ADC, internal references output buffers powered down)
next generation pin-compatible family, MODE will converted digital control certain reserved functions. selection internal external reference speed functions will supported using MODE. system board using ADS61x9/x8, MODE routed digital controller. This will avoid board modification while migrating next generation ADC.
SERIAL INTERFACE CONFIGURATION ONLY
exercise this mode, first serial registers have reset their default values RESET kept LOW. SEN, SDATA SCLK function serial interface pins this mode used access internal registers ADC. registers reset either applying pulse RESET setting HIGH <RESET> register 0x00). serial interface section describes register programming register reset more detail. Since parallel pins MODE used this mode, they have tied ground.
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
CONFIGURATION USING BOTH SERIAL INTERFACE PARALLEL CONTROLS
increased flexibility, additional configuration mode supported wherein combination serial interface registers parallel controls (DFS, MODE) used configure device. exercise this mode, serial registers have reset their default values RESET kept LOW. SEN, SDATA SCLK function serial interface pins this mode used access internal registers ADC. registers reset either applying pulse RESET setting HIGH <RESET> register 0x00). serial interface section describes register programming register reset more detail. parallel interface control pins MODE used their function determined appropriate voltage levels described Table voltage levels easily derived, using resistor string illustrated with example shown Figure Since some functions controlled using both parallel pins serial registers, priority between determined Priority Table shown Table Table Priority Between Parallel Pins Serial Registers
FUNCTION Internal/External reference Data format selection LVDS CMOS interface selection PRIORITY MODE controls this selection ONLY register bits <REF> otherwise <REF> controls selection controls this selection ONLY register bits <DATA FORMAT> otherwise <DATA FORMAT> controls selection controls this selection ONLY register bits <LVDS CMOS> otherwise <LVDS CMOS> controls selection
DESCRIPTION PARALLEL PINS
Table SDATA DIGITAL CONTROL
SDATA AVDD Normal operation (default) Global power-down. ADC, internal references output buffers powered down. DESCRIPTION
Table ANALOG CONTROL
(3/8)AVDD (5/8)AVDD AVDD DESCRIPTION Output Clock Edge Programmability LVDS: Data output clock transitions aligned CMOS: Setup time increases (6xTs/26), Hold time reduces (6xTs/26) LVDS: Setup time decreases (4xTs/26), Hold time increases (4xTs/26) CMOS: Setup time increases (9xTs/26), Hold time reduces (9xTs/26) LVDS: Setup time increases (4xTs/26), Hold time reduces (4xTs/26) CMOS: Setup time increases (3xTs/26), Hold time reduces (3xTs/26) Default output clock position (Setup/hold timings output data with respect this clock position specified timing characteristics table).
Table ANALOG CONTROL
(3/8)AVDD (5/8)AVDD AVDD complement data LVDS output complement data parallel CMOS output Offset binary data parallel CMOS output Offset binary data LVDS output DESCRIPTION
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
Table MODE ANALOG CONTROL
MODE (3/8)AVDD (5/8)AVDD AVDD DESCRIPTION Internal reference, SPEED mode disabled (for MSPS) External reference, SPEED mode disabled (for MSPS) External reference, SPEED mode enabled (for MSPS) Internal reference, SPEED mode enabled (for MSPS)
AVDD (5/8) AVDD (5/8) AVDD
(3/8) AVDD
AVDD
(3/8) AVDD Parallel
S0321-0
Figure Simple Scheme Configure Parallel Pins SCLK
SERIAL INTERFACE
internal registers, which accessed serial interface formed pins (Serial interface Enable), SCLK (Serial Interface Clock) SDATA (Serial Interface Data). Serial shift bits into device enabled when low. Serial data SDATA latched every falling edge SCLK when active (low). serial data loaded into register every 16th SCLK falling edge when low. case word length exceeds multiple bits, excess bits ignored. Data loaded multiple 16-bit words within single active pulse. first bits form register address remaining bits register data. interface work with SCLK frequency from down very speeds (few Hertz) also with non-50% SCLK duty cycle. Register Initialization After power-up, internal registers MUST initialized their default values. This done ways: Either through hardware reset applying high-going pulse RESET width greater than 10ns) shown Figure applying software reset. Using serial interface, <RESET> register 0x00) HIGH. This initializes internal registers their default values then self-resets <RESET> LOW. this case RESET kept LOW.
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
Register Address
Register Data
SDATA
t(DH)
t(SCLK)
t(DSU)
SCLK
t(SLOADS)
t(SLOADH)
RESET
T0109-0
Figure Serial Interface Timing
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values 25°C, values across full temperature range TMIN -40°C TMAX 85°C, AVDD 3.3V, DRVDD 1.8V, unless otherwise noted.
PARAMETER fSCLK tSLOADS tSLOADH SCLK frequency tSCLK) SCLK setup time SCLK hold time SDATA setup time SDATA hold time UNIT
SERIAL REGISTER READOUT
device includes option where contents internal registers read back. This useful diagnostic check verify serial interface communication between external controller ADC. First, register <SERIAL READOUT> This also disables further writes into registers (EXCEPT register <SERIAL READOUT> itself). Initiate serial interface cycle specifying address register (A7-A0) whose content read. device outputs contents (D7-D0) selected register OVR_SDOUT pin. external controller latch contents falling edge SCLK. enable register writes, reset register <SERIAL READOUT>
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
Enable serial readout (<SERIAL READOUT>
Register Address (A7:A0) 0x00
Register Data (D7:D0)
SDATA
SCLK
OVR_SDOUT
OVR_SDOUT functions (<SERIAL READOUT>
Read contents register 0x3F. This register been initialized with 0x04 (device global power down mode)
Register Address (A7:A0) 0x3F
Register Data (D7:D0) (Don't Care)
SDATA
SCLK
OVR_SDOUT
OVR_SDOUT functions serial readout (<SERIAL READOUT>
T0386-0
Figure Serial Readout
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
RESET TIMING
Typical values 25°C, values across full temperature range TMIN -40°C TMAX 85°C, unless otherwise noted.
PARAMETER Power-on delay Reset pulse width TEST CONDITIONS Delay from power-up AVDD DRVDD RESET pulse active Pulse width active RESET signal that will reset serial registers Delay from RESET disable active
Power Supply AVDD, DRVDD
UNIT
RESET
T0108-0
Figure Reset Timing Diagram
SERIAL REGISTER
Table Summary Functions Supported Serial Interface
REGISTER ADDRESS A7-A0 <RESET> Software Reset REGISTER FUNCTIONS <ENABLE SPEED MODE> <PDN GLOBAL> <SERIAL READOUT> <PDN OBUF>
REF> Internal external reference <LVDS CMOS> Output interface
<STANDBY>
<CLKOUT POSN> Output clock position control
<DATA FORMAT> complement offset binary CUSTOM PATTERN HIGH>
<CUSTOM PATTERN LOW> ENABLE OFFSET CORR> <FINE GAIN
<OFFSET CORR TIME CONSTANT> Offset correction time constant TEST PATTERNS> PROGRAM OFFSET PEDESTAL
Multiple functions register programmed single write operation.
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
DESCRIPTION SERIAL REGISTERS
A7-A0 <RESET> Software Reset <SERIA READO
<RESET> Software reset applied resets internal registers self-clears <SERIAL READOUT> Serial readout disabled Serial readout enabled, OVR_SDOUT functions serial data readout.
A7-A0 <ENABLE SPEED MODE>
<ENABLE SPEED MODE> SPEED mode disabled. sampling frequency MSPS Enable SPEED mode sampling frequencies MSPS.
A7-A0 D6,D5 <REF> <PDN GLOBAL> <STANDBY> <PDN OBUF>
<PDN OBUF> Power down output buffer Output buffer enabled Output buffer powered down <STANDBY> Normal operation alone powered down. Internal references, output buffers active. Quick wake-up time <PDN GLOBAL> Normal operation Total power down ADC, internal references output buffers powered down. Slow wake-up time. <REF> Internal external reference selection MODE controls reference selection Internal reference enabled External reference enabled
A7-A0 D7,D6 <LVDS CMOS> <LVDS CMOS> controls LVDS CMOS interface selection LVDS interface Parallel CMOS interface
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
A7-A0 LVDS Interface D7-D5 D4-D2 <CLKOUT POSN> Output clock rising edge position Default output clock position (refer timing specification table) Default output clock position (refer timing specification table) Rising edge shifted (4/26)Ts Rising edge aligned with data transition Rising edge shifted (4/26)Ts <CLKOUT POSN> Output clock falling edge position Default output clock position (refer timing specification table) Default output clock position (refer timing specification table) Falling edge shifted (4/26)Ts Falling edge aligned with data transition Falling edge shifted (4/26)Ts <CLKOUT POSN> Output clock position control
CMOS Interface D7-D5 D4-D2 <CLKOUT POSN> Output clock rising edge position Default output clock position (refer timing specification table) Default output clock position (refer timing specification table) Rising edge shifted (4/26)Ts Rising edge shifted (6/26)Ts Rising edge aligned with data transition <CLKOUT POSN> Output clock falling edge position Default output clock position (refer timing specification table) Default output clock position (refer timing specification table) Falling edge shifted (4/26)Ts Falling edge shifted (6/26)Ts Falling edge aligned with data transition
A7-A0 D2,D1 <DATA FORMAT> controls data format selection complement Offset binary <DATA FORMAT> complement offset binary
A7-A0 D7-D0 <CUSTOM LOW> lower bits custom pattern available output instead data. D5-D0 <CUSTOM HIGH> upper bits custom pattern available output instead data <Custom Pattern> <Custom Pattern>
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
A7-A0 <ENABLE OFFSET CORR> Offset correction disabled Offset correction enabled <ENABLE OFFSET CORR> Offset correction enable
A7-A0 <OFFSET CORR Offset correction time constant
<FINE GAIN>
D3-D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 D7-D4 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100
<OFFSET CORR Time constant correction loop number clock cycles. "Offset Correction" application section. <FINE GAIN> Gain programmability steps gain, default after reset gain gain gain gain gain gain gain gain gain gain gain gain
1100 1111 RESERVED
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
A7-A0 D2-D0 <TEST PATTERNS>
<TEST PATTERNS> Test Patterns verify data capture Normal operation Outputs zeros Outputs ones Outputs toggle pattern Outputs digital ramp Outputs custom pattern Unused Unused
A7-A0 D5-D0 <OFFSET PEDESTAL>
<OFFSET PEDESTAL> When offset correction enabled, final converged value after offset corrected will mid-code value. pedestal added final converged value programming these bits. example, "Offset COrrection" application section.
011111 011110 011101 000000 111111 111110 100000
Mid-code Mid-code Mid-code Mid-code Mid-code Mid-code Mid-code
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
DEVICE INFORMATION
D12_D13_M D10_D11_M D12_D13_P D10_D11_P D8_D9_M D6_D7_M D2_D3_M
D4_D5_M
D8_D9_P
D4_D5_P
D6_D7_P
DRGND DRVDD OVR_SDOUT CLKOUCLKOUTP AVDD AGND CLKP CLKM AGND
D2_D3_P
DRGND DRVDD D0_D1_P D0_D1_M RESET SCLK SDATA AVDD AGND
connected DRGND
Thermal
MODE
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
P0023-12
Figure CONFIGURATION (LVDS MODE) ADS6149/48
D10_D11_M D10_D11_P
D8_D9_M
D4_D5_M
DRGND DRVDD OVR_SDOUT CLKOUCLKOUTP AVDD AGND CLKP CLKM AGND
D0_D1_M
D6_D7_M
D2_D3_M
D8_D9_P
D2_D3_P
D4_D5_P
D6_D7_P
D0_D1_P
DRGND DRVDD RESET SCLK SDATA AVDD AGND
connected DRGND
Thermal
MODE
AGND
AGND
AVDD
AVDD
AVDD
AGND
AVDD
P0023-13
Figure CONFIGURATION (LVDS MODE) ADS6129/28
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
Table ASSIGNMENTS (LVDS MODE) ADS6149/48 ADS6129/28
NAME AVDD AGND CLKP, CLKM INP, PINS 3.3-V Analog power supply Analog ground Differential clock input Differential analog input Internal reference mode Common-mode voltage output. DESCRIPTION
External reference mode Reference input. voltage forced this sets internal references
Serial interface RESET input.
RESET
When using serial interface mode, user MUST initialize internal registers through hardware RESET applying high-going pulse this using software reset option. Refer SERIAL INTERFACE section. parallel interface mode, user RESET permanently HIGH. (SDATA used parallel controls this mode) internal pull-down resistor.
Serial interface clock input. internal pull-down resistor. This functions serial interface data input when RESET LOW. functions power down control when RESET tied high.
SCLK
SDATA
Table detailed information. internal pull-down resistor.
This functions serial interface enable input when RESET low.
functions output clock edge control when RESET tied high. Table detailed information. internal pull-up resistor AVDD.
Output buffer enable input, active high. internal pull-up resistor DRVDD Data Format Select input. This sets DATA FORMAT complement Offset binary) LVDS/CMOS output interface type.
Table detailed information.
MODE
Internal external reference selection speed mode control. control. Table detailed information. Differential output clock, true Differential output clock, complement Differential output data multiplexed, true Differential output data multiplexed, complement Differential output data multiplexed, true Differential output data multiplexed, complement Differential output data multiplexed, true Differential output data multiplexed, complement Differential output data multiplexed, true Differential output data multiplexed, complement Differential output data multiplexed, true Differential output data multiplexed, complement Differential output data multiplexed, true Differential output data multiplexed, complement Differential output data multiplexed, true Differential output data multiplexed, complement CMOS output with logic levels determined DRVDD supply. functions out-of-range indicator after reset when register <SERIAL READOUT> functions serial register readout when register <SERIAL READOUT>
CLKOUTP CLKOUD0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M D12_D13_P D12_D13_M OVR_SDOUT
Figure Figure
next generation pin-compatible family, MODE will converted digital control certain reserved functions. selection internal external reference speed functions will supported using MODE. system board using ADS61x9/x8, MODE routed digital controller. This will avoid board modification while migrating next generation ADC. Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
Table ASSIGNMENTS (LVDS MODE) ADS6149/48 ADS6129/28 (continued)
NAME DRVDD DRGND Figure Figure PINS Digital output buffer supply Digital output buffer ground DESCRIPTION
connect
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
DRGND DRVDD OVR_SDOUT UNUSED CLKOUT AVDD AGND CLKP CLKM AGND
DRGND DRVDD RESET SCLK SDATA AVDD AGND
connected DRGND
Thermal
MODE
AGND
AGND
AVDD
AVDD
AVDD
AGND
AVDD
P0023-14
Figure CONFIGURATION (CMOS MODE) ADS6149/48
DRGND DRVDD OVR_SDOUT UNUSED CLKOUT AVDD AGND CLKP CLKM AGND
DRGND DRVDD RESET SCLK SDATA AVDD AGND
connected DRGND
Thermal
MODE
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
P0023-15
Figure CONFIGURATION (CMOS MODE) ADS6129/28
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
ASSIGNMENTS (CMOS MODE) ADS6149/48 ADS6129/28
NAME AVDD AGND CLKP, CLKM INP, PINS 3.3-V Analog power supply Analog ground Differential clock input Differential analog input Internal reference mode Common-mode voltage output. External reference mode Reference input. voltage forced this sets internal references Serial interface RESET input. When using serial interface mode, user MUST initialize internal registers through hardware RESET applying high-going pulse this using software reset option. Refer SERIAL INTERFACE section. parallel interface mode, user RESET permanently HIGH. (SDATA used parallel controls this mode) internal pull-down resistor. Serial interface clock input. internal pull-down resistor. This functions serial interface data input when RESET LOW. functions power down control when RESET tied high. Table detailed information. internal pull-down resistor. This functions serial interface enable input when RESET low. functions output clock edge control when RESET tied high. Table detailed information. internal pull-up resistor DVDD. Data Format Select input. This sets DATA FORMAT complement Offset binary) LVDS/CMOS output interface type. Table detailed information. Internal external reference selection control speed mode control. Table detailed information. CMOS output clock Output buffer enable input, active high. internal pull-up resistor DRVDD Differential output clock, complement bit/12 CMOS output data CMOS output with logic levels determined DRVDD supply. functions out-of-range indicator after reset when register <SERIAL READOUT> functions serial register readout when <SERIAL READOUT> Digital output buffer supply Digital output buffer ground Unused CMOS mode connect DESCRIPTION
RESET
SCLK
SDATA
MODE CLKOUT CLKOUD0-D13
Figure Figure Figure Figure
14/12
OVR_SDOUT DRVDD DRGND UNUSED
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
TYPICAL CHARACTERISTICS ADS6149
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
INPUT SIGNAL
Amplitude -100 -120 -140 -160
INPUT SIGNAL
Amplitude -100 -120 -140 -160
G002
SFDR 94.6 SINAD 73.3 dBFS 73.4 dBFS 90.2
SFDR 87.7 SINAD 72.7 dBFS dBFS
Frequency
Frequency
Figure INPUT SIGNAL
Amplitude -100 -120 -140 -160
G003
Figure INPUT SIGNAL
Amplitude -100 -120 -140 -160
G004
SFDR 81.8 SINAD 70.8 dBFS 71.3 dBFS 79.7
SFDR 76.3 SINAD 68.1 dBFS 69.1 dBFS 73.8
Frequency
Frequency
Figure 2-TONE INPUT SIGNAL (IMD)
Amplitude -100 -120 -140 -160
G005
Figure 2-TONE INPUT SIGNAL (IMD)
Amplitude -100 -120 -140 -160
G006
fIN1 185.1 MHz, dBFS fIN2 190.1 MHz, dBFS 2-Tone -90.6 dBFS SFDR dBFS
fIN1 185.1 MHz, dBFS fIN2 190.1 MHz, dBFS 2-Tone -105 dBFS SFDR -103 dBFS
Frequency
Frequency
Figure
Figure
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
TYPICAL CHARACTERISTICS ADS6149 (continued)
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
SFDR INPUT FREQUENCY
SFDR Input Frequency
G007
INPUT FREQUENCY
LVDS dBFS
Input Frequency
G008
LVDS
CMOS
CMOS
Figure SFDR GAIN
SFDR Input Frequency
G009
Figure SINAD GAIN
SINAD dBFS Input Frequency
G010
Input adjusted -1dBFS input
Input adjusted -1dBFS input
Figure
Figure
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
TYPICAL CHARACTERISTICS ADS6149 (continued)
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
PERFORMANCE INPUT AMPLITUDE
SFDR dBc, dBFS SFDR (dBc) (dBFS) SFDR (dBFS) dBFS
PERFORMANCE INPUT COMMON-MODE VOLTAGE
SFDR SFDR dBFS
G012 G014
1.35
1.40
1.45
1.50
1.55
1.60
1.65
Input Amplitude dBFS
Common-Mode Voltage Analog Inputs
Figure PERFORMANCE AVDD SUPPLY
SFDR SFDR
G013
Figure PERFORMANCE DRVDD SUPPLY
dBFS SFDR 60.1 AVDD SFDR dBFS
60.1 DRVDD
AVDD Supply Voltage
DRVDD Supply Voltage
Figure
Figure
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
TYPICAL CHARACTERISTICS ADS6149 (continued)
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
PERFORMANCE TEMPERATURE
G015
PERFORMANCE INPUT CLOCK AMPLITUDE
SFDR dBFS 0.20 0.70 1.20 1.70 2.20 2.70
G016
Input Clock Amplitude dBFS
G018
SFDR
Temperature
Figure PERFORMANCE INPUT CLOCK DUTY CYCLE
SFDR dBFS SFDR
SFDR
SFDR
SFDR
Figure PERFORMANCE VOLTAGE
External Reference Mode SFDR dBFS
Input Clock Duty Cycle
1.30
G017
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
VVCM Voltage
Figure OUTPUT NOISE HISTOGRAM
(LSB) 0.995 Occurence 8203 8204 8205 8206 8207 8208 8209 8210 8211 8212 Output Code
G019
Figure
Figure
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
TYPICAL CHARACTERISTICS ADS6148
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
INPUT SIGNAL
Amplitude -100 -120 -140 -160
G020
INPUT SIGNAL
Amplitude -100 -120 -140 -160
SFDR 90.75 SINAD 73.13 dBFS 73.25 dBFS 87.76
SFDR 92.3 SINAD 72.9 dBFS dBFS
Frequency
Frequency
Figure INPUT SIGNAL
Amplitude -100 -120 -140 -160
G022
Figure INPUT SIGNAL
SFDR 82.44 SINAD 70.81 dBFS 71.17 dBFS 80.89
Amplitude -100 -120 -140 -160
SFDR 76.3 SINAD 68.5 dBFS 69.3 dBFS 75.1
G023
Frequency
Frequency
Figure 2-TONE INPUT SIGNAL (IMD)
Amplitude -100 -120 -140 -160
G024
Figure 2-TONE INPUT SIGNAL (IMD)
Amplitude -100 -120 -140 -160
G025
fIN1 185.1 MHz, dBFS fIN2 190.1 MHz, dBFS 2-Tone dBFS SFDR dBFS
fIN1 185.1 MHz, dBFS fIN2 190.1 MHz, dBFS 2-Tone -101 dBFS SFDR dBFS
Frequency
Frequency
Figure
Figure
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
TYPICAL CHARACTERISTICS ADS6148 (continued)
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
SFDR INPUT FREQUENCY
SFDR Input Frequency
G026
INPUT FREQUENCY
LVDS dBFS
Input Frequency
G027
LVDS
CMOS
CMOS
Figure SFDR GAIN
SFDR Input Frequency
G028
Figure SINAD GAIN
SINAD dBFS Input Frequency
G029
Input adjusted -1dBFS input
Input adjusted -1dBFS input
Figure
Figure
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
TYPICAL CHARACTERISTICS ADS6148 (continued)
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
PERFORMANCE INPUT AMPLITUDE
SFDR dBc, dBFS SFDR (dBc)
G030
PERFORMANCE INPUT COMMON-MODE VOLTAGE
60.1
SFDR (dBFS)
dBFS
SFDR SFDR
dBFS
G03G033
(dBFS)
1.35
1.40
1.45
1.50
1.55
1.60
1.65
Input Amplitude dBFS
Common-Mode Voltage Analog Inputs
Figure PERFORMANCE AVDD SUPPLY
SFDR 60.1 DRVDD SFDR dBFS
G032
Figure PERFORMANCE DRVDD SUPPLY
SFDR 60.1 AVDD SFDR dBFS
AVDD Supply Voltage
DRVDD Supply Voltage
Figure
Figure
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
TYPICAL CHARACTERISTICS ADS6148 (continued)
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
PERFORMANCE TEMPERATURE
60.1
G034
PERFORMANCE INPUT CLOCK AMPLITUDE
dBFS 0.70 1.20 1.70 2.20
G035
SFDR
0.20
Temperature
Input Clock Amplitude
Figure PERFORMANCE INPUT CLOCK DUTY CYCLE
G036
Figure PERFORMANCE VOLTAGE
60.1 External Reference Mode
dBFS
dBFS
G037
SFDR
SFDR
SFDR
SFDR
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
Input Clock Duty Cycle
VVCM Voltage
Figure OUTPUT NOISE HISTOGRAM
(LSB) Occurence 8203 8204 8205 8206 8207 8208 8209 8210 8211 8212 Output Code
G038
Figure
Figure
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
dBFS
SFDR SFDR
SFDR
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
TYPICAL CHARACTERISTICS ADS6129
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
INPUT SIGNAL
Amplitude -100 -120 -140 -160
G039
INPUT SIGNAL
Amplitude -100 -120 -140 -160
G040
SFDR 94.87 SINAD 70.73 dBFS 70.77 dBFS 89.9
SFDR 87.8 SINAD 70.5 dBFS 70.6 dBFS
Frequency
Frequency
Figure INPUT SIGNAL
Amplitude -100 -120 -140 -160
Figure INPUT SIGNAL
Amplitude -100 -120 -140 -160
G042
SFDR 81.9 SINAD 69.2 dBFS 69.5 dBFS 79.7
SFDR 76.09 SINAD 67.13 dBFS 67.95 dBFS 73.72
Frequency
Frequency
Figure 2-TONE INPUT SIGNAL (IMD)
Amplitude -100 -120 -140 -160
G043
Figure 2-TONE INPUT SIGNAL (IMD)
Amplitude -100 -120 -140 -160
G044
fIN1 185.1 MHz, dBFS fIN2 190.1 MHz, dBFS 2-Tone -90.5 dBFS SFDR dBFS
fIN1 185.1 MHz, dBFS fIN2 190.1 MHz, dBFS 2-Tone -103 dBFS SFDR dBFS
Frequency
Frequency
Figure
Figure
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
TYPICAL CHARACTERISTICS ADS6129 (continued)
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
SFDR INPUT FREQUENCY
SFDR Input Frequency
G045
INPUT FREQUENCY
LVDS dBFS
Input Frequency
G046
CMOS
LVDS
CMOS
Figure SFDR GAIN
SFDR Input Frequency
G047
Figure SINAD GAIN
SINAD dBFS Input Frequency
G048
Input adjusted -1dBFS input
Input adjusted -1dBFS input
Figure
Figure
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
TYPICAL CHARACTERISTICS ADS6129 (continued)
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
PERFORMANCE INPUT AMPLITUDE
SFDR dBc, dBFS SFDR (dBc)
G049
PERFORMANCE INPUT COMMON-MODE VOLTAGE
dBFS SFDR SFDR dBFS
G050 G052
SFDR (dBFS)
(dBFS)
1.35
1.40
1.45
1.50
1.55
1.60
1.65
Input Amplitude dBFS
Common-Mode Voltage Analog Inputs
Figure PERFORMANCE AVDD SUPPLY
SFDR SFDR
Figure PERFORMANCE DRVDD SUPPLY
60.1 AVDD SFDR dBFS
60.1 DRVDD
dBFS
SFDR
AVDD Supply Voltage
DRVDD Supply Voltage
Figure
Figure
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
TYPICAL CHARACTERISTICS ADS6129 (continued)
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
PERFORMANCE TEMPERATURE
G053
PERFORMANCE INPUT CLOCK AMPLITUDE
SFDR dBFS 0.20 0.70 1.20 1.70 2.20 2.70
G054
Input Clock Amplitude dBFS
G056
SFDR
Temperature
Figure PERFORMANCE INPUT CLOCK DUTY CYCLE
G055
SFDR
SFDR
Figure PERFORMANCE VOLTAGE
60.1 External Reference Mode dBFS SFDR SFDR dBFS
SFDR
SFDR
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
Input Clock Duty Cycle
VVCM Voltage
Figure OUTPUT NOISE HISTOGRAM
Occurence 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 Output Code
G057
Figure
Figure
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
TYPICAL CHARACTERISTICS ADS6128
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
INPUT SIGNAL
Amplitude -100 -120 -140 -160
G058
INPUT SIGNAL
Amplitude -100 -120 -140 -160
G059
SFDR 90.8 SINAD 70.6 dBFS 70.7 dBFS 87.8
SFDR 92.5 SINAD 70.5 dBFS 70.6 dBFS 88.9
Frequency
Frequency
Figure INPUT SIGNAL
Amplitude -100 -120 -140 -160
G060
Figure INPUT SIGNAL
SFDR 82.59 SINAD 69.18 dBFS 69.42 dBFS 80.99
Amplitude -100 -120 -140 -160
SFDR 76.3 SINAD 67.5 dBFS 68.1 dBFS 75.1
Frequency
Frequency
Figure 2-TONE INPUT SIGNAL (IMD)
Amplitude -100 -120 -140 -160
G062
Figure 2-TONE INPUT SIGNAL (IMD)
Amplitude -100 -120 -140 -160
G063
fIN1 185.1 MHz, dBFS fIN2 190.1 MHz, dBFS 2-Tone dBFS SFDR dBFS
fIN1 185.1 MHz, dBFS fIN2 190.1 MHz, dBFS 2-Tone -101 dBFS SFDR dBFS
Frequency
Frequency
Figure
Figure
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
TYPICAL CHARACTERISTICS ADS6128 (continued)
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
SFDR INPUT FREQUENCY
SFDR Input Frequency
G064
INPUT FREQUENCY
LVDS dBFS
Input Frequency
G065
CMOS
LVDS
CMOS
Figure SFDR GAIN
SFDR Input Frequency
G066
Figure SINAD GAIN
SINAD dBFS Input Frequency
G067
Input adjusted -1dBFS input
Input adjusted -1dBFS input
Figure
Figure
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
TYPICAL CHARACTERISTICS ADS6128 (continued)
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
PERFORMANCE INPUT AMPLITUDE
SFDR dBc, dBFS SFDR (dBc)
G068
PERFORMANCE INPUT COMMON-MODE VOLTAGE
dBFS SFDR SFDR dBFS
G069
SFDR (dBFS)
(dBFS)
1.35
1.40
1.45
1.50
1.55
1.60
1.65
Input Amplitude dBFS
Common-Mode Voltage Analog Inputs
Figure PERFORMANCE AVDD SUPPLY
SFDR
G070
Figure PERFORMANCE DRVDD SUPPLY
dBFS
60.1 AVDD SFDR
60.1 DRVDD SFDR
AVDD Supply Voltage
DRVDD Supply Voltage
Figure
Figure
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
dBFS
SFDR
ADS6149/ADS6129 ADS6148/ADS6128
TYPICAL CHARACTERISTICS ADS6128 (continued)
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
PERFORMANCE TEMPERATURE
60.1 SFDR
G072
PERFORMANCE INPUT CLOCK AMPLITUDE
dBFS SFDR SFDR 0.20 0.70 1.20 1.70 2.20
G073
Input Clock Amplitude dBFS
G075
SFDR
Temperature
Figure PERFORMANCE INPUT CLOCK DUTY CYCLE
G074
Figure PERFORMANCE VOLTAGE
60.1 External Reference Mode dBFS SFDR SFDR dBFS
SFDR
SFDR
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
Input Clock Duty Cycle
VVCM Voltage
Figure OUTPUT NOISE HISTOGRAM
Occurence 2048 2049 2050 2051 2052 2053 2054 2055 2056 Output Code
G076
Figure
Figure
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
TYPICAL CHARACTERISTICS COMMON PLOTS
plots 25°C, AVDD DRVDD maximum rated sampling frequency, sine wave input clock. differential clock amplitude, clock duty cycle, DBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
CMRR INPUT FREQUENCY
Total Power CMRR -100
G079
TOTAL POWER SAMPLING FREQUENCY
G077
LVDS
CMOS
Input Frequency
Sampling Frequency MSPS
Figure DRVDD CURRENT SAMPLING FREQUENCY
IDRVDD DRVDD Current
G078
Figure
LVDS
CMOS Disabled
Sampling Frequency MSPS
Figure
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
CONTOUR PLOTS ADS6149/ADS6148/ADS6129/ADS6128
Plots 25°C, AVDD 3.3V, DRVDD sine wave input clock, differential clock amplitude, clock duty cycle, dBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
Sampling Frequency MSPS
Input Frequency
SFDR
M0049-17
Figure SFDR Contour Plot gain)
Sampling Frequency MSPS
Input Frequency
SFDR
M0049-18
Figure SFDR Contour Plot gain)
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
CONTOUR PLOTS ADS6149/ADS6148
Plots 25°C, AVDD 3.3V, DRVDD sine wave input clock, differential clock amplitude, clock duty cycle, dBFS differential analog input, internal reference mode, gain, LVDS output interface (unless otherwise noted)
Sampling Frequency MSPS
Input Frequency
dBFS
M0048-19
Figure Contour Plot gain)
Sampling Frequency MSPS
Input Frequency
dBFS
M0048-20
Figure Contour Plot gain)
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
APPLICATION INFORMATION THEORY OPERATION
ADS6149/48 ADS6129/28 family high performance, power 14-bit 12-bit converters with maximum sampling rates MSPS. conversion process initiated falling edge external input clock analog input signal sampled. sampled signal sequentially converted series small resolution stages, with outputs combined digital correction logic block. every clock edge sample propagates through pipeline resulting data latency clock cycles. output available 14-bit/12-bit data, LVDS CMOS coded either straight offset binary binary complement format.
ANALOG INPUT
analog input consists switched-capacitor based differential sample hold architecture. This differential topology results very good performance even high input frequencies high sampling rates. pins have externally biased around common-mode voltage 1.5V, available pin. full-scale differential input, each input INP, swing symmetrically between 0.5V 0.5V, resulting 2Vpp differential input swing.
Sampling switch Lpkg~1 Cbond Resr Cpar1 0.25 Csamp Cpar2 Csamp Sampling capacitor
Filter
Lpkg~1 Cbond Resr
Cpar2 Sampling switch
Sampling capacitor
Figure Analog Input Equivalent Circuit input sampling circuit high 3-dB bandwidth that extends (measured from input pins sampled voltage).
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
Drive Circuit Requirements optimum performance, analog inputs must driven differentially. This improves common-mode noise immunity even order harmonic rejection. resistor series with each input recommended damp ringing caused package parasitics. also necessary present impedance common mode switching currents. This achieved using resistors from each input terminated common mode voltage (VCM). Note that device includes internal filter from each input ground. purpose this filter absorb glitches caused opening closing sampling capacitors. cut-off frequency filter involves trade-off. lower cut-off frequency (larger absorbs glitches better, also reduces input bandwidth maximum input frequency that supported. other hand, with internal filter, high input frequency supported, sampling glitches need supplied external driving circuit. This limitations presence package bond-wire inductance. ADS61x9/x8, component values have been optimized while supporting high input bandwidth MHz). However, applications where very high input frequency support required, filtering glitches improved further using external R-C-R filter shown Figure Figure 100). addition above, drive circuit have designed provide insertion loss over desired frequency range matched impedance source. While doing this, input impedance must considered. Figure Figure show impedance (Zin Cin) looking into input pins.
Resistance
0.01 1000 Frequency
Figure Analog Input Resistance (Rin) Across Frequency
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
Capacitance
1000 Frequency
Figure Analog Input Capacitance (Cin) Across Frequency Driving Circuit example driving circuit configurations shown Figure Figure optimized bandwidth (low input frequencies) other high bandwidth support higher input frequencies. Figure external R-C-R filter using 22pF been used. Together with series inductor (39nH), this combination forms filter absorbs sampling glitches. large capacitor (22pF) R-C-R resistors series with each input pin, this drive circuit bandwidth suited input frequencies. support high input frequencies (see Figure 99), capacitance used R-C-R reduced 3.3pF series inductors shorted out. Together with lower series resistors this drive circuit provides high bandwidth supports high input frequencies. Note that both drive circuits have been terminated near side. termination accomplished resistor from each input 1.5V common-mode (VCM) from device. This biases analog inputs around required common-mode voltage.
Figure Drive Circuit with Bandwidth (for input frequencies)
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
mismatch transformer parasitic capacitance (between windings) results degraded even-order harmonic performance. Connecting identical transformers back back helps minimize this mismatch good performance obtained high frequency input signals. additional termination resistor pair required between transformers shown figures. center point this termination connected ground improve balance between sides. values terminations between transformers secondary side have chosen effective case source impedance).
Figure 100. Drive Circuit with High Bandwidth (for high input frequencies) Input Common-Mode ensure low-noise common-mode reference, filtered with 0.1µF low-inductance capacitor connected ground. designed directly drive inputs. input stage sinks common-mode current order (per input pin, MSPS). Equation describes dependency common-mode current sampling frequency. MSPS This equation helps design output capability impedance driving circuit accordingly.
REFERENCE
ADS614X/2X built-in internal references REFP REFM, requiring external components. Design schemes used linearize converter load seen references; this on-chip integration requisite reference capacitors eliminates need external decoupling. full-scale input range converter controlled external reference mode explained below. internal external reference modes selected programming serial interface register <REF>.
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
INTREF Internal Reference
INTREF
EXTREF REFM
REFP
S0165-09
Figure 101. Reference Section Internal Reference When device internal reference mode, REFP REFM voltages generated internally. Common-mode voltage (1.5V nominal) output pin, which used externally bias analog input pins. External Reference When device external reference mode, acts reference input pin. voltage forced buffered gained 1.33 internally, generating REFP REFM voltages. differential input voltage corresponding full-scale given Equation
Full-scale differential input (Voltage forced VCM) 1.33
this mode, 1.5V common-mode voltage bias input pins generated externally.
CLOCK INPUT
ADS614X/2X clock inputs driven differentially (sine, LVPECL LVDS) single-ended (LVCMOS), with little difference performance between them. common-mode voltage clock inputs using internal resistors. This allows using transformer-coupled drive circuits sine wave clock ac-coupling LVPECL, LVDS clock sources.
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
CLKP
CLKM
S0166-07
Figure 102. Internal Clock Buffer Single-ended CMOS clock ac-coupled CLKP input, with CLKM connected ground with 0.1-µF capacitor, shown Figure 104. best performance, clock inputs have driven differentially, reducing susceptibility common-mode noise. high input frequency sampling, recommended clock source with very jitter. Band-pass filtering clock source help reduce effect jitter. There change performance with non-50% duty cycle clock input.
CLKP
CMOS Clock Input CLKP
Differential Sine-Wave PECL LVDS Clock Input CLKM
CLKM
S0167-10
S0168-14
Figure 103. Differential Clock Driving Circuit
Figure 104. Single-Ended Clock Driving Circuit
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
FINE GAIN CONTROL
ADS614X/2X includes gain settings that used improved SFDR performance (compared gain). gain programmable from steps). each gain setting, analog input full-scale range scales proportionally, shown Table SFDR improvement achieved expense SNR; each gain setting, degrades about 0.5-1dB. degradation less high input frequencies. result, fine gain useful high input frequencies SFDR improvement significant with marginal degradation SNR. fine gain used trade-off between SFDR SNR. Note that default gain after reset Table Full-Scale Range Across Gains
Gain, Fine, programmable Type Default after reset Full-Scale, 1.78 1.59 1.42 1.26 1.12 1.00
OFFSET CORRECTION
ADS61x9/x8 internal offset correction algorithm that estimates corrects offset ±10mV. correction enabled using serial register <ENABLE OFFSET CORR>. Once enabled, algorithm estimates channel offset applies correction every clock cycle. time constant correction loop function sampling clock frequency. time constant controlled using register bits <OFFSET CORR TIME CONSTANT> described inTable After offset estimated, correction locked setting <OFFSET CORR TIME CONSTANT> Once locked, last estimated value used offset correction every clock cycle. Note that offset correction disabled default after reset. Figure shows time response offset correction algorithm, after enabled. Table Time Constant Offset Correction Algorithm
<OFFSET CORR TIME CONSTANT> D3-D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 111Copyright 2008, Texas Instruments Incorporated
Time constant (TCCLK), number clock cycles RESERVED RESERVED RESERVED RESERVED
Time constant, (=TCCLK 1/Fs) Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
8204 8200 8196 8192 8188 8184 Code 8180 8176 8172 8168 8164 8160 8156 8152 8148
G080
Offset Correction Disabled
Offset Correction Enabled
Output Data With Offset Corrected
Output Data With Offset
Time
Figure 105. Output Code Time Response With Offset Correction Enabled
POWER DOWN
ADS614X/2X three power down modes power down global, standby output buffer disable. Power Down Global this mode, entire chip including converter, internal reference output buffers powered down resulting reduced total power dissipation about output buffers high impedance state. wake-up time from global power down data becoming valid normal mode typically This controlled using register <PDN GLOBAL> using SDATA parallel configuration mode). Standby Here, only converter powered down internal references active, resulting fast wake-up time total power dissipation standby about This controlled using register <STANDBY>. Output Buffer Disable output buffers disabled high impedance state wakeup time from this mode fast, about This controlled using register <PDN OBUF>. Input Clock Stop addition above, converter enters low-power mode when input clock frequency falls below MSPS. power dissipation about
POWER SUPPLY SEQUENCE
During power-up, AVDD DRVDD supplies come sequence. supplies separated device. Externally, they driven from separate supplies from single supply.
DIGITAL OUTPUT INFORMATION
ADS614X/2X provides 14-bit/12-bit data output clock synchronized with data.
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
Output Interface output interface options available Double Data Rate (DDR) LVDS parallel CMOS. They selected using serial interface register <ODI> using parallel configuration mode. LVDS Outputs this mode, data bits clock output using LVDS (Low Voltage Differential Signal) levels. data bits multiplexed output each LVDS differential pair.
Pins CLKOUTP CLKOUD0_D1_P D0_D1_M
LVDS Buffers
Pins CLKOUTP CLKOU
Output Clock
Output Clock
Data bits DLVDS Buffers
D0_D1_P D0_D1_M D2_D3_ D2_D3_M D4_D5_P D4_D5_M
data
Data bits
D2_D3_P D2_D3_M D4_D5_P D4_D5_M D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M D12_D13_P D12_D13_M
Data bits Data bits
Data bits
Data bits
data
D6_D7_P
Data bits
D6_D7_M D8_D9_P
Data bits
Data bits
D8_D9_M D10_D11_P
Data bits
Data bits D10,
D10_D11_M
Data bits D10,
Data bits D12,
ADS612X
Figure 106. 14-Bit LVDS Outputs
Figure 107. 12-Bit LVDS Outputs
Even data bits output falling edge CLKOUTP data bits output rising edge CLKOUTP. Both rising falling edges CLKOUTP have used capture data bits (see Figure 108).
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
CLKOUTP CLKOU
D0_D1_P, D0_D1_M D2_D3_P, D2_D3_M D4_D5_P, D4_D5_M D6_D7_P, D6_D7_M D8_D9_P, D8_D9_M D10_D11_P, D10_D11_M D12_D13_P, D12_D13_M
Sample
Sample N+T0110-0
Figure 108. LVDS Interface LVDS Buffer equivalent circuit each LVDS output buffer shown Figure 109. buffer designed present output impedance (Rout). differential outputs terminated receive termination. buffer output impedance behaves like source-side series termination. absorbing reflections from receiver end, helps improve signal integrity. Note that this internal termination cannot disabled value cannot changed.
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/48/29/28
High
0.35
OUTP
External 100-W Load
-0.35
Switch impedance nominally (±10%)
When High switches closed, OUTP 1.375 1.025 When switches closed, OUTP 1.025 1.375 When High Low) switches closed, Rout
S0374-0
Figure 109. LVDS Buffer Equivalent Circuit Parallel CMOS Interface CMOS mode, each data output separate CMOS voltage level, every clock cycle. rising edge output clock CLKOUT used latch data receiver (for sampling frequencies MSPS). MSPS, setup hold timings output data with respect CLKOUT specified. recommended minimize load capacitance seen data clock output pins using short traces receiver. Also, match output data clock traces minimize skew between them. sampling frequencies MSPS, recommended external clock capture data. delay from input clock output data data valid times specified higher sampling frequencies. These timings used delay input clock appropriately capture data (see Figure
High
Rout
OU
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
Pins
OVR_SDOUT
CLKOUT
CMOS Output Buffers
14-Bit Data
ADS614x
Figure 110. CMOS Output Interface Output Buffer Strength Programmability Switching noise (caused CMOS output data transitions) couple into analog inputs during instant sampling degrade SNR. coupling degradation increases output buffer drive made stronger. minimize this, CMOS output buffers designed with controlled drive strength best SNR. default drive strength also ensures wide data stable window load capacitances CMOS Interface Power Dissipation With CMOS outputs, DRVDD current scales with sampling frequency load capacitance every output pin. maximum DRVDD current occurs when each output toggles between every clock cycle. actual application, DRVDD current would determined average number output bits switching, which function sampling frequency nature analog input signal. Digital current CMOS output switching DRVDD FAVG), where load capacitance, FAVG average number output bits switching. Figure shows current across sampling frequencies analog input frequency. Output Data Format output data formats supported complement offset binary. They selected using serial interface register <DATA FORMAT> controlling parallel configuration mode. event input voltage overdrive, digital outputs appropriate full scale level. positive overdrive, output code 0x3FFF offset binary output format, 0x1FFF complement output format. negative input overdrive, output code 0x0000 offset binary output format 0x2000 complement output format.
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
BOARD DESIGN CONSIDERATIONS
Grounding single ground plane sufficient give good performance, provided analog, digital, clock sections board cleanly partitioned. User Guide details layout grounding. Supply Decoupling ADS61x9/x8 already includes internal decoupling, minimal external decoupling used without loss performance. Note that decoupling capacitors help filter external power supply noise, optimum number capacitors would depend actual application. decoupling capacitors should placed very close converter supply pins. Exposed addition providing path heat dissipation, also electrically connected digital ground internally. necessary solder exposed ground plane best thermal electrical performance. detailed information, application notes Layout Guidelines (SLOA122) QFN/SON Attachment (SLUA271).
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
SLWS211A JULY 2008 REVISED SEPTEMBER 2008. www.ti.com
DEFINITION SPECIFICATIONS
Analog Bandwidth analog input frequency which power fundamental reduced with respect frequency value. Aperture Delay delay time between rising edge input sampling clock actual time which sampling occurs. This delay will different across channels. maximum variation specified aperture delay variation (channel-channel). Aperture Uncertainty (Jitter) sample-to-sample variation aperture delay. Clock Pulse Width/Duty Cycle duty cycle clock signal ratio time clock signal remains logic high (clock pulse width) period clock signal. Duty cycle typically expressed percentage. perfect differential sine-wave clock results duty cycle. Maximum Conversion Rate maximum sampling rate which certified operation given. parametric testing performed this sampling rate unless otherwise noted. Minimum Conversion Rate minimum sampling rate which functions. Differential Nonlinearity (DNL) ideal exhibits code transitions analog input values spaced exactly apart. deviation single step from this ideal value, measured units LSBs. Integral Nonlinearity (INL) deviation ADC's transfer function from best line determined least squares curve that transfer function, measured units LSBs. Gain Error Gain error deviation ADC's actual input full-scale range from ideal value. gain error given percentage ideal input full-scale range. Gain error components: error reference inaccuracy error channel. Both these errors specified independently EGREF EGCHAN. first order approximation, total gain error will ETOTAL EGREF EGCHAN. example, ETOTAL ±0.5%, full-scale input varies from (1-0.5/100) FSideal 0.5/100) FSideal. Offset Error offset error difference, given number LSBs, between ADC's actual average idle channel output code ideal average idle channel output code. This quantity often mapped into Temperature Drift temperature drift coefficient (with respect gain error offset error) specifies change degree Celsius parameter from TMIN TMAX. calculated dividing maximum deviation parameter across TMIN TMAX range difference TMAX-TMIN. Signal-to-Noise Ratio ratio power fundamental (PS) noise floor power (PN), excluding power first nine harmonics. 10Log10 either given units carrier) when absolute power fundamental used reference, dBFS full scale) when power fundamental extrapolated converter's full-scale range. Signal-to-Noise Distortion (SINAD) SINAD ratio power fundamental (PS) power other spectral components including noise (PN) distortion (PD), excluding SINAD 10Log10 SINAD either given units carrier) when absolute power fundamental used reference, dBFS full scale) when power fundamental extrapolated converter's full-scale range. Effective Number Bits (ENOB) ENOB measure converter performance compared theoretical limit based quantization noise.
Submit Documentation Feedback
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129 ADS6148/ADS6128
ENOB
SINAD 1.76 6.02
Total Harmonic Distortion (THD) ratio power fundamental (PS) power first nine harmonics (PD). 10Log10 typically given units carrier). Spurious-Free Dynamic Range (SFDR) ratio power fundamental highest other spectral component (either spur harmonic). SFDR typically given units carrier). Two-Tone Intermodulation Distortion IMD3 ratio power fundamental frequencies power worst spectral component either frequency 2f1-f2 2f2-f1. IMD3 either given units carrier) when absolute power fundamental used reference, dBFS full scale) when power fundamental extrapolated converter's full-scale range. Power Supply Rejection Ratio PSRR) PSSR ratio change offset error change analog supply voltage. PSRR typically given units mV/V. Power Supply Rejection Ratio PSRR) PSRR measure rejection variations supply voltage ADC. VSUP change supply voltage Vout resultant change output code (referred input), then DVOUT (Expressed dBc) PSRR 20Log DVSUP Voltage Overload Recovery number clock cycles taken recover less than error after overload analog inputs. This tested separately applying sine wave signal with positive negative overload. deviation first samples after overload (from their expected values) noted. Common Mode Rejection Ratio (CMRR) CMRR measure rejection variation analog input common-mode ADC. Vcm_in change common-mode voltage input pins VOUT resultant change output code (referred input), then DVOUT (Expressed dBc) CMRR 20Log10 DVCM Cross-Talk (only multi-channel ADC)- This measure internal coupling signal from adjacent channel into channel interest. specified separately coupling from immediate neighboring channel (near-channel) coupling from channel across package (far-channel). usually measured applying full-scale signal adjacent channel. Cross-talk ratio power coupling signal measured output channel interest) power signal applied adjacent channel input. typically expressed dBc.
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
PACKAGE OPTION ADDENDUM
www.ti.com
16-Sep-2008
PACKAGING INFORMATION
Orderable Device ADS6128IRGZR ADS6128IRGZT ADS6129IRGZR ADS6129IRGZT ADS6148IRGZR ADS6148IRGZT ADS6149IRGZR ADS6149IRGZT
Status PREVIEW PREVIEW ACTIVE ACTIVE PREVIEW PREVIEW ACTIVE ACTIVE
Package Type
Package Drawing
Pins Package Plan 2500
Lead/Ball Finish Call Call NIPDAU NIPDAU Call Call NIPDAU NIPDAU
Peak Temp Call Call Level-3-260C-168 Level-3-260C-168 Call Call Level-3-260C-168 Level-3-260C-168
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br)
2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Sep-2008
TAPE REEL INFORMATION
*All dimensions nominal
Device
Package Package Pins Type Drawing
Reel Reel Diameter Width (mm) (mm) 330.0 330.0 16.4 16.4
(mm)
(mm)
(mm)
(mm) 12.0 12.0
Pin1 (mm) Quadrant 16.0 16.0
ADS6129IRGZR ADS6129IRGZT
2500
Pack Materials-Page
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Sep-2008
*All dimensions nominal
Device ADS6129IRGZR ADS6129IRGZT
Package Type
Package Drawing
Pins
2500
Length (mm) 333.2 333.2
Width (mm) 345.9 345.9
Height (mm) 28.6 28.6
Pack Materials-Page
IMPORTANT NOTICE
Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Information third parties subject additional restrictions. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. products authorized safety-critical applications (such life support) where failure product would reasonably expected cause severe personal injury death, unless officers parties have executed agreement specifically governing such use. Buyers represent that they have necessary expertise safety regulatory ramifications their applications, acknowledge agree that they solely responsible legal, regulatory safety-related requirements concerning their products products such safety-critical applications, notwithstanding applications-related information support that provided Further, Buyers must fully indemnify representatives against damages arising products such safety-critical applications. products neither designed intended military/aerospace applications environments unless products specifically designated military-grade "enhanced plastic." Only products designated military-grade meet military specifications. Buyers acknowledge agree that such products which designated military-grade solely Buyer's risk, that they solely responsible compliance with legal regulatory requirements connection with such use. products neither designed intended automotive applications environments unless specific products designated compliant with ISO/TS 16949 requirements. Buyers acknowledge agree that, they non-designated products automotive applications, will responsible failure meet such requirements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters Clocks Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF ZigBee® Solutions amplifier.ti.com dataconverter.ti.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf Applications Audio Automotive Broadband Digital Control Medical Military Optical Networking Security Telephony Video Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office 655303, Dallas, Texas 75265 Copyright 2008, Texas Instruments Incorporated

Other recent searches


OPV1100 - OPV1100   OPV1100 Datasheet
NJM8202MZ - NJM8202MZ   NJM8202MZ Datasheet
NJM8204VZ - NJM8204VZ   NJM8204VZ Datasheet
NJG1650HB6 - NJG1650HB6   NJG1650HB6 Datasheet
LT3757 - LT3757   LT3757 Datasheet
LDGM4341 - LDGM4341   LDGM4341 Datasheet
TRS-X - TRS-X   TRS-X Datasheet
CRX14 - CRX14   CRX14 Datasheet
APD-016A070 - APD-016A070   APD-016A070 Datasheet
AM15EW-C - AM15EW-C   AM15EW-C Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive