Vaccum fluorescent display (VFD) driver Figure Block diagram
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STV7710
Vaccum fluorescent display (VFD) driver
Figure
Block diagram
outputs driver absolute maximum supply 3.3V/5V compatible logic -40/30mA source/sink output -50/50mA source/sink output diode 1-bit data MHz) process Packaging: form
DATA_A
TEST
DATA_B 96bit Shift register
Latch
Description
STV7710 driver vacuum fluorescent display (VFD) designed proprietary high voltage technology. Using wide data bus, control high current high voltage outputs. STV7710 supplied with separated power output supply. command inputs CMOS 3.3V logic levels compatible.
VSSLOG
VSSSUB
STV7710
VSSP
OUT1
OUT96
July 2007
1/21
www.st.com
Contents
STV7710
Contents
Block diagram assignment Mechanical specification
Alignment marks Pads specification
Circuit description
description Data configuration Description
Absolute maximum ratings Electrical characteristics timing requirements timing characteristics Input/ouput schematics Thermal characteristics Ordering information Revision history
2/21
STV7710
Block diagram
Figure
Block diagram
STV7710 block diagram
TEST
DATA_A 96bit Shift register
DATA_B
Latch
VSSLOG
VSSSUB
STV7710
VSSP
OUT1
OUT96
3/21
assignment
STV7710
assignment
Figure assignment
2.07
OUT54 OUT43
OUT55 OUT56 OUT57
OUT42 OUT41 OUT40
5.89
OUT95 OUT96 VSSP VSSP
OUT2 OUT1 VSSP VSSP
VSSLOG
4/21
VSSLOG
VSSSUB
TEST
DATA_B DATA_A
STV7710
Mechanical specification
Mechanical specification
Alignment marks
Figure Alignment marks
min. 0.35 0.25
Patterning restricted area
min. 0.35
0.25
0.15
Pads specification
reference centre (x=0, y=0) Table side from left right
Centre: -773.67 -670.48 -567.29 -464.1 -360.91 -257.72 -154.53 -51.34 51.85 155.04 258.23 361.42 Centre: 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 Size: 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 SIze: 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
Name OUT54 OUT53 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43
0.15
5/21
Mechanical specification Table Bottom side from right left
Centre: 771.63 669.54 566.35 463.16 359.97 257.63 154.44 51.25 -119.85 -567.88 -669.54 -771.63 Centre: -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 Size: 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
STV7710
Name VSSLOG DATA_A DATA_B VSSSUB TEST VSSLOG
SIze: 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
Table
Right side from bottom
Centre: 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 Centre: 2050.11 1946.92 1843.73 1740.54 1638.88 1535.69 1432.50 1329.31 1226.12 1122.93 1019.74 916.55 813.36 710.17 606.98 503.79 400.60 297.41 194.22 91.03 Size: 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 SIze: 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
Name OUT42 OUT41 OUT40 OUT39 OUT38 OUT37 OUT36 OUT35 OUT34 OUT33 OUT32 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23
6/21
STV7710 Table Right side from bottom (continued)
Centre: 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 Centre: -12.15 -115.34 -218.53 -321.72 -424.91 -528.10 -631.29 -734.48 -837.67 -940.86 -1044.05 -1147.24 -1250.43 -1353.62 -1456.81 -1560.00 -1663.19 -1766.38 -1869.57 -1972.76 -2075.95 -2179.14 -2282.16 -2385.35 -2488.46 -2591.65
Mechanical specification
Name OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 VSSP VSSP
Size: 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
SIze: 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
7/21
Mechanical specification Table Left side from bottom
Centre: -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 Centre: -2591.65 -2488.46 -2385.35 -2282.16 -2179.14 -2075.95 -1972.76 -1869.57 -1766.38 -1663.19 -1560.00 -1456.81 -1353.62 -1250.43 -1147.24 -1044.05 -940.86 -837.67 -734.48 -631.29 -528.10 -424.91 -321.72 -218.53 -115.34 -12.15 91.03 194.22 297.41 400.60 503.79 606.98 710.17 813.36 916.55 Size: 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
STV7710
Name VSSP VSSP OUT96 OUT95 OUT94 OUT93 OUT92 OUT91 OUT90 OUT89 OUT88 OUT87 OUT86 OUT85 OUT84 OUT83 OUT82 OUT81 OUT80 OUT79 OUT78 OUT77 OUT76 OUT75 OUT74 OUT73 OUT72 OUT71 OUT70 OUT69 OUT68 OUT67 OUT66
SIze: 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
8/21
STV7710 Table Left side from bottom (continued)
Centre: -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 Centre: 1019.74 1122.93 1226.12 1329.31 1432.50 1535.69 1638.88 1740.54 1843.73 1946.92 2050.11
Mechanical specification
Name OUT65 OUT64 OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55
Size: 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
SIze: 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
9/21
Circuit description
STV7710
Circuit description
description
Table
Symbol OUT(01-96) VSSP VSSLOG VSSSUB DATA_A DATA_B TEST
STV7710 description
Function Output Ground Supply Input Input Input Supply Ground Ground Input Input Input/output Input/output Input Power output Ground power outputs High voltage supply power outputs Blanking input Power output control input Selection shift direction logic supply Logic ground Substrate ground Clock data shift register Latch data outputs Shift register input Shift register output Test input Description
Table
Input
Data configuration
STV7710 data configuration
Data shift Output DATA_B DATA_A Forward shift Reverse shift
DATA_A Output DATA_B Output
This table describes position first data sampled first rising edge signal.
10/21
STV7710
Circuit description
Description
STV7710 includes logic power circuits necessary drive electrodes vacuum fluorescent display (VFD). Binary values each pixel displayed line loaded into shift register DATA_A/B data bus. Data shifted each high transition clock. After shifts, data available output shift register. This output used cascade several drive higher resolution displays. forward /reverse (F/R) input used select direction shift register. Data input/output status according selected direction (refer Table maximum frequency shift clock 40MHz. When signal high, data transferred from shift register latch power output stages. output data kept memorized held latch stage when latch input level. Vsssub Vsslog must connected close possible logical reference ground application. Also, make sure that TEST input connected ground (Figure STV7710 supplied with power supply. logic inputs driven either CMOS logic, CMOS logic. Table Shift register truth table
Input Data-in data-out Shift register function DATA_A Data-in Data-out DATA_B Data-out Data-in Forward shift Steady Reverse shift Steady
Table
TEST
Power output truth table
Driver output "Low" "High" Comments Output level Output high level Data latched Data transfered Data transfered
11/21
Absolute maximum ratings
STV7710
Absolute maximum ratings
Table
Symbol IPOUT Tjmax TSTG VOUT Logic supply range Driver supply range Logic input voltage range Driver output current(1) Maximum junction temperature Storage temperature range Output power voltage range
Absolute maximum ratings
Parameter -0.3, -0.3, -0.3, Vcc+0.3 -30, +150 -0.3, Value Unit
Through power output. Through power output power outputs (see Figure Test configuration) with Junction temperature lower than equal Tjmax
susceptibility Human Body Model: pins withstand except Data_A Data_B:
12/21
STV7710
Electrical characteristics
Electrical characteristics
(VCC VSSP Tamb fCLK MHz, unless otherwise specified)
Table
Symbol Supply ICCL IPPH Output
Electrical characteristics
Parameter Unit
Logic supply voltage Logic supply current
4.50 MHz)(2)
Logic dynamic supply current (fCLK=20 Logic supply current (VIH=2.0V) Power output supply voltage
Power output supply current (steady outputs)
OUT1-OUT96 (Figure VPOUTH VPOUTL VDOUTH VDOUTL Power output high level (voltage drop versus VPP) @IPOUTH Power output level IPOUTL Output diode voltage drop IDOUTH
Output diode voltage drop IDOUTL mA(3)
DATA DATA (Figure Input CLK, F/R, STB, POC, BLK, DATA_A, DATA (Figure Input high level Input level High level input current (VIH >=2.0V) level input current (VIL Input capacitance(4) Logic output high level @IOH=-1mA Logic output level @IOL
Logic input levels compatible with CMOS logic. data inputs commuted 10MHz Figure Test configuration This parameter measured during ST's internal qualification which includes temperature characterization standard corner batches process. This parameter tested part.
13/21
timing requirements
STV7710
timing requirements
Tamb input signals leading edge trailing edge (tr,
Table
Symbol tCLK tWHCLK tWLCLK tSDAT tHDAT tHSTB tSTB tSSTB
timing requirements
Parameter Data clock period Duration pulse high level Duration pulse level Set-up time data input before high clock transition Hold-time data input after high clock transition Hold-time after high clock transition Unit
level pulse duration set-up time before rise
14/21
STV7710
timing characteristics
timing characteristics
VSSP VSSSUB Vsslog Tamb 25°C, fCLK (VILMAX Vcc, VIHMIN VCC)
Table
Symbol tPHL1 tPLH1 tPHL2 tPLH2
timing characteristics
Parameter Delay power output change after transition high high Delay power output change after transition high high Delay power output change after BLK, transition high high Power output rise time(1) Power output fall time(1) Width falling edge smooth shape (not tested)(2) Logic data output rise time 10pF) Logic data output fall time 10pF) Delay logic data output change after transition high high Unit
tPHL3 tPLH3 tPHL4 tPLH4
output among loading capacitor 50pF, other outputs level Figure Zoom OUTn showing
15/21
timing characteristics Figure characteristics waveform
tCLK tWHCLK tWLCLK
STV7710
tSDAT tHDAT DATA_A tPHL4
DATA_B
tSTB
tPLH4
tHSTB
tSSTB
tPHL2 tPLH2
tPHL1 tPLH1
OUTn
(POC="L")
tPLH3 OUTn
tPHL3
16/21
STV7710 Figure Test configuration
VPP=VSSP
timing characteristics
VPP=VSSP
VDOUTH
IDOUTH
VDOUTL VSSP VSSP
IDOUTL
Output sinking current positive value, sourcing current negative value
Figure
Zoom OUTn showing
OUTn
17/21
Input/ouput schematics
STV7710
Figure
Input/ouput schematics
CLK, STB, F/R, POC, inputs
Figure
Test
CLK, F/R, POC, BLK,
TEST
GNDSUB GNDSUB GNDLOG must grounded application
GNDLOG
Figure DATA_A, DATA_B
Figure Power output
DATA_A DATA_B
OUT1
GNDLOG GNDSUB
VSSP
18/21
STV7710
Thermal characteristics
Thermal characteristics
STV7710 exposed high temperatures during manufacturing module (display sealing). STV7710 qualified maximum storage temperature 475°C during minutes following thermal profile described Figure Figure Thermal profile applied internal qualification
Temperature (°C)
Time (minutes)
19/21
Ordering information
STV7710
Ordering information
Table Order codes
Description Bare Tested usawn bump wafer (u=die) Unsawn wafer Dice cavity plate (unit=die)
Part number STV7710 STV7710/BMP STV7710/WAF STV7710/WP
Revision history
Table
Date 24-Mar-2004 30-Apr-2004 11-Jul-2007
Document revision history
Revision Initial release. Renamed document STV7710/WAF order code. Added Chapter Ordering information Chapter Revision history. Updated document cover STV7710 order codes. Changes
20/21
STV7710
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