1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
differential 3.3V LVPECL outputs Selectable differential clock inputs CLKx, nCLKx pair accept following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL range: 200MHz 500MHz External feedback "zero delay" clock regeneration with configurable frequencies Cycle-to-cycle jitter (RMS): 20ps (maximum) Output skew: 70ps (maximum), within bank 3.3V supply voltage -40°C 85°C ambient operating temperature compatible with MPC993
GENERAL DESCRIPTION
ICS87993I clock driver designed specifically redundant clock tree designs. HiPerClockSdevice receives differential LVPECL clock signals from which generates differential LVPECL clock outputs. output pairs regenerate input signal frequency phase while other three pairs generate phase aligned clock outputs. External feedback used also provide zero delay buffer performance.
ICS87993I Dynamic Clock Switch (DCS) circuit continuously monitors both input signals. Upon detection failure (CLK stuck HIGH least period), INP_BAD that will latched (H). that primary clock, will switch good secondary clock phase/frequency alignment will occur with minimal output phase disturbance. typical phase bump caused failed clock eliminated.
ASSIGNMENT
nQB0 nQB1 nQB2
nQA1 nQA0 VCCA MAN_OVERRIDE PLL_SEL
INP0BAD INP1BAD CLK_SELECTED nEXT_FB EXT_FB
ICS87993I
32-Lead (LQFP) 1.4mm package body Package View
nALARM_RESET
CLK0
nCLK0
CLK_SEL
CLK1
nCLK1
BLOCK DIAGRAM
PLL_SEL CLK_SELECTED INP1BAD INP0BAD MAN_OVERRIDE ALARM_RESET SEL_CLK nCLK0 CLK0 nCLK1 CLK1 nEXT_FB EXT_FB
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Dynamic Switch Logic
nQB0 nQB1
nQB2 nQA0 nQA1
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
Type Input Description Active Master Reset. When logic LOW, internal dividers reset causing true outputs inver outputs Pullup high. When logic HIGH, internal dividers outputs enabled. LVCMOS LVTTL interface levels. When LOW, resets input flags aligns CLK_SELECTED Pullup with SEL_CLK. LVCMOS LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup
TABLE DESCRIPTIONS
Number Name
nALARM_RESET CLK0 nCLK0 SEL_CLK CLK1 nCLK1 EXT_FB nEXT_FB CLK_SELECTED INP1BAD
Input Input Input Input Input Input Power Input Input Output Output
Inver ting differential clock input. Clock select input. When LOW, selects CLK0, nCLK0 inputs. When Pulldown HIGH, selects CLK1, nCLK1 inputs. LVCMOS LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Negative supply pins. Pulldown Differential external feedback. Pullup Differential external feedback. LOW, when CLK0, nCLK0 selected, HIGH, when CLK1, nCLK1 selected. LVCMOS LVTTL interface levels. Indicates detection input reference clock with respect feedback signal. output active HIGH will remain HIGH until alarm reset asser ted. Indicates detection input reference clock with respect feedback signal. output active HIGH will remain HIGH until alarm reset asser ted. Core supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Analog supply pin. Manual override. When HIGH, disables internal clock switch circuitr Pulldown LVCMOS LVTTL interface levels. Selects between reference clock input Pullup dividers. When LOW, selects reference clock.When HIGH, selects PLL. LVCMOS LVTTL interface levels.
INP0BAD nQB2, nQB1, nQB0, nQA1, nQA0, VCCA MAN_OVERRIDE PLL_SEL
Output Power Output Output Output Output Output Power Input Input
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
4.6V -0.5V 50mA 100mA 47.9°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA 3.3V±5%, -40°C 85°C
Symbol VCCA ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical Maximum 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VCCA 3.3V±5%, -40°C 85°C
Symbol Parameter Input High Voltage Input Voltage LVCMOS Inputs LVCMOS Inputs SEL_CLK, MAN_OVERRIDE Input High Current nALARM_RESET, PLL_SEL, SEL_CLK, MAN_OVERRIDE Input Current nALARM_RESET, PLL_SEL, Output High Voltage; NOTE Test Conditions Minimum -0.3 3.465V 3.465V 3.465V 3.465V -120 Typical Maximum Units
Output Voltage; NOTE NOTE Outputs terminated with VCC/2. Parameter Measurement Information Section, "3.3V Output Load Test Circuit diagram".
TABLE DIFFERENTIAL CHARACTERISTICS, VCCA 3.3V±5%, -40°C 85°C
Symbol Parameter CLK0, CLK1, EXT_FB Input High Current nCLK0, nCLK1, nEXT_FB CLK0, CLK1, EXT_FB Input Current nCLK0, nCLK1, nEXT_FB Peak-to-Peak Input Voltage Test Conditions 3.465V 3.465V 3.465V 3.465V -120 0.15 0.85 Minimum Typical Maximum Units
Common Mode Input Voltage; NOTE VCMR NOTE Common mode voltage defined VIH. NOTE single ended appliations, maximum input voltage CLK, nCLK 0.3V.
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
Test Conditions Minimum Typical Maximum Units
TABLE LVPECL CHARACTERISTICS, VCCA 3.3V±5%, -40°C 85°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing
NOTE Outputs terminated with
TABLE CHARACTERISTICS, VCCA 3.3V±5%, -40°C 85°C
Symbol fVCO tPWI CLKx Propagation Delay CLKx EXT_FB; NOTE PLL_SEL PLL_SEL HIGH fVCO 360MHz PLL_SEL HIGH fVCO 500MHz 50MHz Parameter Lock Range Test Conditions Minimum -150 -150 3.45 Typical Maximum Tested typical conditions 360MHz Units ps/cycle ps/cycle ps/cycle ps/cycle
Output Rise Time Output Skew; NOTE Within Bank Outputs 75MHz Output; NOTE 150MHz Output; NOTE 75MHz Output; NOTE 150MHz Output; NOTE
sk(o)
PER/CYCLE
Rate change Periods
jit(cc)
Output Duty Cycle Cycle-to-Cycle Jitter (RMS); NOTE Lock Time; NOTE
parameters measured fMAX unless noted otherwise. NOTE These parameters guaranteed characterization. tested production. NOTE Defined time difference between input reference clock averaged feedback input signal, when locked input reference frequency stable. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE Specification holds clock switch between signals greater than 400ps phase. Delta period change cycle averaged over clock switch excursion. NOTE Specification holds clock switch between signals greater than phase. Delta period change cycle averaged over clock switch excursion.
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
PARAMETER MEASUREMENT INFORMATION
VCCA
SCOPE
nCLK0, nCLK1
LVPECL
Cross Points
CLK0, CLK1
-1.3V 0.165V
3.3V OUTPUT LOAD TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
tsk(o)
nQAx, nQBx nQAx, nQBx
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
Clock Outputs
nQAx, nQBx nQAx, nQBx
Pulse Width
PERIOD
PERIOD
OUTPUT RISE/FALL TIME
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tPERIOD
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tcycle
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS87993I provides separate power supplies isolate high switching noise from outputs internal PLL. VCCA should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VCCA pin.
3.3V .01µF VCCA .01µF
FIGURE POWER SUPPLY FILTERING
TERMINATION LVPECL OUTPUTS
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
FOUT
3.3V
FOUT
(VOH
FIGURE LVPECL OUTPUT TERMINATION
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FIGURE LVPECL OUTPUT TERMINATION
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
WIRING DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
Figure shows differential input wired accept single ended levels. reference voltage V_REF VCC/2 generated bias resistors This bias circuit should located close possible input pin. ratio
Single Ended Clock Input
CLKx
V_REF
nCLKx
0.1u
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
here examples only. Please consult with vendor driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples HiPerClockS CLK/nCLK input driven most common driver types. input interfaces suggested
3.3V 3.3V 3.3V 1.8V nCLK LVHSTL HiPerClockS LVHSTL Driver LVPECL HiPerClockS Input nCLK HiPerClockS Input
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
3.3V 3.3V LVDS_Driv
nCLK
Receiv
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
3.3V 3.3V 3.3V LVPECL nCLK HiPerClockS Input
R5,R6 locate near driver pin.
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH COUPLE
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
Bank Bank depending application. decoupling capacitors should physically located near power pin. ICS87993I, unused outputs left floating.
SCHEMATIC EXAMPLE
Figure shows schematic example ICS87993I. this example, CLK0/nCLK0 input selected primary. input driven LVPECL driver. Feedback either from
VCCA LVCMOS 0.01u
CLK_SEL LVPECL Driv (Option) 0.1u ICS87993I
PLL_SEL MAN_OVR VCCA nQA0 nQA1
(Option) 0.1u nQB0 nQB1 nQB2
LVPECL Driv (Option) 0.1u (Option) 0.1u
EXT_FB nEXT_FB CLK_SELECTED INP1BAD INP0BAD
nALM_RS CLK0 nCLK0 CLK_SEL CLK1 nCLK1
LVCMOS
LVCMOS
LVCMOS
(U1-16)
(U1-17)
(U1-24)
(U1-29)
0.1uF
0.1uF
0.1uF
0.1uF
FIGURE ICS87993I LVPECL SCHEMATIC EXAMPLE
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following component footprints used this layout example: resistors capacitors size 0603.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces. differential output traces should have same length. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock traces same layer. Whenever possible, avoid placing vias clock traces. Placement vias traces affect trace characteristic impedance hence degrade signal integrity. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow separation least three trace widths between differential clock trace other signal trace. Make sure other signal traces routed between clock trace pair. series termination resistors should located close driver pins possible.
POWER
GROUNDING
Place decoupling capacitors close possible power pins. space allows, placement decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power caused via. Maximize power ground sizes number vias capacitors. This reduce inductance between power ground planes component power ground pins. filter consisting C11, should placed close VDDA possible.
CLOCK TRACES
TERMINATION
Poor signal integrity degrade system performance cause system failure. synchronous high-speed digital systems, clock signal less tolerant poor signal integrity than other signals. ringing rising falling edge excessive ring back cause system failure. shape trace
VCCA
Traces
FIGURE BOARD LAYOUT ICS87993I
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS87993I. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS87993I core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 624mW Power (outputs)MAX 30.2mW/Loaded Output pair outputs loaded, total power 30.2mW 151mW
Total Power_MAX (3.465V, with outputs switching) 624mW 151mW 775mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 42.1°C/W Table below. Therefore, ambient temperature 85°C with outputs switching 85°C 0.775W 42.1°C/W 117.6°C. This below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
32-PIN LQFP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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Calculations Equations.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
VOUT
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CC_MAX
OH_MAX
CC_MAX
1.0V
OH_MAX
1.0V 1.7V
logic low, VOUT
CC_MAX
OL_MAX
CC_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CC_MAX
CC_MAX
OH_MAX
[(2V
CC_MAX
OH_MAX
))/R
CC_MAX
OH_MAX
[(2V 1V)/50] 20.0mW ))/R
Pd_L
OL_MAX
CC_MAX
2V))/R
CC_MAX
OL_MAX
[(2V
CC_MAX
OL_MAX
CC_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30.2mW
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS87993I 2745
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
Marking ICS87993AYI ICS87993AYI Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS87993AYI ICS87993AYIT
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 87993AYI
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
REVISION HISTORY SHEET Description Change Table deleted Note Added "Wiring Differential Input Accept Single Ended Levels". Features Section changed max. from 360MHz 500MHz. Descriptions Table revised description. Characteristics Table changed from max. typical 4pF. Absolute Maximum Ratings changed included Continuous Current Surge Current Characteristics Table changed fVCO from 360MHz 500MHz. added test conditions CLKx EXT_FB. Added another line with 500MHz test conditions. added test conditions. Added Differential Clock Input Interface Application Information section. Added Schematic Example. 5/21/03 Date 1/16/03
Table
Page
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