MCF52277 LQFP-176 MAPBGA-196 15mm 15mm MCF5227x ColdFire® Mi

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MCF52277 LQFP-176 MAPBGA-196 15mm 15mm MCF5227x ColdFire® Mi

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Document Number: MCF52277 Rev. 07/2008
MCF52277
LQFP-176 MAPBGA-196 15mm 15mm
MCF5227x ColdFire® Microprocessor Data Sheet
Features Version ColdFire® Core with EMAC Dhrystone MIPS 166.67 Kbytes configurable cache (instruction only, data only, split instruction/data) Kbytes internal SRAM Support booting from SPI-compatible flash, EEPROM, FRAM devices Crossbar switch technology (XBS) concurrent access peripherals from multiple masters channel controller 32-bit SDR/DDR controller On-the-Go controller Liquid crystal display controller with support pixels touchscreen controller FlexCAN module 32-bit timers with support supported serial peripheral interface (DSPI) UARTs interface Synchronous serial interface (SSI) Plus-width modulator (PWM) Real-time clock (RTC) programmable interrupt controllers (PIT)
This document contains information product. Specifications information herein subject change without notice. Freescale Semiconductor, Inc., 2008. rights reserved. Preliminary-Subject Change Without Notice
Table Contents
MCF5227x Family Comparison Ordering Information. Hardware Design Considerations Power Filtering. Power Filtering Power Filtering Supply Voltage Sequencing 3.4.1 Power Sequence 3.4.2 Power Down Sequence Power Consumption Specifications. Assignments Reset States Signal Multiplexing Pinout-176 LQFP Pinout-196 MAPBGA Electrical Characteristics Maximum Ratings Thermal Characteristics Protection Electrical Specifications Oscillator Electrical Characteristics Electrical Characteristics 5.6.1 Gain Calculations External Interface Timing Specifications 5.7.1 FlexBus 5.7.2 SDRAM General Purpose Timing Reset Configuration Override Timing 5.10 Controller Timing Specifications 5.11 On-The-Go Specifications. 5.12 Timing Specifications 5.13 Timing Specifications 5.14 Timer Timing Specifications 5.15 DSPI Timing Specifications 5.16 Timing Specifications. 5.17 JTAG Boundary Scan Timing Specifications 5.18 Debug Timing Specifications Package Information Product Documentation. Revision History
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
MCF52277
JTAG Configurable Cache Version ColdFire Core Serial Boot Facility Oscillator
128K SRAM
Hardware Divide
EMAC
Controller
eDMA
Crossbar Switch (XBS)
Peripheral Bridge FlexBus Touch Screen DSPI FlexCAN GPIO
SDRAM Controller
EPORT
INTC
PITs
UARTs
Timers
LEGEND
DSPI eDMA EMAC EPORT GPIO INTC JTAG Background debug module serial peripheral interface Enhanced direct memory access Enchance multiply-accumulate unit Edge port module General Purpose Input/Output Module Inter-Intergrated Circuit Interrupt controller Joint Test Action Group interface UART Liquid-crystal display Programmable interrupt timer Phase locked loop module Pulse-width modulator Real time clock Synchronous Serial Interface Universal asynchronous receiver/transmitter Universal Serial On-the-Go controller
Figure MCF52277 Block Diagram
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
MCF5227x Family Comparison
MCF5227x Family Comparison
Table MCF5227x Family Configurations
Module ColdFire Version Core with EMAC (Enhanced Multiply-Accumulate Unit) Core (System) Clock Peripheral External Clock (Core clock Performance (Dhrystone/2.1 MIPS) Static (SRAM) Configurable Cache Touchscreen Controller Controller On-the-Go FlexBus External Interface SDR/DDR SDRAM Controller FlexCAN 2.0B communication module Real Time Clock Watchdog Timer 16-channel Direct Memory Access (DMA) Interrupt Controllers (INTC) Synchronous Serial Interface (SSI)
following table compares various device derivatives available within MCF5227x family.
MCF52274
MCF52277 166.67 83.33
Kbytes Kbytes 12-bit color LQFP 18-bit color MAPBGA
DSPI UARTs 32-bit Timers Periodic Interrupt Timers (PIT) Module Edge Port Module (EPORT) General Purpose Module (GPIO) JTAG IEEE 1149.1 Test Access Port Package
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Ordering Information
Ordering Information
Table Orderable Part Numbers
Freescale Part Number MCF52274CLU120 MCF52277CVM160 Description MCF52274 RISC Microprocessor MCF52277 RISC Microprocessor Package LQFP MAPBGA Speed 166.67 Temperature -40° +85° -40° +85°
Hardware Design Considerations
Power Filtering
further enhance noise isolation, external filter strongly recommended analog pins. filter shown Figure should connected between board PLLVDD pins. resistor capacitors should placed close dedicated PLLVDD possible.
Board IVDD
Figure System Power Filter
Power Filtering
minimize noise, external filters required each power pins. filter shown Figure should connected between board EVDD USBVDD pin. resistor capacitors should placed close dedicated USBVDD possible.
Board EVDD
Figure Power Filter
NOTE
addition above filter circuitry, 0.01 capacitor also recommended parallel with those shown.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Hardware Design Considerations
Power Filtering
minimize noise, external filters required ADCVDD power pin. filter shown Figure should connected between board EVDD ADCVDD pin. resistor capacitors should placed close dedicated ADCVDD possible.
Board EVDD
Figure Power Filter
Supply Voltage Sequencing
relationship between SDVDD EVDD non-critical during power-up power-down sequences. Both SDVDD (2.5V 3.3V) EVDD specified relative IVDD.
3.4.1
Power Sequence
EVDD/SDVDD powered with IVDD then sense circuits pads will cause output drivers connected EVDD/SDVDD high impedance state. There limit long after EVDD/SDVDD powers before IVDD must powered IVDD should lead EVDD, SDVDD PLLVDD more than during power ramp-up, there will high current internal protection diodes. rise times power supplies should slower than avoid turning internal protection clamp diodes.
3.4.2
Power Down Sequence
IVDD/PLLVDD powered down first, then sense circuits pads will cause output drivers high impedance state. There limit long after IVDD PLLVDD power down before EVDD SDVDD must power down. IVDD should EVDD, SDVDD, PLLVDD going more than during power down there will undesired high current protection diodes. There requirements fall times power supplies. recommended power down sequence follows: Drop IVDD/PLLVDD Drop EVDD/SDVDD supplies.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Hardware Design Considerations
Power Consumption Specifications
Table MCF52277 Application Power Consumption1
application power consumption data data measured M52277EVB running Freescale Linux BSP.
Core Freq. IVDD EVDD SDVDD Total Power
Idle (LCD image) 61.4 28.87 18.8 221.211
Idle (audio image) 59.2 25.73 18.57 207.135
Button Demo 84.7 35.3 21.8 282.78
Slideshow Demo 96.5 34.6 23.9 301.95
Playback 89.2 33.46 22.66 285.006
File Copy 89.5 29.86 22.2 272.748
Units
voltage rails nominal values: IVDD EVDD SDVDD
Idle (LCD image) Idle (Audio Image) Button Demo Slideshow Demo Playback File Copy
Total Power (mW)
Figure Power Consumption Various Applications current consumption data data measured single device using evaluation board. Table shows typical power consumption low-power modes. These current measurements taken after executing STOP instruction. Table Current Consumption Low-Power Modes1,2
System Frequency Mode Voltage Supply 80MHz IVDD (mA) Power (mW) WAIT IVDD (mA) Power (mW) 75.1 112.65 61.9 92.85 64MHz 62.7 94.05 52.8 79.20 48MHz 49.2 73.80 42.0 63.00 32MHz 36.6 54.90 31.7 47.55 4MHz (LIMP mode) 5.25 4.35
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Hardware Design Considerations
Table Current Consumption Low-Power Modes1,2 (continued)
System Frequency Mode Voltage Supply 80MHz IVDD (mA) Power (mW) STOP IVDD (mA) Power (mW) STOP IVDD (mA) Power (mW) STOP IVDD (mA) Power (mW) STOP
64MHz 48.8 73.20 15.1 22.65 14.9 22.35 2.70 0.75
48MHz 38.9 58.35 13.4 20.10 13.2 19.80 2.70 0.75
32MHz 29.7 44.55 12.5 18.75 12.4 18.60 2.70 0.75
4MHz (LIMP mode) 4.05 1.95 1.95 1.95 0.75
57.0 85.50 16.1 24.15 15.9 23.85 2.70 0.75
DOZE
IVDD (mA) Power (mW)
values measured M52277EVB with nominal core voltage(IVDD Tests performed room temperature. peripheral clocks prior entering low-power mode Refer Power Management chapter MCF52277 Reference Manual more information low-power modes.
(LIMP) System Frequency (MHz) WAIT DOZE STOP STOP STOP STOP
IVDD Power Consumption (mW)
Figure IVDD Power Consumption Low-Power Modes
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Assignments Reset States
Assignments Reset States
Signal Multiplexing
following table lists MCF5227x pins grouped function. direction column direction primary function only. Refer Section "Pin Assignments Reset States," package diagrams. more detailed discussion MCF5227x signals, consult MCF52277 Reference Manual (MCF52277RM).
NOTE
this table throughout this document single signal within group designated without square brackets (i.e., FB_A23), while designations multiple signals within group brackets (i.e., FB_A[23:21]) meant include signals within bracketed numbers when these numbers separated colon.
NOTE
primary functionality necessarily default functionality. Most pins that muxed with GPIO will default their GPIO functionality. Table list exceptions. Table Special-Case Default Signal Functionality
FB_BE/BWE[3:0] FB_CS[3:0] FB_OE FB_TA FB_R/W FB_TS Default Signal FB_BE/BWE[3:0] FB_CS[3:0] FB_OE FB_TA FB_R/W FB_TS
Table MCF5227x Signal Information Muxing
Voltage Domain Pull-up (U)1 Pull-down Direction2
Signal Name
GPIO
Alternate
Alternate
MCF52274 LQFP
MCF52277 MAPBGA
Reset RESET RSTOUT Clock EXTAL XTAL Mode Selection BOOTMOD[1:0]
EVDD 110, G10,
EVDD EVDD
EVDD EVDD
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Assignments Reset States
Table MCF5227x Signal Information Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down Direction2
Signal Name
GPIO
Alternate
Alternate
MCF52274 LQFP
MCF52277 MAPBGA
FlexBus FB_A[23:22] FB_A[21:16] FB_A[15:14] FB_A[13:11] FB_A10 FB_A[9:0] FB_CS[5:4] SD_BA[1:0] SD_A[13:11] SD_A[9:0]
SDVDD 143, C11, A12, B12, C12, B13, A13, B14, C14, D12, E11-E14, F11-F13, G11, G12, K1-K4, L1-L3, P3,M4, G1-G4, H1-H4, B11,
SDVDD 141-139, 137-135 SDVDD SDVDD SDVDD SDVDD 131, 129-127 125-116
FB_D[31:16]
SD_D[31:16]
SDVDD
30-37, 49-56
FB_D[15:0]
FB_D[31:16]
SDVDD
19-26, 60-67
FB_CLK FB_BE/BWE[3:0] FB_CS[3:2] FB_CS1 FB_CS0 FB_OE FB_TA FB_R/W FB_TS
PBE[3:0] PCS[3:2] PCS1 PCS0 PFBCTL3 PFBCTL2 PFBCTL1 PFBCTL0
SD_DQM[3:0] SD_CS1 DACK0
SDRAM Controller
SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD
SD_A10 SD_CAS SD_CKE SD_CLK SD_CLK SD_CS0 SD_DQS[3:2] SD_RAS SD_SDR_DQS
SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Assignments Reset States
Table MCF5227x Signal Information Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down Direction2
Signal Name
GPIO
Alternate
Alternate
MCF52274 LQFP
MCF52277 MAPBGA
SD_WE
External Interrupts Port4
SDVDD
IRQ7 IRQ4 IRQ1
PIRQ7 PIRQ4 PIRQ1
DREQ0 USB_CLKIN
DSPI_PCS4 SSI_CLKIN Controller6
EVDD EVDD EVDD
LCD_D[17:16]6 LCD_D[15:14]6 LCD_D13 LCD_D12 LCD_D[11:8]6 LCD_D7 LCD_D6 LCD_D[5:2]6 LCD_D1 LCD_D0 LCD_ACD/ LCD_OE LCD_FLM/ LCD_VSYNC LCD_LP/ LCD_HSYNC LCD_LSCLK
PLCDDH[1:0] PLCDDM[7:6] PLCDDM5 PLCDDM4 PLCDDM[3:0] PLCDDL7 PLCDDL6 PLCDDL[5:2] PLCDDL1 PLCDDL0 PLCDCTL3 PLCDCTL2 PLCDCTL1 PLCDCTL0
LCD_D[11:10] LCD_D[9:8] CANTX CANRX LCD_D[7:4] PWM7 PWM5 LCD_D[3:0] PWM3 PWM1 LCD_SPL_SPR
On-the-Go
EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD
175-172
EVDD
EVDD
EVDD
USB_DM USB_DP
Real Time Clock
RTC_EXTAL RTC_XTAL
EVDD EVDD
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Assignments Reset States
Table MCF5227x Signal Information Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down Direction2
Signal Name
GPIO
Alternate
Alternate
MCF52274 LQFP
MCF52277 MAPBGA
ADC_IN[7:0]
VDD_ VDD_ 82-85, 87-90 P12, N12, P13, N13, P14, N14, M13,
ADC_REF
I2C_SCL I2C_SDA
PI2C1 PI2C0
CANTX CANRX
U2TXD U2RXD DSPI7
EVDD EVDD
DSPI_PCS0/SS DSPI_SIN DSPI_SOUT DSPI_SCK
PDSPI3 PDSPI2 PDSPI1 PDSPI0
U2RTS U2RXD U2TXD U2CTS
SBF_DI SBF_D0 SBF_CK UARTs
EVDD EVDD EVDD EVDD
U1CTS U1RTS U1RXD U1TXD U0CTS U0RTS U0RXD U0TXD
PUART7 PUART6 PUART5 PUART4 PUART3 PUART2 PUART1 PUART0
SSI_BCLK SSI_FS SSI_RXD SSI_TXD DT1OUT DT1IN CANRX CANTX
LCD_CLS LCD_PS USB_VBUS_EN USB_VBUS_OC Timers
EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD
DT3IN DT2IN/SBF_CS DT1IN DT0IN
PTIMER3 PTIMER2 PTIMER1 PTIMER0
DT3OUT DT2OUT DT1OUT DT0OUT
SSI_MCLK DSPI_PCS2 LCD_CONTRAST LCD_REV BDM/JTAG9
EVDD EVDD EVDD EVDD
PST[3:0] DDATA[3:0] ALLPST
EVDD EVDD EVDD
L10, M10, N10,
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Assignments Reset States
Table MCF5227x Signal Information Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down Direction2
Signal Name
GPIO
Alternate
Alternate
MCF52274 LQFP
MCF52277 MAPBGA
JTAG_EN PSTCLK BKPT DSCLK
TCLK TRST Test
EVDD EVDD EVDD EVDD EVDD EVDD
TEST
Power Supplies
EVDD
IVDD EVDD SD_VDD VDD_OSC VDD_PLL VDD_USB VDD_RTC VDD_ADC VSS_OSC VSS_ADC
114, 138,
F10,
111, 148, 113, 132, 112, 133, G6-G8, H6-H8,
Pull-ups generally only enabled pins with their primary function, except noted. Refers pin's primary function. Enabled only oscillator bypass mode (internal crystal oscillator disabled). GPIO functionality determined edge port module. GPIO module only responsible assigning alternate functions. Pull-up when DREQ controls pin. LQFP device only supports 12-bit data bus. DSPI signal functionality controlled RESET. When asserted, these pins configured serial boot; when negated, pins configured DSPI. Pull-up when serial boot facility (SBF) controls pin. JTAG_EN asserted, these pins default alternate (JTAG) functionality. GPIO module responsible assigning these pins.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Assignments Reset States
Pinout-176 LQFP
EVDD LCD_D5 LCD_D4 LCD_D3 LCD_D2 IVDD LCD_LSCLK LCD_ACD/OE I2C_SCL I2C_SDA T0IN T1IN T2IN T3IN IRQ7 IRQ4 IRQ1 U1TXD U1RXD U1RTS U1CTS DSPI_SIN DSPI_SOUT DSPI_SCK DSPI_PCS0 VDD_USB USB_DP USB_DM EVDD SD_VDD FB_CS0 FB_CS1 FB_A23 FB_A22 FB_A21 FB_A20 FB_A19 IVDD FB_A18 FB_A17 FB_A16 TEST
pinout MCF52274 package shown below.
LCD_D8 LCD_D9 LCD_D10 LCD_D11 LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_FLM/VSYNC LCD_LP/HSYNC EVDD SD_VDD FB_TS SD_WE SD_CKE SD_CS0 FB_D15 FB_D14 FB_D13 FB_D12 FB_D11 FB_D10 FB_D9 FB_D8 FB_BE/BWE1 SD_DQS3 FB_BE/BWE3 FB_D31 FB_D30 FB_D29 FB_D28 FB_D27 FB_D26 FB_D25 FB_D24 SD_SDR_DQS IVDD SD_CLK SD_CLK FB_CLK SD_VDD SD_VDD
SD_VDD FB_A15 FB_A14 FB_A13 FB_A12 FB_A11 FB_A10 FB_A9 FB_A8 FB_A7 FB_A6 FB_A5 FB_A4 FB_A3 FB_A2 FB_A1 FB_A0 FB_TA IVDD SD_VDD EVDD BOOTMOD1 BOOTMOD0 VDD_OSC VSS_OSC EXTAL XTAL VDD_PLL RESET RSTOUT VDD_RTC RTC_EXTAL RTC_XTAL U0RTS U0CTS U0RXD U0TXD EVDD VSS_ADC VDD_ADC ADC_IN0 ADC_IN1
SD_A10 SD_CAS SD_RAS FB_D23 FB_D22 FB_D21 FB_D20 FB_D19 FB_D18 FB_D17 FB_D16 FB_BE/BWE2 SD_DQS2 FB_BE/BWE0 FB_D7 FB_D6 FB_D5 FB_D4 FB_D3 FB_D2 FB_D1 FB_D0 FB_R/W FB_OE SD_VDD EVDD EVDD PSTCLK IVDD ALLPST DSCLK JTAG_EN BKPT ADC_IN7 ADC_IN6 ADC_IN5 ADC_IN4 ADC_REF ADC_IN3 ADC_IN2
Figure MCF52274 Pinout (176 LQFP)
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
LCD_D6
Pinout-196 MAPBGA
LCD_D5 LCD_D4 LCD_D2 LCD_ LSCLK LCD_ ACD/OE T0IN U1TXD U1RXD USB_DM USB_DP FB_CS2 FB_A21 FB_A17 FB_A16
pinout MCF52277 package shown below.
LCD_D8
LCD_D7
LCD_D3
LCD_D1
T1IN
IRQ_1
U1RTS
DSPI_ PCS0 DSPI_ DSPI_ SOUT
VDD_
FB_CS3
FB_A20
FB_A18
FB_A15
LCD_D13 LCD_D12 LCD_D10
LCD_D0
I2C_SCL
T2IN
IRQ_4
U1CTS
FB_CS0
FB_A23
FB_A19
FB_A14
FB_A13
LCD_D15 LCD_D14 LCD_D11
LCD_D9
I2C_SDA
T3IN
IRQ_7
DSPI_SIN
FB_CS1
FB_A22
FB_A12
FB_A11
FB_A10
LCD_LP/ LCD_FLM/ LCD_D17 LCD_D16 HSYNC VSYNC
IVDD
EVDD
EVDD
SDVDD
SDVDD
TEST
FB_A9
FB_A8
FB_A7
FB_A6
SD_CS0
SD_CKE
SD_WE
FB_TS
EVDD
EVDD
SDVDD
IVDD
FB_A5
FB_A4
FB_A3
EXTAL
FB_D15
FB_D14
FB_D13
FB_D12
EVDD
SDVDD
BOOT MOD1 BOOT MOD0
FB_A2
FB_A1
VDD_ VSS_ VDD_
XTAL
FB_D11
FB_D10
FB_D9
FB_D8
SDVDD
EVDD
FB_A0
FB_TA
VDD_ RTC_ EXTAL RTC_ XTAL VSS_
FB_BE/ BWE1
SD_DQS3
FB_BE/ BWE3
FB_D31
SDVDD
SDVDD
EVDD
IVDD
RESET
U0RTS
FB_D30
FB_D29
FB_D28
FB_D27
IVDD
SDVDD
SDVDD
EVDD
EVDD
JTAG_EN RSTOUT
U0CTS
U0RXD
FB_D26
FB_D25
FB_D24
SD_A10
FB_D17
FB_BE/ BWE0
FB_D4
FB_D0
PST3
DDATA3
U0TXD
VDD_
SD_CLK
SDR_DQS
FB_D23
FB_D20
FB_D16
FB_D7
FB_D3
FB_R/W
PST2
DDATA2
ADC_
ADC_IN1 ADC_IN0
SD_CLK
SD_CAS
FB_D22
FB_D19
FB_BE/ BWE2 DQS0
FB_D6
FB_D2
FB_OE
PST1
DDATA1
ADC_IN6 ADC_IN4 ADC_IN2
FB_CLK
SD_RAS
FB_D21
FB_D18
FB_D5
FB_D1
TCLK
PST0
DDATA0
TRST
ADC_IN7 ADC_IN5 ADC_IN3
Figure MCF52277 Pinout (196 MAPBGA)
Electrical Characteristics
This document contains electrical specification tables reference timing diagrams MCF5227x microprocessor. This section contains detailed information DC/AC electrical characteristics timing specifications. electrical specifications preliminary from previous designs design simulations. These specifications fully tested guaranteed this early stage product life cycle, however production silicon these specifications will met. Finalized specifications will published after complete characterization device qualifications have been completed.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Electrical Characteristics
NOTE
parameters specified this document supersede values found module specifications.
Maximum Ratings
Table Absolute Maximum Ratings1,
Characteristic Core Supply Voltage CMOS Supply Voltage DDR/Memory Supply Voltage Supply Voltage Digital Input Voltage
Symbol IVDD EVDD SDVDD PLLVDD Tstg
Value -0.5 +2.0 -0.3 +4.0 -0.3 +4.0 -0.3 +2.0 -0.3 +3.6 +150
Unit
Instantaneous Maximum Current Single limit (applies pins) Operating Temperature Range (Packaged) Storage Temperature Range
Functional operating conditions given Section 5.4, Electrical Specifications." Absolute maximum ratings stress ratings only, functional operation maxima guaranteed. Continued operation these levels affect device reliability cause permanent damage device. This device contains circuitry protecting against damage high static voltage electrical fields; however, advised that normal precautions taken avoid application voltages higher than maximum-rated voltages this high-impedance circuit. Reliability operation enhanced unused inputs tied appropriate logic voltage level (e.g., either EVDD). Input must current limited value specified. determine value required current-limiting resistor, calculate resistance values positive negative clamp voltages, then larger values. functional non-supply pins internally clamped EVDD. Power supply must maintain regulation within operating EVDD range during instantaneous operating maximum current conditions. positive injection current (Vin EVDD) greater than IDD, injection current flow EVDD could result external power supply going regulation. Insure external EVDD load will shunt current greater than maximum injection current. This will greatest risk when consuming power (ex; clock). Power supply must maintain regulation within operating EVDD range during instantaneous operating maximum current conditions.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
Thermal Characteristics
Table Thermal Characteristics
Characteristic Junction ambient, natural convection Junction ambient (@200 ft/min) Junction board Junction case Junction package Maximum operating junction temperature
Symbol Four layer board (2s2p) Four layer board (2s2p)
MAPBGA 471,2 431,2
LQFP
Unit °C/W °C/W °C/W °C/W °C/W
parameters simulated conformance with EIA/JESD Standard 51-2 natural convection. Freescale recommends power dissipation specifications system design prevent device junction temperatures from exceeding rated specification. System designers should aware that device junction temperatures significantly influenced board layout surrounding devices. Conformance device junction temperature specification verified physical measurement customer's system using parameter, device power dissipation, method described EIA/JESD Standard 51-2. JEDEC JESD51-6 with board horizontal. Thermal resistance between printed circuit board conformance with JEDEC JESD51-8. Board temperature measured surface board near package. Thermal resistance between case surface measured cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating temperature difference between package junction temperature JEDEC JESD51-2. When Greek letters available, thermal characterization parameter written conformance with Psi-JT.
average chip-junction temperature (TJ) obtained from:
Eqn.
Where:
QJMA PINT PI/O Ambient Temperature, Package Thermal Resistance, Junction-to-Ambient, °C/W PINT PI/O IVDD, Watts Chip Internal Power Power Dissipation Input Output Pins User Determined
most applications PI/O PINT ignored. approximate relationship between PI/O neglected)
Eqn.
Solving equations gives: 273°C
Eqn.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Electrical Characteristics
where constant pertaining particular part. determined from Equation measuring equilibrium) known Using this value values obtained solving Equation Equation iteratively value
Protection
Table Protection Characteristics1,2
Characteristic Target Human Body Model
Symbol
Value 2000
Unit
testing conformity with CDF-AEC-Q100 Stress Test Qualification Automotive Grade Integrated Circuits. device defined failure after exposure pulses device longer meets device specification requirements. Complete parametric functional testing performed applicable device specification room temperature followed temperature, unless specified otherwise device specification.
Electrical Specifications
Table Electrical Specifications
Characteristic Symbol IVDD PLLVDD EVDD SDVDD 2.25 USBVDD EVIH EVIL EVOH EVOL SDVIH 1.35 SDVIL 0.45 SDVDD SDVDD SDVDD EVDD 1.95 2.75 EVDD Unit
Core Supply Voltage Supply Voltage CMOS Supply Voltage SDRAM FlexBus Supply Voltage Mobile DDR/Bus Supply Voltage (nominal 1.8V) DDR/Bus Supply Voltage (nominal 2.5V) SDR/Bus Supply Voltage (nominal 3.3V) Supply Voltage CMOS Input High Voltage CMOS Input Voltage CMOS Output High Voltage -5.0 CMOS Output Voltage SDRAM FlexBus Input High Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Supply Voltage (nominal 2.5V) SDR/Bus Supply Voltage (nominal 3.3V) SDRAM FlexBus Input Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Supply Voltage (nominal 2.5V) SDR/Bus Supply Voltage (nominal 3.3V)
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table Electrical Specifications (continued)
Characteristic SDRAM FlexBus Output High Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Supply Voltage (nominal 2.5V) SDR/Bus Supply Voltage (nominal 3.3V) -5.0 modes SDRAM FlexBus Output Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Supply Voltage (nominal 2.5V) SDR/Bus Supply Voltage (nominal 3.3V) modes Input Leakage Current VSS, Input-only pins Weak Internal Pull-Up Device Current, tested Max.1 Input Capacitance input-only pins input/output (three-state) pins
Symbol SDVOH
Unit
SDVOL IAPU -1.0 -130
Refer signals section pins having weak internal pull-up devices. This parameter characterized before qualification rather than 100% tested.
Oscillator Electrical Characteristics
Table Electrical Characteristics
Characteristic Reference Frequency Range Crystal reference External reference Core/system frequency CLKOUT Frequency Crystal Start-up Time1,2 EXTAL Input High Voltage Crystal Mode3 other modes (External, Limp) EXTAL Input Voltage Crystal Mode3 other modes (External, Limp) Lock Time Duty cycle reference XTAL Current Total on-chip stray capacitance XTAL Total on-chip stray capacitance EXTAL Crystal capacitive load
Symbol fref_crystal fref_ext fsys fsys/2 tcst VIHEXT VIHEXT VILEXT VILEXT tlpll IXTAL CS_XTAL CS_EXTAL
VXTAL EVDD/2
66.67 66.67 166.67 83.33 VXTAL EVDD/2 50000
Unit CLKIN
crystal spec
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Electrical Characteristics
Table Electrical Characteristics (continued)
Characteristic Discrete load capacitance XTAL Discrete load capacitance EXTAL Symbol CL_XTAL CL_EXTAL CS_XTAL CS_EXTAL CS_PCB)5 Unit
Frequency un-LOCK Range Frequency LOCK Range CLKOUT period jitter measured fsys Peak-to-peak jitter (Clock edge clock edge) Long-term jitter frequency (fvco fref PFDR)
fLCK Cjitter
-4.0 -2.0
fsys fsys fsys/2 fsys/2
fvco
This parameter guaranteed characterization before qualification rather than 100% tested. Applies external clock reference only. Proper board layout procedures must followed achieve specifications. This parameter guaranteed design rather than 100% tested. This specification lock time only does include oscillator start-up time. CS_PCB measured stray capacitance EXTAL XTAL. Jitter average deviation from programmed frequency measured over specified interval maximum fsys. Measurements made with device powered filtered supplies clocked stable external clock signal. Noise injected into circuitry VDD, EVDD, variation crystal oscillator frequency increase Cjitter percentage given interval.
Electrical Characteristics
Table Electrical Characteristics
Characteristic Analog Supply Voltage Input Voltage Range Internal Reference Voltage Operating Current Consumption Power-down Current Consumption Resolution Sampling rate Integral Non-linearity Differential Non-linearity Internal Clock Frequency Conversion Range Conversion Time Sample Time tAIC tADC tADS Symbol VDDA VADIN VREF IDDA_ON IDDA_OFF VDDA VDDA Unit bits KS/s lsb1 lsb1 tAIC cycles tAIC cycles
Table lists electrical specifications module.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table Electrical Characteristics (continued)
Characteristic Multiplexer Settling Time Gain Error Offset Error Input Capacitance Input Leakage Current Input Current (Touchscreen enable)
Symbol tAMS CAIN IALEAK IIN_TS_E
Unit tAIC cycles lsb1 lsb1
lsb: least significant
5.6.1
Gain Calculations
Sample
ideal mapping input voltage output digital sample defined follows:
4095 SMAX
2480
3300
Figure Gain Calculations general, mapping function S=G*V Where input, output, slope. Nominal Gain 4095/3300 1.24mV-1 Eqn. Eqn.
5.7.1
External Interface Timing Specifications
FlexBus
multi-function external interface called FlexBus provided with basic functionality interface slave-only devices maximum frequency 66MHz. directly connected asynchronous synchronous devices such external boot ROMs, flash memories, gate-array logic, other simple target (slave) devices with little additional circuitry. asynchronous devices simple chip-select based interface used.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Electrical Characteristics
processor timings synchronous; that input setup/hold output delay given respect rising edge reference clock, FB_CLK. FB_CLK frequency same internal system frequency integer divider that frequency. following timing numbers indicate when data will latched driven onto external bus, relative Flexbus output clock, FB_CLK. other timing relationships derived from these values. Table FlexBus Timing Specifications
Frequency Operation
Characteristic
Symbol
83.33
Unit
Notes fsys/2 tcyc
Clock Period (FB_CLK) Address, Data, Control Output Valid (FB_A[23:0], FB_D[31:0], FB_CS[5:0], FB_R/W, FB_TS, FB_BE/BWE[3:0] FB_OE) Address, Data, Control Output Hold (FB_A[23:0], FB_D[31:0], FB_CS[5:0], FB_R/W, FB_TS, FB_BE/BWE[3:0], FB_OE) Data Input Setup Data Input Hold Transfer Acknowledge (TA) Input Setup Transfer Acknowledge (TA) Input Hold
tFBCK tFBCHDCV tFBCHDCI tDVFBCH tDIFBCH tCVFBCH tCIFBCH
12.0
Timing chip selects only applies FB_CS[5:0] signals. Please Section 5.7.2.2, "DDR SDRAM Timing Specifications," SD_CS[3:0] timing. FlexBus supports programming extension address hold. Please consult device reference manual more information.
NOTE
processor drives data lines during first clock cycle transfer with full 32-bit address. This ignored standard connected devices using non-multiplexed address data buses. However, some applications find this feature beneficial. address data busses muxed between FlexBus SDRAM controller. read write cycles address signals indeterminate.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
FB_CLK
ADDR[23:0] ADDR[31:X] DATA
FB_A[23:0] FB_D[31:X]
FB_R/W FB_TS FB_CSn, FB_OE, FB_BE/BWEn
FB_TA
Figure FlexBus Read Timing
FB_CLK
ADDR[23:0]
FB_A[23:0]
FB_D[31:X] FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB_TA
ADDR[31:X]
DATA
Figure Flexbus Write Timing
5.7.2
SDRAM
SDRAM controller supports accesses main SDRAM memory from internal master. supports either standard SDRAM double data rate (DDR) SDRAM, does support both same time.
5.7.2.1
SDRAM Timing Specifications
following timing numbers indicate when data will latched driven onto external bus, relative memory clock, when operating mode write cycles relative SD_DQS read cycles. device's SDRAM controller controller that mode. Because designed support DDR, pulse must still supplied device each data beat read. processor accomplishes this asserting signal named SD_SDR_DQS during
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Electrical Characteristics
read cycles. Care must taken during board design adhere following guidelines specs with regard SD_SDR_DQS signal usage. Table Timing Specifications
Characteristic Frequency Operation Clock Period Pulse Width High Pulse Width Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] Output Valid Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] Output Hold SD_SDR_DQS Output Valid SD_DQS[3:2] input setup relative SD_CLK SD_DQS[3:2] input hold relative SD_CLK Data (D[31:0]) Input Setup relative SD_CLK (reference only) SD10 Data Input Hold relative SD_CLK (reference only) SD11 Data (D[31:0]) Data Mask(SD_DQM[3:0]) Output Valid SD12 Data (D[31:0]) Data Mask (SD_DQM[3:0]) Output Hold
Symbol
83.33 0.55 0.55 SD_CLK Self timed 0.40 SD_CLK
Unit SD_CLK SD_CLK
Notes
tSDCK tSDCKH tSDCKH tSDCHACV tSDCHACI tDQSOV tDQVSDCH tDQISDCH tDVSDCH tDISDCH tSDCHDMV tSDCHDMI
12.0 0.45 0.45 0.25 SD_CLK
Does apply. fixed width. 0.25 SD_CLK SD_CLK
device supports same frequency operation both FlexBus SDRAM clock operates that internal clock. Please chapter device reference manual more information setting SDRAM clock rate. SD_CLK SDRAM clock Pulse width high plus pulse width cannot exceed clock period. SD_SDR_DQS designed pulse 0.25 clock before rising edge memory clock. This guideline only. Subtle variation from this guideline expected. SD_SDR_DQS will only pulse during read cycle pulse will occur each data beat. SD_DQS designed pulse 0.25 clock before rising edge memory clock. This spec guideline only. Subtle variation from this guideline expected. SD_DQS will only pulse during read cycle pulse will occur each data beat. SD_DQS pulse designed clock width. timing rising edge most important. falling edge does affect memory controller. Since read cycle mode still uses circuit within device, critical that data valid window centered after rising edge DQS. Ensuring that this happens will result successful reads. input setup spec provided guidance.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
SD_CLK
SD_CSn SD_RAS SD_CAS SD_WE A[23:0] SD_BA[1:0]
SD11 SDDM SD12 D[31:0]
Figure Write Timing
SD_CLK SD_CSn, SD_RAS, SD_CAS, SD_WE A[23:0], SD_BA[1:0]
MCLK Reference
tDQS
SDDM SD_SDR_DQS
(Measured Output Pin) Board Delay
SD_DQS[3:2]
(Measured Input Pin) Board Delay
Delayed SD_CLK D[31:0] from Memories
NOTE: Data driven from memories relative delayed memory clock.
SD10
Figure Read Timing
5.7.2.2
SDRAM Timing Specifications
When using SDRAM controller mode, following timing numbers must followed properly latch drive data onto memory bus. timing numbers relative byte lanes.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Electrical Characteristics
Table Timing Specifications
Characteristic Frequency Operation Clock Period Pulse Width High Pulse Width Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] Output Valid Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] Output Hold Write Command first Latching Transition Data Data Mask Output Setup (DQDQS) Relative (DDR Write Mode) Data Data Mask Output Hold (DQSDQ) Relative (DDR Write Mode) Input Data Skew Relative (Input Setup) Symbol tDDCK tDDSK tDDCKH tDDCKL tSDCHACV tSDCHACI tCMDVDQ tDQDMV tDQDMI tDVDQ tDIDQ 12.0 0.45 0.45 0.25 SD_CLK 0.5ns 83.33 0.55 0.55 SD_CLK 1.25 Unit SD_CLK SD_CLK SD_CLK
Notes
DD10 Input Data Hold Relative
DD11 falling edge from SDCLK rising (output hold time) tDQLSDCH
frequency operation either FB_CLK frequency operation. FlexBus SDRAM clock operate same frequency internal clock. SD_CLK SDRAM clock Pulse-width high plus pulse-width cannot exceed minimum maximum clock period. Command output valid should one-half memory clock (SD_CLK) plus some minor adjustments process, temperature, voltage variations. This specification relates required input setup time today's memories. device's output setup should larger than input setup memories. larger, then input setup memory will violation. MEM_DATA[31:24] relative MEM_DQS[3], MEM_DATA[23:16] relative MEM_DQS[2], MEM_DATA[15:8] relative MEM_DQS[1], MEM_DATA[7:0] relative MEM_DQS[0]. first data beat will valid before first rising edge after write preamble. remaining data beats will valid each subsequent edge. This specification relates required hold time today's memories. MEM_DATA[31:24] relative MEM_DQS[3], MEM_DATA[23:16] relative MEM_DQS[2], MEM_DATA[15:8] relative MEM_DQS[1], MEM_DATA[7:0] relative MEM_DQS[0]. Data input skew derived from each clock edge. begins with transition ends when last data line becomes valid. This input skew must include memory output skew system-level board skew (due routing other factors). Data input hold derived from each clock edge. begins with transition ends when first data line becomes invalid.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
SD_CLK
SD_CLK
SD_CSn, SD_WE, SD_RAS, SD_CAS
A[13:0]
DD11 SD_DQS[3:2] SD_DM[3:2]
D[31:16]
Figure Write Timing
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Electrical Characteristics
SD_CLK
SD_CLK
SD_CSn,SD_WE, SD_RAS, SD_CAS A[13:0]
CL=2
CL=2.5
SD_DQS3/SD_DQS2
Read Preamble
Read Postamble
DD10 D[31:24]/D[23:16]
Read Preamble Read Postamble
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
Figure Read Timing Table Clock Crossover Specifications
Symbol VOUT
Characteristic Clock output mid-point voltage Clock output voltage level Clock output differential voltage (peak peak swing) Clock crossing point voltage1
1.05 -0.3 1.05
1.45 SD_VDD SD_VDD 1.45
Unit
clock crossover voltage only guaranteed when using highest drive strength option SDCLK[1:0] SDCLK[1:0] signals.
SD_CLK SD_CLK
Figure SD_CLK SD_CLK Crossover Timing
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
General Purpose Timing
Table GPIO Timing1
Characteristic FB_CLK High GPIO Output Valid FB_CLK High GPIO Output Invalid GPIO Input Valid FB_CLK High FB_CLK High GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Unit
These general purpose specifications apply following signals: IRQn, UART signals, FlexCAN signals, signals, DACKn DREQn, signals configured GPIO.
FB_CLK
GPIO Outputs
GPIO Inputs
Figure GPIO Timing
Reset Configuration Override Timing
Table Reset Configuration Override Timing
Characteristic RESET Input valid FB_CLK High FB_CLK High RESET Input invalid RESET Input valid Time
Symbol tRVCH tCHRI tRIVT tCHROV tROVCV tCOS tCOH tROICZ
Unit tCYC tCYC tCYC
FB_CLK High RSTOUT Valid RSTOUT valid Config. Overrides valid Configuration Override Setup Time RSTOUT invalid Configuration Override Hold Time after RSTOUT invalid RSTOUT invalid Configuration Override High Impedance
During power STOP, synchronizers RESET input bypassed RESET asserted asynchronously system. Thus, RESET must held minimum
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Electrical Characteristics
FB_CLK
RESET
RSTOUT
Configuration Overrides*: (RCON, Override pins)
Figure RESET Configuration Override Timing
NOTE
Refer chapter MCF52277 Reference Manual more information.
5.10
Controller Timing Specifications
Table LCD_LSCLK Timing
LCD_LSCLK Period Pixel data setup time Pixel data time Characteristic 2000 Unit
This sections lists timing specifications Controller.
Note: pixel clock equal LCD_LSCLK (PCD When CSTN, TFT, monochrome mode with width LCD_LSCLK equal pixel clock. When monochrome with other width settings, LCD_LSCLK equal pixel clock divided width. polarity LCD_LSCLK LCD_D signals also programmed.
LCD_LSCLK
LCD_D[17:0]
Figure LCD_LSCLK LCD_D[17:0] timing diagram
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
Non-display Region
Display Region
LCD_VSYNC LCD_HSYNC LCD_OE LCD_D[17:0]
Line
Line
Line
LCD_HSYNC LCD_LSCLK LCD_OE LCD_D[15:0]
XMAX
(1,1)
(1,2)
(1,X)
Figure 4/8/12/16/18 Bit/Pixel Color Mode Panel Timing Table 4/8/12/16/18 Bit/Pixel Color Mode Panel Timing
Characteristic LCD_OE beginning LCD_VSYNC LCD_HSYNC period LCD_VSYNC pulse width LCD_VSYNC beginning LCD_OE LCD_HSYNC pulse width LCD_HSYNC beginning LCD_OE LCD_OE beginning LCD_HSYNC Value (VWAIT1 XMAX+T5+T6+T7 VWIDTH (VWAIT2 T2)+1 HWIDTH HWAIT2 HWAIT1 Unit
Note: LCD_LSCLK period. LCD_VSYNC, LCD_HSYNC, LCD_OE programmed active high active low. Figure signals active low. LCD_LSCLK programmed deactivated during LCD_VSYNC pulse LCD_OE deasserted period. Figure LCD_LSCLK always active. Note: XMAX defined number pixels line.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Electrical Characteristics
XMAX
LCD_LSCLK
LCD_D
D320
D320
LCD_SPL_SPR LCD_HSYNC LCD_CLS
LCD_PS LCD_REV
Figure Sharp Panel Timing Table Sharp Panel Timing
Characteristic LCD_SPL/LCD_SPR pulse width LCD_D line beginning LCD_HSYNC LCD_HSYNC beginning LCD_D line LCD_CLS rise delay from LCD_D line LCD_CLS pulse width LCD_PS rise delay from LCD_CLS negation LCD_REV toggle delay from last LCD_D line Value HWAIT1+1 HWAIT2 CLS_RISE_DELAY+1 CLS_HI_WIDTH+1 PS_RISE_DELAY REV_TOGGLE_DELAY+1 Unit
Note: Falling LCD_SPL/LCD_SPR aligns with first LCD_D line. Note: Falling LCD_PS aligns with rising edge LCD_CLS. Note: LCD_REV toggles every LCD_HSYN period.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
LCD_VSYNC LCD_HSYNC XMAX
LCD_LSCLK LCD_D[15:0]
Figure Non-TFT Mode Panel Timing Table Non-TFT Mode Panel Timing
Characteristic LCD_HSYNC LCD_VSYNC delay LCD_HSYNC pulse width LCD_VSYNC LCD_LSCLK LCD_LSCLK LCD_HSYNC Value HWAIT2 HWIDTH HWAIT1 Unit Tpix Tpix Tpix
Note: LCD_LSCLK period while Tpix pixel clock period. LCD_VSYNC, LCD_HSYNC, LCD_LSCLK programmed active high active low. Figure these signals active high. When CSTN mode monochrome mode with width Tpix When monochrome mode with width Tpix respectively.
5.11
On-The-Go Specifications
Table On-Chip Transceiver Characteristics
Characteristic Input High Input Input Differential Differential Common Mode Range Single Ended Receive Threshold Single Ended Receive Hysteresis Output High Output Differential Output Crossover Driven Driven Condition Driven Symbol VSETHR VSEHYS VCRS Unit
MCF5227x device compliant with industry standard specification.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Electrical Characteristics
Table On-Chip Transceiver Characteristics (continued)
Characteristic side Impedance side Impedance Impedance Matching Pulldown Resistance1
Condition Driven Driven
Symbol ZMatching
6.25 6.25
8.25 8.25 0.17
11.25 11.25 0.23
Unit
pulldown resistors included provide method keep signals known quiescent state desired when port being used when cable connected. These on-chip resistors should used provide 15-k host-mode pulldowns called Chapter Specification, Rev. Rev. 2.0.
Table On-Chip Transceiver Full Speed Characteristics
Characteristic Rise Time Fall Time Rise/Fall Matching Rise/Fall Matching, TIme Skew Between Condition 10-90% 90-10% Symbol Matching Pad-to-Pad tSKE 17.5 17.5 Unit
Table On-Chip Transceiver Speed Characteristics
Characteristic Rise Time Fall Time Rise/Fall Matching Condition 10-90% 90-10% Symbol Matching Unit
5.12
Timing Specifications
This section provides timings master (clocks driven) slave modes (clocks input). timings given non-inverted serial clock polarity (SSI_TCR[TSCKP] SSI_RCR[RSCKP] non-inverted frame sync (SSI_TCR[TFSI] SSI_RCR[RFSI] polarity clock and/or frame sync have been inverted, timings remain valid inverting clock signal (SSI_BCLK) and/or frame sync (SSI_FS) shown figures below. Table Timing-Master Modes1
Characteristic SSI_MCLK cycle time SSI_MCLK pulse width high SSI_BCLK cycle time SSI_BCLK pulse width tBCLK Symbol tMCLK tSYS tSYS Unit tMCLK tBCLK
Notes
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table Timing-Master Modes1 (continued)
Characteristic SSI_BCLK SSI_FS output valid SSI_BCLK SSI_FS output invalid SSI_BCLK SSI_TXD valid SSI_BCLK SSI_TXD invalid high impedence SSI_RXD SSI_FS input setup before SSI_BCLK SSI_RXD SSI_FS input hold after SSI_BCLK
Symbol
Unit
Notes
timings specified with capactive load 25pF. SSI_MCLK generated from SSI_CLKIN divided version internal system clock (SYSCLK). SSI_BCLK derived from SSI_CLKIN divided version SYSCLK. SYSCLK used, minimum divider SSI_CLKIN input used, programmable dividers must ensure that SSI_BCLK does exceed fSYS.
Table Timing-Slave Modes1
Characteristic SSI_BCLK cycle time SSI_BCLK pulse width high SSI_FS input setup before SSI_BCLK SSI_FS input hold after SSI_BCLK SSI_BCLK SSI_TXD SSI_FS output valid SSI_BCLK SSI_TXD SSI_FS output invalid high impedence SSI_RXD setup before SSI_BCLK SSI_RXD hold after SSI_BCLK
Symbol tBCLK
tSYS
Unit tBCLK
Notes
timings specified with capactive load
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Electrical Characteristics
SSI_MCLK (Output)
SSI_BCLK (Output)
SSI_FS (Output)
SSI_FS (Input)
SSI_TXD
SSI_RXD
Figure Timing-Master Modes
SSI_BCLK (Input)
SSI_FS (Output)
SSI_FS (Input)
SSI_TXD
SSI_RXD
Figure Timing-Slave Modes
5.13
Timing Specifications
Table Input Timing Specifications between
Start condition hold time Clock period I2C_SCL/I2C_SDA rise time (VIL Data hold time Characteristic Unit tcyc tcyc
Table lists specifications input timing parameters shown Figure
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table Input Timing Specifications between (continued)
Characteristic I2C_SCL/I2C_SDA fall time (VIH Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Unit tcyc tcyc tcyc
Table lists specifications output timing parameters shown Figure Table Output Timing Specifications between
Characteristic Start condition hold time Clock period I2C_SCL/I2C_SDA rise time (VIL Data hold time I2C_SCL/I2C_SDA fall time (VIH Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Unit tcyc tcyc tcyc tcyc tcyc tcyc tcyc
Output numbers depend value programmed into IFDR; IFDR programmed with maximum frequency (IFDR 0x20) results minimum output timings shown Table interface designed scale actual data transition time move middle period. actual position affected prescale division values programmed into IFDR; however, numbers given Table minimum values. Because I2C_SCL I2C_SDA open-collector-type outputs, which processor only actively drive low, time I2C_SCL I2C_SDA take reach high level depends external signal capacitance pull-up resistor values. Specified nominal 50-pF load.
Figure shows timing values Table Table
I2C_SCL I2C_SDA
Figure Input/Output Timings
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Electrical Characteristics
5.14
Timer Timing Specifications
Table Timer Module Timing Specifications
Characteristic DT0IN DT1IN DT2IN DT3IN cycle time DT0IN DT1IN DT2IN DT3IN pulse width Unit tCYC tCYC
Table lists timer module timings.
5.15
DSPI Timing Specifications
Serial Peripheral Interface (DSPI) provides synchronous serial with both master slave operations. Many transfer attributes programmable. Table provides DSPI timing characteristics classic timing modes. Refer DSPI chapter MCF52277 Reference Manual information modified transfer formats used communicating with slower peripheral devices. Table DSPI Module Timing Specifications1
Characteristic DSPI_SCK Cycle Time DSPI_SCK Duty Cycle Symbol tSCK tSYS (tsck (tsck Unit Notes
Master Mode DSPI_PCSn DSPI_SCK delay DSPI_SCK DSPI_PCSn delay DSPI_SCK DSPI_SOUT valid DSPI_SCK DSPI_SOUT invalid DSPI_SIN DSPI_SCK input setup DSPI_SCK DSPI_SIN input hold tCSC tASC tSYS) tSYS)
Slave Mode DS10 DS11 DS12 DS13 DS14
DSPI_SCK DSPI_SOUT valid DSPI_SCK DSPI_SOUT invalid DSPI_SIN DSPI_SCK input setup DSPI_SCK DSPI_SIN input hold DSPI_SS active DSPI_SOUT driven DSPI_SS inactive DSPI_SOUT driven
Timings shown DMCR[MTFE] (classic SPI) DCTARn[CPHA] Data sampled DSPI_SIN odd-numbered DSPI_SCK edges driven DSPI_SOUT even-numbered DSPI edges. When master mode, baud rate programmable DCTARn[PBR] DCTARn[BR]. DSPI_PCSn DSPI_SCK delay programmable DCTARn[PCSSCK] DCTARn[CSSCK]. DSPI_SCK DSPI_PCSn delay programmable DCTARn[PASC] DCTARn[ASC].
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
DSPI_PCSn
DSPI_SCK (DCTARn[CPOL]
DSPI_SCK (DCTARn[CPOL]
DSPI_SIN
First Data
Data
Last Data
Data Last Data
DSPI_SOUT
First Data
Figure DSPI Classic Timing-Master Mode
DSPI_SS
DSPI_SCK (DCTARn[CPOL]
DSPI_SCK (DCTARn[CPOL]
DS13 DS10 First Data DS11 DS12 Data Last Data Data
DS14
DSPI_SOUT
Last Data
DSPI_SIN
First Data
Figure DSPI Classic Timing-Slave Mode
5.16
Timing Specifications
Serial Boot Facility (SBF) provides means read configuration information system boot code from broad array SPI-compatible EEPROMs, flashes, FRAMs, nVSRAMs, etc. Table provides timing specifications SBF.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Electrical Characteristics
Table Timing Specifications
Characteristic SBF_CK Cycle Time SBF_CK High/Low Time SBF_CS SBF_CK delay SBF_CK SBF_CS delay SBF_CK SBF_DO valid SBF_CK SBF_DO invalid SBF_DI SBF_SCK input setup SBF_CK SBF_DI input hold
Symbol tSBFCK
tSBFCK tSBFCK
Unit tSBFCK
Notes
reset, SBF_CK cycle time tREF first byte data read from serial memory contains divider value that used SBF_CK cycle time duration serial boot process.
SBF_CK
SBF_CS
Data Last Data Data Last Data
SBF_DI
First Data
SBF_DO
First Data
Figure Timing
5.17
JTAG Boundary Scan Timing Specifications
Table JTAG Boundary Scan Timing
Characteristic1 TCLK Frequency Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise Fall Times Boundary Scan Input Data Setup Time TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Boundary Scan Output Data Valid TCLK Boundary Scan Output High Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ Unit fsys/2 tCYC
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table JTAG Boundary Scan Timing (continued)
Characteristic1 TMS, Input Data Setup Time TCLK Rise TMS, Input Data Hold Time after TCLK Rise TCLK Data Valid TCLK High TRST Assert Time TRST Setup Time (Negation) TCLK High
Symbol tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST
Unit
JTAG_EN expected static signal. Hence, specific timing associated with
TCLK (input)
Figure Test Clock Input Timing
TCLK
Data Inputs
Input Data Valid
Data Outputs
Output Data Valid
Data Outputs
Data Outputs
Output Data Valid
Figure Boundary Scan (JTAG) Timing
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
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Information this document provided solely enable system software implementers Freescale Semiconductor products. There express implied copyright licenses granted hereunder design fabricate integrated circuits integrated circuits based information this document. Freescale Semiconductor reserves right make changes without further notice products herein. Freescale Semiconductor makes warranty, representation guarantee regarding suitability products particular purpose, does Freescale Semiconductor assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters that provided Freescale Semiconductor data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals", must validated each customer application customer's technical experts. Freescale Semiconductor does convey license under patent rights rights others. Freescale Semiconductor products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Freescale Semiconductor product could create situation where personal injury death occur. Should Buyer purchase Freescale Semiconductor products such unintended unauthorized application, Buyer shall indemnify hold Freescale Semiconductor officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Freescale Semiconductor negligent regarding design manufacture part. RoHS-compliant and/or Pb-free versions Freescale products have functionality electrical characteristics their non-RoHS-compliant and/or non-Pb-free counterparts. further information, http://www.freescale.com contact your Freescale sales representative. information Freescale's Environmental Products program, http://www.freescale.com/epp. Freescaleand Freescale logo trademarks Freescale Semiconductor, Inc. other product service names property their respective owners. Freescale Semiconductor, Inc. 2008. rights reserved.
Document Number: MCF52277
Rev. 07/2008
Preliminary-Subject Change Without Notice
Electrical Characteristics
TCLK
Input Data Valid
Output Data Valid
Output Data Valid
Figure Test Access Port Timing
TCLK
TRST
Figure TRST Timing
5.18
Debug Timing Specifications
Table Debug Timing Specification
Table lists specifications debug timing parameters shown Figure
Characteristic PSTCLK cycle time PSTCLK rising PSTDDATA valid PSTCLK rising PSTDDATA invalid DSI-to-DSCLK setup DSCLK-to-DSO hold DSCLK cycle time BKPT assertion time
Units tSYS PSTCLK PSTCLK PSTCLK PSTCLK
DSCLK synchronized internally. measured from synchronized DSCLK input relative rising edge PSTCLK.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Package Information
PSTCLK
PSTDDATA[7:0]
Figure Real-Time Trace Timing
DSCLK
Current
Next
Past
Current
Figure Serial Port Timing
Package Information
latest package outline drawings available product summary pages site: following table lists case outline numbers device. these numbers page's keyword search engine find latest package outline drawings. Table Package Information
Device MCF52274 MCF52277 Package Type LQFP MAPBGA Case Outline Numbers 98ASS23479W 98ASH98061A
Product Documentation
Documentation available from local Freescale distributor, Freescale sales office, Freescale Literature Distribution Center, through Freescale world-wide address
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Revision History
Revision History
Table MCF52277 Data Sheet Revision History
Rev. Date Release 02/2008 05/2008 07/2008 07/2008 Initial public revision. Corrected MCF52274 order number from MCF52274CAB120 MCF52274CLU120 Table Corrected MCF52277CVM166 part number MCF52277CVM160 Table Although, this device maximum rated frequency 166.67 MHz. Added data Section 3.5, "Power Consumption Specifications." Summary Changes
Table summarizes revisions this document.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Reach Home Page: www.freescale.com Support: USA/Europe Locations Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 +1-480-768-2130 www.freescale.com/support Europe, Middle East, Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 81829 Muenchen, Germany 1296 (English) 52200080 (English) 92103 (German) (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center King Street Industrial Estate N.T., Hong Kong +800 2666 8080 support.asia@freescale.com Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. 5405 Denver, Colorado 80217 1-800-441-2447 303-675-2140 Fax: 303-675-2150
Information this document provided solely enable system software implementers Freescale Semiconductor products. There express implied copyright licenses granted hereunder design fabricate integrated circuits integrated circuits based information this document. Freescale Semiconductor reserves right make changes without further notice products herein. Freescale Semiconductor makes warranty, representation guarantee regarding suitability products particular purpose, does Freescale Semiconductor assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters that provided Freescale Semiconductor data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals", must validated each customer application customer's technical experts. Freescale Semiconductor does convey license under patent rights rights others. Freescale Semiconductor products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Freescale Semiconductor product could create situation where personal injury death occur. Should Buyer purchase Freescale Semiconductor products such unintended unauthorized application, Buyer shall indemnify hold Freescale Semiconductor officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Freescale Semiconductor negligent regarding design manufacture part. RoHS-compliant and/or Pb-free versions Freescale products have functionality electrical characteristics their non-RoHS-compliant and/or non-Pb-free counterparts. further information, http://www.freescale.com contact your Freescale sales representative. information Freescale's Environmental Products program, http://www.freescale.com/epp. Freescaleand Freescale logo trademarks Freescale Semiconductor, Inc. other product service names property their respective owners. Freescale Semiconductor, Inc. 2008. rights reserved.
Document Number: MCF52277
Rev. 07/2008
Preliminary-Subject Change Without Notice

MCF52277 LQFP-176 MAPBGA-196 15mm 15mm MCF5227x ColdFire® Mi

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