High current 3-phase gate drive N-channel MOSFETs Cross-conduction pro

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High current 3-phase gate drive N-channel MOSFETs Cross-conduction pro

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A4935 Automotive 3-Phase MOSFET Driver
High current 3-phase gate drive N-channel MOSFETs Cross-conduction protection with adjustable dead time Top-off charge pump 100% Charge pump supply voltage operation Uncommitted current sense amplifier supply voltage range Compatible with logic Extensive diagnostic outputs Low-current sleep mode
A4935 3-phase controller with N-channel external power MOSFETs specifically designed automotive applications. unique charge pump regulator provides full (>10 gate drive battery voltages down allows A4935 operate with reduced gate drive, down bootstrap capacitor used provide above-battery supply voltage required N-channel MOSFETs. internal charge pump high-side drive allows (100% duty cycle) operation. Full control over power FETs 3-phase bridge provided, allowing motors driven with block commutation sinusoidal excitation. power FETs protected from shoot-through integrated crossover control resistoradjustable dead time. Bridge current measured using integrated current sense amplifier. This uncommitted differential amplifier with below-ground common mode range allowing used low-side current sense applications. Gain offset defined external resistors.
Continued next page.
Package: 48-pin LQFP with exposed thermal (suffix
scale
Typical Application
VBAT
A8450
Regulator
VBAT
Control Microcontroller
A4935
3-Phase BLDC Motor
Diagnostics
Current Sense
4935-DS
A4935
Description (continued)
Automotive 3-Phase MOSFET Driver
A4935 supplied 48-pin LQFP with exposed thermal pad, (suffix JP). This small footprint mm2) power package. lead (Pb) free with 100% matte leadframe plating.
Integrated diagnostics provide indication undervoltage, overtemperature, power bridge faults. They configured protect power FETs under most short circuit conditions. Detailed diagnostics available serial data word.
Selection Guide
Part Number
A4935KJP-T
Packing
pieces tray
Absolute Maximum Ratings*
Characteristic Load Supply Voltage Logic Supply Voltage VREG Logic Inputs Outputs VDSTH RDEAD VDRAIN GHA, GHB, GLA, GLB, Operating Temperature Range Junction Temperature Transient Junction Temperature Storage Temperature Range Rating, Human Body Model Rating, Charged Device Model *With respect AGND. TJ(max) Tstg AEC-Q100-002, pins AEC-Q100-011, pins Overtemperature event exceeding lifetime duration exceeding guaranteed design characterization Range Symbol Notes Rating -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Sx+15 -0.3 Sx+15 2000 1050 Units
THERMAL CHARACTERISTICS require derating maximum conditions
Characteristic Package Thermal Resistance Symbol *Additional thermal information available Allegro website. Test Conditions* 4-layer based JEDEC standard 2-layer with in.2 copper area each side Value Units
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4935
Automotive 3-Phase MOSFET Driver
Functional Block Diagram
Battery
Logic Supply
Charge Pump Regulator
VREG CREG
VBAT
COAST PWMH PWML
Charge Pump Bootstrap Monitor
VDRAIN
CBOOTA RGATE
Control Logic
High Side Drive
VREG CCEN RESET RDEAD Diagnostics Protection UVLO, Short Supply Short Short Load VDSTH AGND CSOUT Phase (repeated Side Drive RGATE Phase Phase
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4935
Automotive 3-Phase MOSFET Driver
ELECTRICAL CHARACTERISTICS valid -40°C 150°C, unless noted otherwise Characteristics Supply Reference
Load Supply Voltage Functional Operating Range1 Load Supply Quiescent Current Logic Supply Voltage Logic Supply Quiescent Current IBBQ IBBS IDDQ IDDS RESET high, outputs RESET IREG IREG VREG Output Voltage VREG IREG IREG Bootstrap Diode Forward Voltage Bootstrap Diode Resistance Bootstrap Diode Current Limit Top-off Charge Pump Current Limit High-Side Gate Drive Static Load Resistance VfBOOT IDBOOT ITOCPM RGSH RDS(on)UP RDS(on)DN VGHX VGLX tP(off) tP(on) Input change unloaded gate output change Input change unloaded gate output change Measured between corresponding transition points sequential phases Measured across phase CLOAD CLOAD 25°C, IGHx -150 150°C, IGHx -150 25°C, IGLx 150°C, IGLx Bootstrap capacitor fully charged rD(100mA) (VfBOOT(150mA) VfBOOT(50mA)) RESET high, outputs low, RESET low, Sleep mode, 12.5 12.5 VREG 13.80 13.80
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Gate Output Drive
Turn-On Time Turn-Off Time Pullup Resistance Pulldown Resistance Output Voltage Output Voltage Turn-Off Propagation Delay2 Turn-On Propagation Delay2 Propagation Delay Matching, Phase-to-Phase Propagation Delay Matching, On-to-Off
Continued next page.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4935
Automotive 3-Phase MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued) valid -40°C 150°C, unless noted otherwise Characteristics Symbol Test Conditions
RDEAD tied RDEAD Dead Time2 tDEAD RDEAD RDEAD RDEAD tied
Min.
-200
Typ.
Max.
1110
Units
V/°C
Logic Inputs Outputs
Fault Output Fault Output Leakage RDEAD Input Voltage RDEAD Current3 Current3 VFF(L) IFF(H) VDEAD(L) IDEAD VIN(L) VIN(H) VINhys CCEN)3 tRES VILC VIHC VIChys Delay4 IBIAS VIOS VIOS Vopn Vclos CSN, -1.3 range range RDEAD fault present fault present
Input Voltage Input High Voltage Input Hysteresis Input Current (Except RESET RESET Pulse Time4 RESET Delay4 Clock Input High Voltage Clock Input Voltage Clock Input Hysteresis Clock Valid Data Clock High Time4 Clock Time4 Clock Fault Reset Delay4 Input Pulldown Resistor (RESET CCEN)
-VDD -1.5
Current Sense Differential Amplifier
Differential Input Voltage Input Bias Current3 Input Offset Current3 Input Offset Voltage Input Offset Voltage Drift Input Common Mode Range Open Loop Gain Closed Loop Gain
Continued next page.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4935
Automotive 3-Phase MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued) valid -40°C 150°C, unless noted otherwise Characteristics
Small Signal Frequency Bandwidth Settling Time Output Dynamic Range Output Current Sink Output Current Source VREG Supply Ripple Rejection Common Mode Rejection Common Mode Rejection Common Mode Recovery Time Output Slew Rate Input Overload Recovery
Symbol
tSETTLE VCSOUT ICSsink ICSsource PSRR CMRR CMRR tCMrec tIDrec
Test Conditions
mVpp, within steady state, VCSOUT square wave -100 ICSOUT -400 VCSOUT VCSOUT AGND, step mVpp, within steady state, step within 90%, step within steady state, step VREG rising VREG falling with respect falling
Min.
Typ.
Max.
Units
Protection
VREG Undervoltage Lockout Threshold Bootstrap Undervoltage Threshold Bootstrap Undervoltage Hysteresis Undervoltage Turn-Off Threshold Undervoltage Hysteresis VDSTH Input Range VDSTH Input Current VDRAIN Input Voltage VDRAIN Input Current Short-to-Ground Threshold Offset5 Short-to-Battery Threshold Offset6 Overtemperature Fault Flag Threshold Overtemperature Fault Hysteresis
1Functions
VREGUVon VREGUVoff VBOOTUV VBOOTUVhys VDDUV VDDUVhys VDSTH IDSTH VDRAIN IDRAIN VSTGO VSTBO TJFhys
6.75 2.45
7.25 ±100 ±100
7.75 2.85
%VREG %VREG
VDSTH VDSTH VDRAIN High-side VDSTH High-side VDSTH Low-side VDSTH Low-side VDSTH Temperature increasing Recovery TJFhys
-150 -150
correctly, parameters guaranteed, below general limits 2See Gate Drive Timing diagrams. 3For input output current specifications, negative current defined coming (sourcing) specified device pin. 4See Fault Output Timing diagram. decreases, fault occurs VBAT -VSx VSTG. threshold, VSTG VDSTH VSTGO increases, fault occurs VLSS VSTB threshold, VSTB VDSTH+VSTBO
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4935
Automotive 3-Phase MOSFET Driver
Timing Diagrams
tDEAD tP(off) tP(off) Synchronous Rectification tDEAD High-Side tP(on) tP(off) tP(on) tP(off) Low-Side
Gate Drive Timing, Phase Control Inputs
PWMH tP(off) tDEAD tP(off) tDEAD
PWML tDEAD tP(off) tDEAD PWMH tP(off)
PWML
Gate Drive Timing, Inputs
COAST tP(off) PWMH PWML tP(on)
COAST tP(off) PWMH PWML tP(on)
Gate Drive Timing, COAST Inputs
Gate Drive
Disabled
Enabled
Gate Drive
Disabled Enabled
tRES RESET Fault Register Read RESET Simple Fault Reset
Fault Output Timing
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4935
Automotive 3-Phase MOSFET Driver
Functional
A4935 three-phase MOSFET driver (pre-driver) with separate supplies logic, analog drive sections. This permits operation with regulated logic supply from with unregulated main supply high current gate drives capable driving wide range N-channel power MOSFETs, configured three high-side drives three low-side drives. Each drive controlled with logic level input compatible with logic. A4935 provides necessary circuits ensure that gate-source voltage both high-side low-side external FETs above supply voltages down extreme battery voltage drop conditions, correct functional operation guaranteed supply voltages down with reduced gate drive voltage. control inputs A4935 provide very flexible solution many motor control applications. full sinusoidal excitation, each phase driven with independent signal. less complex drive solutions, inputs, PWML PWMH, allow simple high-side, low-side, fast-decay control with single signal. current sense amplifier allows motor current sensed low-value sense resistor ground connection power bridge. A4935 includes number protection features against undervoltage, overtemperature, power bridge faults. Fault states enable responses device external controller, depending fault condition logic settings. fault flag outputs, FF2, provided signal detected faults external controller. Diagnostics include internal fault register, which accessed serial read using fault flag pins.
This provides very rugged solution harsh automotive environment.
Gate Drives A4935 designed drive external, on-resistance, power N-channel MOSFETs. supplies large transient currents necessary quickly charge discharge external gate capacitance order reduce dissipation external during switching. charge discharge rate controlled using external resistor series with connection gate FET.
Gate Drive Voltage Regulation gate drives powered
internal regulator which limits supply drives therefore maximum gate voltage. When supply greater than about regulator simple linear regulator. Below regulated supply maintained charge pump boost converter, which requires pump capacitor connected between pins. This capacitor must have minimum value typically regulated voltage, nominally available VREG pin. sufficiently large storage capacitor must connected this provide transient charging current low-side drives bootstrap capacitors.
Top-off Charge Pump additional top-off charge pump
Power Supplies power supply voltages required, logic interface analog output drive sections. Both supplies should decoupled with ceramic capacitors connected close supply ground pins. logic supply, connected VDD, allows flexibility logic interface. main power supply should connected through reverse voltage protection circuit. A4935 operates within specified parameters with supply from functions correctly with supply down
provided each phase. charge pumps allow high-side drives maintain gate voltage external FETs indefinitely, ensuring so-called 100% required. This current trickle charge pump, operated only after high-side been signaled turn floating high-side gate drive requires small bias current (<20 maintain highlevel output. Without top-off charge pump, this bias current would drawn from bootstrap capacitor through pin. charge pump provides sufficient current ensure that bootstrap voltage thereby gate-source voltage maintained necessary level. Note that charge required initial turn-on high-side gate always supplied bootstrap capacitor. bootstrap capacitor becomes discharged, top-off charge pump will provide sufficient current allow turn
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4935
Automotive 3-Phase MOSFET Driver
some applications safety resistor added between gate source each bridge. When high-side held on-state, current through associated high-side gate-source resistor (RGSH) provided high-side drive therefore appears static resistive load top-off charge pump. minimum value RGSH which top-off charge pump provide current shown Electrical Characteristics table.
GLA, GLB, Pins These low-side gate drive
This low-side return path discharge
capacitance gates. should tied directly common sources low-side external FETs through independent impedance connection.
RDEAD This controls internal generation dead time
during switching. When resistor greater than connected between RDEAD AGND, cross-conduction prevented gate drive circuits, which introduce dead time, tDEAD between switching complementary dead time derived from resistor value connected between RDEAD AGND pins. When RDEAD connected directly VDD, cross-conduction prevented gate drive circuits. this case, tDEAD defaults value typical. When RDEAD connected directly AGND, internal dead time generation disabled. This allows dead times duration determined external controller through relative timing phase logic control inputs, xLO. Note that when using external controller determine dead time, care must taken ensure that unintentional shorts across supply avoided. Logic Control Inputs voltage-level digital inputs provide control gate drives. input logic shown table These logic inputs driven from either logic. have nominal hysteresis improve noise performance.
AHI, BHI, CHI, ALO, BLO, Pins These phase
outputs external N-channel MOSFETs. External resistors between gate drive output gate connection close possible FET) used control slew rate seen gate, thereby providing some control di/dt dv/dt outputs. going high turns upper half drive, sourcing current gate lowside external power bridge, turning going turns lower half drive, sinking current from external gate circuit pin, turning FET.
Pins Directly connected motor, these terminals sense voltages switched across load. These terminals also connected negative side bootstrap capacitors negative supply connections floating high-side drives. discharge current from high-side gate capacitance flows through these connections, which should have impedance circuit connections bridge. GHA, GHB, Pins These terminals high-side gate
drive outputs external N-channel FETs. External resistors between gate drive output gate connection close possible FET) used control slew rate seen gate, thereby controlling di/dt dv/dt outputs. going high turns upper half drive, sourcing current gate high-side external motor-driving bridge, turning going turns lower half drive, sinking current from external gate circuit corresponding pin, turning FET.
Pins These high-side connections
bootstrap capacitors positive supply high-side gate drives. bootstrap capacitors charged approximately VREG when associated output terminal low. When output swings high, charge bootstrap capacitor causes voltage corresponding terminal rise with output provide boosted gate voltage needed high-side FETs.
control inputs. inputs control high-side drives inputs control low-side drives. Internal lockout logic ensures that high-side output drive low-side output drive cannot active simultaneously, except when RDEAD connected AGND same time CCEN high, described CCEN section.
PWMH PWML Pins These inputs used externally
control motor torque speed. Setting PWMH turns active high-side drives turns complementary low-side drives. This provides highside-chopped slow-decay with synchronous rectification.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4935
Automotive 3-Phase MOSFET Driver
correct operating condition. charge pump stabilizes approximately under nominal conditions. RESET used also clear latched fault flags without entering sleep mode. hold RESET less then reset pulse time, tRES. This clears latched fault that disables outputs, such short circuit detection bootstrap capacitor undervoltage, also clears fault register. Note that A4935 configured start without external logic input. pull RESET means external resistor. resistor value should between
CCEN This input provides override allow both high-
Setting PWML turns active low-side drives turns complementary high-side drives. This provides low-side- chopped slow-decay with synchronous rectification. PWMH PWML also connected together driven with single signal. This provides fast-decay with synchronous rectification.
COAST active-low input, which forces gate drive
outputs, GLx, turns external FETs. This used protect FETs motor case short circuit. Using COAST does clear faults, fault flags still decoded fault register data word read. Because COAST turns external FETs, also used provide fast-decay without synchronous rectification.
RESET This active-low input, when active
allows A4935 enter sleep mode. When RESET held longer than reset pulse time, tRES, regulator internal circuitry disabled A4935 enters sleep mode. During sleep mode, current consumption from supplies reduced minimal level. addition, latched faults corresponding fault flags cleared. When A4935 coming sleep mode, protection logic ensures that gate drive outputs until charge pump reaches
side low-side external FETs phase active same time, enabling cross-conduction. extra level safety, cross-conduction only occur when RDEAD tied AGND CCEN high. CCEN input inadvertently disconnected from controller, internal pull-down resistor ensures that outputs revert safe condition.
This Enable Stop Fault input. determines
action that taken when certain faults detected. Fault Protection Diagnostics section details.
Table Phase Control Truth Table
Inputs RDEAD >0.2 AGND AGND AGND AGND RESET CCEN COAST PWMH PWML Outputs Phase disabled Phase sinking Phase sourcing Phase disabled Sink; high-side other phases Slow decay, low-side recirculation Slow decay, high-side recirculation Source; low-side other phases Fast decay, Fast decay, Slow decay, high-side recirculation Slow decay, low-side recirculation power shutdown Coast Phase disabled Cross-conduction Comment
don't care, high-side active, low-side active, high impedance, both FETs off, undefined, synchronous rectification
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4935
Automotive 3-Phase MOSFET Driver
Current Sense Amplifier uncommitted differential sense amplifier provided allow either value sense resistors current shunt current sensing element. input common mode range, CMR, allows below-ground current sensing typically required motor control during switching transients. Input pins. output sense amplifier available CSOUT used peak current control system. gain sense amplifier using external input feedback resistors. gain must greater than specified minimum ensure stability. Typically gain will between V/V. Output offset also added using external resistors. Examples setting sense amplifier gain offset provided Applications Information section.
damage components, external controller take COAST input phase control inputs.
VDSTH Faults external FETs determined
measuring drain-source voltage, each active comparing threshold voltage applied VDSTH input, VDSTH. avoid false fault detection during switching transients, comparison delayed internal blanking timer.
VDRAIN This low-current sense input from
external bridge. This input allows accurate measurement voltage drain high-side FETs. should connected directly common connection point drains power bridge FETs positive supply connection point. input current VDRAIN proportional voltage VDSTH approximated IVDRAIN VDSTH where IVDRAIN current into VDRAIN pin, VDSTH voltage VDSTH pin,
Pins open drain output fault flags, which
Diagnostics Several diagnostic features integrated into A4935 provide indication fault conditions and, required, take action prevent permanent damage. addition system wide faults such undervoltage overtemperature, A4935 integrates individual drain-source monitors each external FET, provide short circuit detection. When short undervoltage fault being reported, detailed fault information read from fault outputs serial data word.
indicate fault conditions their state, shown table event that more faults detected simultaneously, state fault flags will determined logical flag states detected faults.
Table Fault Definitions
Flag State Fault Description fault Short-to-ground Short-to-supply Shorted load Overtemperature undervoltage VREG undervoltage Bootstrap undervoltage Disable Outputs* High Flag Latched high high high
Diagnostic Management Pins
This (Enable Stop Fault) determines action taken when short circuit overtemperature fault detected. does affect undervoltage fault condition actions.
When logic high, short circuit overtemperature fault condition will pull gate drive outputs coast motor. short faults, this disabled state will latched until RESET goes serial read completed. When logic low, under most conditions A4935 will disrupt normal operation therefore will protect drive circuit motor from damage. This case even though fault flags set. This allows actions taken controlled externally system control circuits. prevent
*Yes indicates gate drives low, FETs off.
When high, short faults will always cause fault flags latched. When low, short fault will only flagged when fault present, flag state will latched. This provides additional diagnostics flexibility during
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4935
Automotive 3-Phase MOSFET Driver
switching. short faults detected will always latched fault register. When short undervoltage fault present, clock applied detailed fault information read from serial word. This used determine which external FETs short being detected, which monitored voltages have gone below their undervoltage threshold level. Fault register serial access operation detailed Fault Register Serial Access section.
time A4935 enters VREG undervoltage fault state, fault register will will remain until cleared register reset (see Fault Register Serial Access section).
Bootstrap Capacitor Undervoltage A4935 monitors
Fault States
Overtemperature junction temperature exceeds overtemperature threshold, typically 165°C, A4935 will enter overtemperature fault state will high. overtemperature fault state, FF1, will only cleared when temperature drops below recovery level defined TJFhys Note that overtemperature fault does permit access fault register because pulled low.
voltage across individual bootstrap capacitors ensure they have sufficient charge supply current pulse highside drive. Before high-side drive turned voltage across associated bootstrap capacitor must higher than turn-on voltage limit. this case, then A4935 will start bootstrap charge cycle activating complementary low-side drive. Under normal circumstances, this will charge bootstrap capacitor above turn-on voltage microseconds high-side drive will then enabled. bootstrap voltage monitor remains active while high-side drive active voltage drops below turn-off voltage charge cycle initiated. either case, there fault that prevents bootstrap capacitor charging, then charge cycle will timeout, fault flags (indicating undervoltage) will set, outputs will disabled. addition, appropriate fault register will set. This allows specific phase giving bootstrap undervoltage determined reading serial data word. bootstrap undervoltage fault state remains latched until RESET serial read fault register completed.
Undervoltage logic supply voltage moni-
high when overtemperature detected, outputs will disabled automatically while fault state present. low, then circuitry will disabled. this case external control circuits must take action limit power dissipation some prevent overtemperature damage chip unpredictable device operation.
VREG Undervoltage VREG supplies low-side gate driver
bootstrap charge current. critical ensure that voltages sufficiently high before enabling outputs. voltage VREG, VREG drops below falling VREG undervoltage lockout threshold, VREGUVoff then A4935 will enter VREG undervoltage fault state. this fault state, both will high, outputs will disabled. VREG undervoltage fault state fault flags will cleared when VREG rises above rising VREG undervoltage lockout threshold, VREGUVon. VREG undervoltage monitor circuit active during power-up, A4935 remains VREG undervoltage fault state until VREG greater than rising VREG undervoltage lockout threshold, VREGUVon.
tored ensure correct logical operation. undervoltage detected, outputs will disabled. addition, because state other reported faults cannot guaranteed, fault states, fault flags, fault register reset replaced fault flags corresponding undervoltage fault state. example, undervoltage will reset existing short circuit fault condition replace with undervoltage fault. When undervoltage condition removed, flags will cleared outputs enabled.
Short Fault Operation Shorts power bridge determined
monitoring drain-souce voltage, each active comparing fault threshold voltage VDSTH pin. Because power MOSFETs take finite time reach rated onresistance, measured drain-source voltages will show fault phase switches. avoid such false short fault detections,
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A4935
Automotive 3-Phase MOSFET Driver
output from comparators ignored under conditions: while external off, until period, referred fault blank time, after turned When turned drain-source voltage exceeds voltage VDSTH time after fault blank time, then short fault will detected. also high, then this fault will latched disabled until reset. some applications, fault blank time insufficient avoid detecting false faults during switching time external FET. these cases, external controller driving A4935 used determine correct fault condition setting low. This will prevent latching fault flag when short fault detected, will disable FET. With low, will remain high only while measured exceeds fault threshold. external controller then monitor fault flags timers validate fault condition. Note that fault thus detected A4935 will still latched fault register remain there until cleared. When low, external FETs disabled A4935 when short fault detected. avoid permanent damage external FETs motor under this condition, A4935 either fully disabled RESET input FETs switched pulling COAST input phase control inputs.
Short Supply short from motor phase connec-
Short Ground short from motor phase connections ground detected monitoring voltage across high-side FETs each phase, using appropriate voltage VDRAIN. This drain-source voltage, continuously compared voltage VDSTH pin. result this comparison ignored active. ignored also fault blank time interval after turned when comparator being ignored, output indicates that exceeds voltage VDSTH pin, will high. also high, will latched high outputs will disabled. Alternatively, also low, outputs will disabled will only high while output comparator indicates that exceeds voltage VDSTH pin. Shorted Load short-to-ground short-to-supply monitor circuits will also detect short across motor phase winding. most cases, shorted winding will indicated high-side low-side fault being detected same time. some cases relative impedances permit only shorts detected.
Differentiating Short Fault Conditions distinction between short-to-ground, short-to-supply, shorted load only made examining contents fault register. possible determine where short fault occurred when using state fault flags, FF2, alone. flag combination high simply indicates presence probable short circuit. described above, shorts detected monitoring drainsource voltage, each FETs power bridge. different short fault conditions defined follows: short-to-ground likely present active high-side greater than threshold defined VDSTH (fault bits short-to-supply likely present active low-side greater than threshold defined VDSTH (fault bits shorted load phase likely present same time, active high-side active low-side both greater than threshold defined VDSTH.
tions battery connection detected monitoring voltage across low-side FETs each phase, using appropriate pin. This drain-source voltage, VDS, continuously compared voltage VDSTH pin. result this comparison ignored active. ignored also fault blank time interval after turned when comparator being ignored, output indicates that exceeds voltage VDSTH pin, then will high. also high, then will latched high outputs will disabled. Alternatively, also low, then outputs will disabled will only high while output comparator indicates that exceeds voltage VDSTH pin.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4935
Fault Register
Automotive 3-Phase MOSFET Driver
then under voltage been detected. either case, sequence reading contents fault register external controller takes necessary additional action protect FETs. external controller pulls low. A4935 outputs fault register first bit, external controller reads fault bit, then cycles high then next bit, Steps alternate until bits fault register have been read out. After final bit, output, external controller cycles high then low. A4935 resets fault register pulls indicate fault present. external controller releases FF2. basic sequence three possible states shown figure serial transfer, last high-to-low transition input FF2, fault register fault flags reset. However, possible that three unlatched fault conditions, VREG undervoltage, undervoltage, overtemperature, still present. this case fault flags will immediately show fault status.
undervoltage short faults recorded 10-bit fault register defined table fault register accumulates detected faults until cleared setting RESET low, cycling power reading contents. contents will also cleared undervoltage fault detected. During undervoltage fault condition, both fault flags will high bits fault register will reset.
Table Fault Register Definitions
Position First Last Function exceeded phase high-side exceeded phase high-side exceeded phase high-side exceeded phase low-side exceeded phase low-side exceeded phase low-side Undervoltage detected VREG Bootstrap undervoltage detected phase Bootstrap undervoltage detected phase Bootstrap undervoltage detected phase
contents fault register read serially from applying clock signal during undervoltage short fault state. fault flag pins, FF2, open drain outputs passively pulled high when fault present. This makes possible drive both these fault pins from external source during fault condition, when A4935 pulling low. thus used clock input shift fault status register, bit-by-bit, other fault flag, FF1. When being pulled A4935, either when fault present when overtemperature fault present, then serial access possible. fault status register accessed only when goes high. This occurs when either short undervoltage fault been detected.
Resetting power-up, coming reset, after VREG undervoltage fault, possible that fault flags fault register will have cleared fault register remains set. This would happen when power-on-reset occurred, VREG risen beyond undervoltage threshold level, VREGUVon. Although VREG undervoltage fault state latched fault flags cleared when fault removed, fault register latched remain after power-on-reset. this reason recommended, when serial fault register used, perform reset taking RESET less than reset pulse time, tRES, after A4935 powered-up fault flags clear (FF1 low).
Faut Register Serial Access access fault register, must monitored external controller. goes high remains low, then short been detected. high together,
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4935
Automotive 3-Phase MOSFET Driver
Overtemperature Condition Present
Overtemperature Fault
fault detected pulled resistor External controller pulls
Phase short-to-supply A4935 outputs fault register each falling edge
A4935 pulls resets fault register
Fault Register Read
fault detected pulled resistor External controller pulls VREG undervoltage 4935 outputs fault register each falling edge A4935 pulls resets fault register
Undervoltage Fault Register Read Figure Fault flag sequence diagrams
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4935
Automotive 3-Phase MOSFET Driver
Applications Information
Power Bridge Management Using Control A4935 provides individual high-side low-side controls each phase, plus control signals coast control. This allows wide variety 3-phase bridge control schemes implemented. advanced schemes using sinusoidal current control, each 3-phase bridge controlled individually without using COAST inputs. This requires higher performance external controller, with output each phase. full external control over dead time required, then outputs will required, each bridge. this type system, external controller full control over current-decay method, load current recirculation paths, braking, coasting. Figure shows example paths bridge load currents when each phase controlled directly. inputs PWMH PWML both tied high COAST tied low. this case high-side FETs switched during current decay time (PWM off-time) load current recirculates through low-side FETs. This commonly referred high-side chopping high-side PWM. During off-time, complementary FETs turned short body diode provide synchronous rectification. Figure shows combination phase states, same principal applies possible phase states. This principal also applies when low-side FETs turned during off-time load current recirculates through high side FETs, shown figure less complex control schemes, example where simple block commutation used, possible control bridge with three logic signals (one each phase) single signal. Figure shows example 2-phase excitation with high-side PWM, commonly used block commutation scheme. PWMH input used modulate phase currents PWML held high. During off-time, active high-side turned complementary low-side turned Note that phase control signals this case change switching, phase combination, managed single signal. low-side PWM, PWMH held high signal applied PWML. tying PWMH PWML together applying signal them, load current controlled using fast decay effectively reversing supply polarity. This feature operates
Phase
Drive
Recirculate Phase
Slow decay, synchronous rectification, high-side using phase inputs
Phase
Drive
Recirculate Phase
Slow decay, synchronous rectification, low-side using phase inputs
Drive Phase PWMH PWML
Recirculate Phase PWMH PWML
Slow decay, synchronous rectification, high-side using PWMx inputs
Figure Power bridge current paths
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A4935
Automotive 3-Phase MOSFET Driver
with either 2-phase 3-phase excitation. When using fast decay, duty cycle results zero effective motor torque. duty cycle less than causes negative effective torque, greater than causes positive effective torque. reduce power dissipation external FETs, A4935 instructed turn appropriate low-side high-side drives during load current recirculation off-cycle. This synchronous rectification allows current flow through selected FETs, rather than source-drain body diode, during decay time. body diodes recirculating power FETs conduct only during dead time that occurs each transition.
choice power external series gate resistance determine selection dead-time resistor, RDEAD. dead time should long enough ensure that phase stopped conducting before complementary starts conducting. This should also take into account tolerance variation gate capacitance, series gate resistance, on-resistance A4935 internal drives. Internally-generated dead time will present only on-command occurs within tDEAD after off-command complementary FET. case where side phase drive permanently off, example when using diode rectification with slow decay, then dead time will occur. this case gate drive will turn within specified propagation delay after corresponding phase input goes high. (Refer Gate Drive Timing diagrams.)
Dead Time prevent cross-conduction (shoot through) phase power bridge, necessary have dead time delay, tDEAD between high- low-side turn-off next complementary turn-on event. potential cross-conduction occurs when complementary high-side low-side pair FETs switched same time; example, when using synchronous rectification after bootstrap capacitor charging cycle. A4935, dead time three phases single deadtime resistor (RDEAD) between RDEAD AGND pins. RDEAD values between 25°C nominal value tDEAD approximated 7200 tDEAD(nom) (200 RDEAD) where RDEAD Greatest accuracy obtained values RDEAD between which shown figure
Fault Blank Time avoid false short fault detection, output from monitor ignored when that period time after turned This period time fault blank time. length dead time, tDEAD plus additional period time that compensates delay monitors. This additional delay typically When tDEAD
DEAD RDEAD
IDEAD current estimated IDEAD RDEAD
dead time generated externally, example output microcontroller, then connect RDEAD AGND internally-generated dead time zero. Note that this configuration allow cross-conduction, appropriate care should taken, described Cross-Conduction section. maximum internally-generated dead time, typical, connecting RDEAD pins.
Figure Dead time versus RDEAD
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A4935
Automotive 3-Phase MOSFET Driver
zero connecting RDEAD AGND, fault blank time typically defaults
voltage drop across bootstrap capacitor being turned approximated QGATE CBOOT
Cross-Conduction some circumstances desirable allow activation both high-side low-side FETs single phase power bridge. This used, with care, reduce diode conduction during synchronous rectification, which improves overall efficiency reduces electromagnetic emissions. This mode operation also useful independently controlling each phase motor turn high-side lowside FETs together, cause supply short circuit blowing safety fuse. Cross-conduction occur only when internally-generated dead time zero connecting RDEAD AGND and, same time, CCEN high. zero internally-generated dead time required, cross-conduction prevented, then CCEN tied AGND. When dead time zero still possible some overlap present switching instants relative switching time FETs.
factor would approximately VBOOT maximum voltage across bootstrap capacitor under normal operating conditions VREG(max). However, some circumstances voltage transiently reach clamp voltage Zener diodes between pins. most applications, with good ceramic capacitor working voltage limited
Bootstrap Charging good practice ensure high-side bootstrap capacitor completely charged before high-side cycle requested. time required charge capacitor, tCHARGE (s), approximated where CBOOT value bootstrap capacitor, required voltage bootstrap capacitor. power-up when drives have been disabled long time, bootstrap capacitor completely discharged. this case considered full high-side drive voltage, Otherwise, amount voltage dropped during charge transfer, which should less. capacitor charged whenever pulled current flows from VREG through internal bootstrap diode circuit CBOOT. Bootstrap Charge Management A4935 provides automatic bootstrap capacitor charge management. bootstrap capacitor voltage each phase continuously checked ensure that above bootstrap under-voltage threshold, VBOOTUV. bootstrap capacitor voltage drops below this threshold, A4935 will turn necessary low-side FET, continue charging until bootstrap capacitor exceeds undervoltage threshold plus hysteresis, VBOOTUV VBOOTUVhys. minimum charge time typically longer very large values bootstrap capacitCHARGE CBOOT
Bootstrap Capacitor Selection bootstrap capacitors, CBOOTx, must correctly selected ensure proper operation A4935. capacitances high, time will wasted charging capacitor, resulting limit maximum duty cycle frequency. capacitances low, there large voltage drop time charge transferred from CBOOTx gate, charge sharing. keep this voltage drop small, charge bootstrap capacitor, QBOOT, should much larger than charge required gate FET, QGATE. factor reasonable value, following formula used calculate value CBOOT QBOOT CBOOT VBOOT QGATE therefore: CBOOT QGATE VBOOT
where VBOOT voltage across bootstrap capacitor.
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A4935
Automotive 3-Phase MOSFET Driver
(>1000 nF). bootstrap capacitor voltage does reach threshold within approximately undervoltage fault will flagged.
attention should paid ensure operating conditions allow A4935 remain safe range junction temperature. power consumed A4935, estimated PBIAS PCPUMP PSWITCHING given: PBIAS
VREG Capacitor Selection internal reference, VREG, supplies current low-side gate drive circuits charging current bootstrap capacitors. When low-side turned gate-drive circuit will provide high transient current gate that necessary turn quickly. This current, which several hundred milliamperes, cannot provided directly limited output VREG regulator, must supplied external capacitor connected VREG. turn-on current high-side similar value that low-side FET, mainly supplied bootstrap capacitor. However bootstrap capacitor must then recharged from VREG regulator output. Unfortunately bootstrap recharge occur very short time after lowside turn-on occurs. This requires that value capacitor connected between VREG AGND should high enough minimize transient voltage drop VREG combination low-side turn-on bootstrap capacitor recharge. value CBOOT reasonable value. maximum working voltage will never exceed VREG capacitor rated This capacitor should placed close possible VREG pin.
PCPUMP VBB) VREG] [VBB VREG]
PSWITCHING QGATE VREG fPWM Ratio where: QGATE fPWM
number FETs switching during cycle, Ratio RGATE Braking A4935 used perform dynamic braking either forcing low-side FETs high-side FETs conversely, forcing low-side FETs high-side FETs This will effectively short-circuit back motor, creating breaking torque. During braking, load current approximated IBRAKE VBEMF (10)
Supply Decoupling Because this switching circuit, there current spikes from supplies switching points. with such circuits, power supply connections should decoupled with ceramic capacitor, typically between supply ground. These capacitors should connected close possible device supply pins VDD, power ground pin, PGND.
where VBEMF voltage generated motor resistance phase winding. Care must taken during braking ensure that maximum ratings power FETs exceeded. Dynamic braking equivalent slow decay with synchronous rectification phases enabled.
Power Dissipation applications where high ambient temperature expected, on-chip power dissipation become critical factor. Careful
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A4935
Automotive 3-Phase MOSFET Driver
A4935 also used perform regenerative braking. This equivalent reversing motor commutation sequence using fast decay with synchronous rectification. Note that phase commutation must continue regenerative braking operate supply must capable managing reverse current, such connecting resistive load dumping current battery capacitor.
tor, between AGND also have matched values. gain sense amplfier, determined relative values approximately: (11)
Current Sense Amplifier gain current sense amplifier using external input feedback resistors. Output offset also added using external resistors. Care must taken ensure that input impedances seen from either sense resistor match. basic configuration shown figure input resistors, have matched values. feedback resistor, between CSOUT, ground reference resisRF CSOUT A4935
output offset required, example allow reverse current measurement, then this generated adding offset input through resistor. Because amplifier operating closed loop, offset added will mirrored output. Figure shows suitable resistor values gain, output offset,
Layout Recommendations Careful consideration must given layout when designing high frequency, fast switching, high current circuits. following recommendations regarding some these considerations: A4935 analog ground, AGND, power ground, PGND, should connected together package pins. This common point, high-current return external FETs, should return separately negative side motor supply filtering capacitor. This will minimize effect switching noise device logic analog reference. exposed thermal pins package should connected common point AGND PGND. Minimize stray inductance using short, wide copper traces drain source terminals power FETs. This includes motor lead connections, input power bus, common source low-side power FETs. This will minimize voltages induced fast switching large load currents. Consider small (100 ceramic decoupling capacitors across sources drains power FETs limit fast transient voltage spikes caused inductance circuit trace. Keep gate discharge return connections short possible. inductance these traces will cause negative transitions corresponding A4935 pins, which exceed absolute maximum ratings. this likely, consider clamping diodes limit negative excursion these pins with respect AGND.
Basic configuration
CSOUT A4935
VOS=
Typical Configuration
Figure Current sense amplifier configurations
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A4935
Automotive 3-Phase MOSFET Driver
Sensitive connections such RDEAD VDSTH, which have very little ground current, should connected Quiet ground (refer figure which connected independently, closest AGND pin. These sensitive components should never connected directly supply common common ground plane. They must referenced directly AGND pin. supply decoupling VBB, VREG, should connected Controller Supply ground, which connected independently, close PGND pin. decoupling capacitors should also connected close practicable relevant supply pin. layout space limited, then Quiet ground Controller Supply ground combined. this case, ensure that ground return dead time resistor close AGND pin. Check peak voltage excursion transients with reference AGND pin, using close grounded (tip barrel) probe. voltage exceeds absolute maximum shown this datasheet, additional clamping capacitance between AGND shown figure Gate charge drive paths gate discharge return paths carry large transient current pulse. Therefore, traces from
GHx, GLx, should short possible reduce circuit trace inductance. Provide independent connection from common point power bridge. recommended connect directly xGND pin, this inject noise into sensitive functions such timer dead time. connection should used connection. inputs sense amplifier, CSN, should have independent circuit traces. best results, they should matched length route. low-cost diode placed connection provide reverse battery protection. reverse battery conditions, possible body diodes power FETs clamp reverse voltage approximately this case, additional diode connection will prevent damage A4935 VDRAIN input will survive reverse voltage. Note that above only recommendations. Each application different encounter different sensitivities. driver running amps will less susceptible than running with each design should tested maximum current ensure parasitic effects eliminated.
Optional reverse battery protection VDRAIN VREG
Supply
A4935
Motor
VDSTH RDEAD AGND PGND Optional components limit transients
Quiet Ground Controller Supply Ground
Power Ground
Supply Common
Figure Supply routing suggestions
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A4935
Automotive 3-Phase MOSFET Driver
Input Output Structures
VREG VDRAIN
VREG
Supply protection structures
Gate drive outputs
COAST PWMx
Fault output
Fault input/output
CCEN
RESET
Logic inputs, pulldown
VREG
Logic input, with pulldown
CSOUT RDEAD VDSTH
RESET input
Current sense amplifier
RDEAD
monitor threshold input
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A4935
Automotive 3-Phase MOSFET Driver
Pin-out Diagram
RDEAD AGND PGND VDRAIN VREG
Terminal List
Name RESET PWML CCEN PWMH COAST CSOUT VDSTH Description internal connection; connect AGND Standby mode control Enable Stop Fault input Fault Flag serial clock input Fault Flag serial data output Control input phase low-side Control input phase high-side Control input phase high-side Control input phase low-side Control input phase low-side Control input phase high-side Low-side input Cross-conduction enable High-side input Coast input Current sense output Logic supply Current sense negative input Current sense positive input Fault threshold voltage Low-side source Name AGND VREG VDRAIN PGND AGND RDEAD Description Low-side gate drive phase Analog ground Motor connection phase High-side gate drive phase Bootstrap capacitor phase Low-side gate drive phase Motor connection phase High-side gate drive phase Bootstrap capacitor phase Low-side gate drive phase Motor connection phase High-side gate drive phase Bootstrap capacitor phase Gate drive supply output High-side drain voltage sense Pump capacitor Pump capacitor Power ground Main power supply Analog ground Dead time setting Exposed thermal pad; connect AGND
CCEN PWMH COAST CSOUT VDSTH AGND
RESET PWML
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A4935
Automotive 3-Phase MOSFET Driver
Package 48-Pin LQFP with Exposed Thermal
0.30 9.00 ±0.20 7.00 ±0.20 +0.05 0.15 -0.06 1.70 0.50
9.00 ±0.20 7.00 ±0.20
5.00 5.00 8.60
0.60 ±0.15 (1.00)
5.00 0.25 SEATING PLANE GAGE PLANE 5.00 8.60
0.08 0.22 ±0.05 0.50
SEATING PLANE
Layout Reference View
1.60 1.40 ±0.05 0.10 ±0.05
Reference Only (reference JEDEC MS-026 BBCHD) Dimensions millimeters Dimensions exclusive mold flash, gate burrs, dambar protrusions Exact case lead configuration supplier discretion within limits shown Terminal mark area Exposed thermal (bottom surface)
Reference land pattern layout (reference IPC7351 QFP50P900X900X160-48M); adjust necessary meet application process requirements layout tolerances; when mounting multilayer PCB, thermal vias exposed thermal land improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Copyright ©2007-2008, Allegro MicroSystems, Inc. products described here manufactured under more U.S. patents U.S. patents pending. Allegro MicroSystems, Inc. reserves right make, from time time, such departures from detail specifications required permit improvements performance, reliability, manufacturability products. Before placing order, user cautioned verify that information being relied upon current. Allegro's products used life support devices systems, failure Allegro product reasonably expected cause failure that life support device system, affect safety effectiveness that device system. information included herein believed accurate reliable. However, Allegro MicroSystems, Inc. assumes responsibility use; infringement patents other rights third parties which result from use. latest version this document, visit website: www.allegromicro.com
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