DSP56309 24-Bit Digital Signal Processor Memory Expansion Ar
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DSP56309 Rev. 2/2005
DSP56309
24-Bit Digital Signal Processor
Memory Expansion Area Triple Timer HI08 ESSI PrograM 20480 bits (default) PM_EB Data 7168 bits (default) XM_EB Data 7168 bits (default) YM_EB
PIO_EB
Peripheral Expansion Area
DSP56309 intended applications benefiting from large amount internal memory, such wireless infrastructure applications.
Address Generation Unit Six-Channel Unit Bootstrap
24-Bit
External Address Address Switch External Interface Inst. Cache Control Control External Data Switch
DSP56300 Core
Internal Data Switch EXTAL XTAL Clock Generator RESET PINIT/NMI Program Interrupt Controller Program Decode Controller MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Program Address Generator
What's New?
Data
Rev. includes following changes:
Adds lead-free packaging part numbers.
56-bit 56-bit Accumulators 56-bit Barrel Shifter
Data
Power Management JTAG OnCE
Figure DSP56309 Block Diagram
DSP56309 member DSP56300 core family programmable CMOS DSPs. DSP56300 core includes barrel shifter, 24-bit addressing, instruction cache, direct memory access (DMA). DSP56309 offers MMACS 3.0-3.6 using internal clock. large internal memory ideal wireless infrastructure wireless local-loop applications. DSP56300 core family offers level performance speed power provided rich instruction low-power dissipation, thus enabling generation wireless, multimedia, telecommunications products.
Note: This document contains information product. Specifications information herein subject change without notice.
Freescale Semiconductor, Inc., 1996, 2005. rights reserved.
Table Contents
Data Sheet Conventions Features.iii Target Applications Product Documentation
Chapter
Signals/Connections
1.10 1.11 1.12 Power .1-3 Ground .1-3 Clock.1-4 External Memory Expansion Port (Port .1-4 Interrupt Mode Control .1-7 Host Interface (HI08).1-8 Enhanced Synchronous Serial Interface (ESSI0) .1-11 Enhanced Synchronous Serial Interface (ESSI1) .1-12 Serial Communication Interface (SCI) .1-14 Timers .1-15 JTAG OnCE Interface .1-16 Maximum Ratings.2-1 Thermal Characteristics .2-2 Electrical Characteristics.2-2 Electrical Characteristics.2-3 TQFP Package Description.3-2 TQFP Package Mechanical Drawing.3-9 MAP-BGA Package Description .3-10 MAP-BGA Package Mechanical Drawing .3-18 Thermal Design Considerations.4-1 Electrical Design Considerations.4-2 Power Consumption Considerations.4-3 Performance Issues .4-4 Input (EXTAL) Jitter Requirements .4-5
Chapter
Specifications
Chapter
Packaging
Chapter
Design Considerations
Appendix
Power Consumption Benchmark
Data Sheet Conventions
OVERBAR
"asserted" "deasserted" Examples:
Indicates signal that active when pulled (For example, RESET active when low.) Means that high true (active high) signal high that true (active low) signal Means that high true (active high) signal that true (active low) signal high Signal/Symbol
Signal State True Asserted False Deasserted True Asserted False Deasserted Note: Values VIL, VOL, VIH, defined individual product specifications.
Logic State
Voltage
VIL/VOL /VOH /VOH VIL/VOL
DSP56309 Technical Data, Rev. Freescale Semiconductor
Features
Table lists features DSP56309 device.
Table DSP56309 Features
Feature Description
million multiply-accumulates second (MMACS) with clock nominal Data arithmetic logic unit (Data ALU) with fully pipelined 24-bit parallel multiplier-accumulator (MAC), 56-bit parallel barrel shifter (fast shift normalization; stream generation parsing), conditional instructions, 24-bit 16-bit arithmetic support under software control Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized applications (including immediate offsets), internal instruction cache controller, internal memoryexpandable hardware stack, nested hardware loops, fast auto-return interrupts Direct memory access (DMA) with channels supporting internal external accesses; one-, twoand three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; triggering from interrupt lines peripherals Phase-lock loop (PLL) allows change low-power divide factor (DF) without loss lock output clock with skew elimination Hardware debugging support including On-Chip Emulation (OnCE`) module, Joint Test Action Group (JTAG) test access port (TAP) Enhanced 8-bit parallel host interface (HI08) supports variety buses (for example, ISA) provides glueless connection number industry-standard microcomputers, microprocessors, DSPs enhanced synchronous serial interfaces (ESSI), each with receiver three transmitters (allows six-channel home theater) Serial communications interface (SCI) with baud rate generator Triple timer module thirty-four programmable general-purpose input/output (GPIO) pins, depending which peripherals enabled 24-bit bootstrap 24-bit total Program RAM, instruction cache, data RAM, data sizes programmable:
High-Performance DSP56300 Core
Internal Peripherals
Internal Memories
Program Size
20480 bits 19456 bits 24576 bits 23552 bits
Instruction Cache Size
1024 24-bit 1024 24-bit
Data Size
7168 bits 7168 bits 5120 bits 5120 bits
Data Size
7168 bits 7168 bits 5120 bits 5120 bits
Instruction Cache
disabled enabled disabled enabled
Switch Mode
disabled disabled enabled enabled
External Memory Expansion
Data memory expansion 24-bit word memory spaces using standard external address lines Program memory expansion 24-bit words memory space using standard external address lines External memory expansion port Chip select logic glueless interface static random access memory (SRAMs) Internal DRAM Controller glueless interface dynamic random access memory (DRAMs) Very low-power CMOS design Wait Stop low-power standby modes Fully static design specified operate down (dc) Optimized power management circuitry (instruction-dependent, peripheral-dependent, modedependent)
Power Dissipation
Packaging
144-pin TQFP package lead-free lead-bearing versions 196-pin molded array plastic-ball grid array (MAP-BGA) package lead-free lead-bearing versions
DSP56309 Technical Data, Rev. Freescale Semiconductor
Target Applications
DSP56309 intended applications benefiting from large amount internal memory, such wireless infrastructure applications.
Product Documentation
documents listed Table required complete description DSP56309 device necessary design properly with part. Documentation available from local Freescale distributor, Freescale semiconductor sales office, Freescale Semiconductor Literature Distribution Center. documentation updates, visit Freescale website. contact information back cover this document.
Table DSP56309 Documentation
Name
DSP56309 User's Manual
Description
Detailed functional description DSP56309 memory configuration, operation, register programming
Order Number
DSP56309UM DSP56300FM DSP56309 product website
DSP56300 Family Detailed description DSP56300 family processor core instruction Manual
Application Notes Documents describing specific applications optimized device operation including code examples
DSP56309 Technical Data, Rev. Freescale Semiconductor
Signals/Connections
DSP56309 input output signals organized into functional groups shown Table 1-1. Figure diagrams DSP56309 signals functional group. remainder this chapter describes signal pins each functional group.
Table 1-1. DSP56309 Functional Signal Groupings
Number Signals Functional Group TQFP
Power (VCC) Ground (GND) Clock Address Data control Interrupt mode control Host interface (HI08) Enhanced synchronous serial interface (ESSI) Serial communication interface (SCI) Timer OnCE/JTAG Port Notes: Port
MAP-BGA
Port
Ports Port
Port signals define external memory interface port, including external address bus, data bus, control signals. Port signals HI08 port signals multiplexed with GPIO signals. Port signals ESSI port signals multiplexed with GPIO signals. Port signals port signals multiplexed with GPIO signals. There signal connections TQFP package signal connections MAP-BGA package that used. These designated connect (NC) package description (see Chapter
Note: This chapter refers number configuration registers used select individual multiplexed signal functionality. Refer DSP56309 User's Manual details these configuration registers.
DSP56309 Technical Data, Rev. Freescale Semiconductor
Signals/Connections
During Reset MODA MODB MODC MODD RESET Non-Multiplexed H[0-7] HCS/HCS Single HDS/HDS Single HREQ/HREQ HACK/HACK After Reset IRQA IRQB IRQC IRQD RESET Multiplexed HAD[0-7] HAS/HAS HA10 Double HRD/HRD HWR/HWR Double HTRQ/HTRQ HRRQ/HRRQ Port GPIO PC[0-2] Port GPIO PD[0-2] Port GPIO Timer GPIO TIO0 TIO1 TIO2 Port GPIO PB[0-7] PB10 PB13 PB11 PB12 PB14 PB15
DSP56309
VCCP VCCQL VCCQH VCCA VCCD VCCC VCCH VCCS GNDP GNDP1 GNDQ GNDA GNDD GNDC GNDH GNDS EXTAL XTAL CLKOUT PCAP After Reset Power Inputs: Internal Logic Address Data Control HI08 ESSI/SCI/Timer Grounds4:
Interrupt/ Mode Control
Internal Logic Address Data Control HI08 ESSI/SCI/Timer
Host Interface (HI08) Port1
Clock
Enhanced Synchronous Serial Interface Port (ESSI0)
SC0[0-2] SCK0 SRD0 STD0
Enhanced Synchronous Serial Interface Port (ESSI1) Port
During Reset PINIT
SC1[0-2] SCK1 SRD1 STD1
A[0-17] D[0-23]
External Address External Data External Control
Serial Communications Interface (SCI) Port2
SCLK
AA[0-3]/RAS[0-3] BCLK BCLK Notes:
Timers3
TIO0 TIO1 TIO2 TRST
OnCE/ JTAG Port
HI08 port supports non-multiplexed multiplexed bus, single double Data Strobe (DS), single double Host Request (HR) configurations. Since each these modes configured independently, combination these modes possible. These HI08 signals also configured alternatively GPIO signals (PB[0-15]). Signals with dual designations (for example, HAS/HAS) have configurable polarity. ESSI0, ESSI1, signals multiplexed with Port GPIO signals (PC[0-5]), Port GPIO signals (PD[0-5]), Port GPIO signals (PE[0-2]), respectively. TIO[0-2] configured GPIO signals. Ground connections shown this figure TQFP package. MAP-BGA package, addition GNDP GNDP1 connections, there connections common internal package ground plane.
Figure 1-1.
Signals Identified Functional Group
DSP56309 Technical Data, Rev. Freescale Semiconductor
Power
Power
Table 1-2.
Power Name
VCCP VCCQL VCCQH VCCA VCCD VCCC VCCH VCCS
Power Inputs
Description
Power-VCC dedicated use. voltage should well-regulated input should provided with extremely impedance path power rail. Quiet Power (core)-An isolated power core processing logic. This input must isolated externally from other chip power inputs. Quiet External (High) Power-A quiet power source lines. This input must tied externally other chip power inputs, except VCCQL. Address Power-An isolated power sections address drivers. This input must tied externally other chip power inputs, except VCCQL. Data Power-An isolated power sections data drivers. This input must tied externally other chip power inputs, except VCCQL. Control Power-An isolated power control drivers. This input must tied externally other chip power inputs, except VCCQL. Host Power-An isolated power HI08 drivers. This input must tied externally other chip power inputs, except VCCQL. ESSI, SCI, Timer Power-An isolated power ESSI, SCI, timer drivers. This input must tied externally other chip power inputs, except VCCQL.
Note: user must provide adequate external decoupling capacitors power connections.
Ground
Table 1-3.
Ground Name
GNDP
Grounds1
Description
Ground-Ground-dedicated use. connection should provided with extremely low-impedance path ground. VCCP should bypassed 0.47 capacitor located close possible chip package. Ground 1-Ground-dedicated use. connection should provided with extremely low-impedance path ground. Quiet Ground-An isolated ground internal processing logic. This connection must tied externally other chip ground connections, except GNDP GNDP1. user must provide adequate external decoupling capacitors. Address Ground-An isolated ground sections address drivers. This connection must tied externally other chip ground connections, except user must provide adequate external decoupling capacitors. Data Ground-An isolated ground sections data drivers. This connection must tied externally other chip ground connections, except GNDP GNDP1. user must provide adequate external decoupling capacitors. Control Ground-An isolated ground control drivers. This connection must tied externally other chip ground connections, except GNDP GNDP1. user must provide adequate external decoupling capacitors. Host Ground-An isolated ground HI08 drivers. This connection must tied externally other chip ground connections, except user must provide adequate external decoupling capacitors. ESSI, SCI, Timer Ground-An isolated ground ESSI, SCI, timer drivers. This connection must tied externally other chip ground connections, except user must provide adequate external decoupling capacitors. Ground-Connected internal device ground plane. user must provide adequate external decoupling capacitors connections. These connections only used TQFP package. These connections common grounds used MAP-BGA package.
GNDP1 GNDQ2 GNDA2
GNDD2
GNDC2
GNDH2 GNDS2
GND3 Notes:
DSP56309 Technical Data, Rev. Freescale Semiconductor
Signals/Connections
Clock
Table 1-4.
Signal Name
EXTAL XTAL Input Output
Clock Signals
Signal Description
Type
State During Reset
Input Chip-driven
External Clock/Crystal Input-Interfaces internal crystal oscillator input external crystal external clock. Crystal Output-Connects internal crystal oscillator output external crystal. external clock used, leave XTAL unconnected.
Table 1-5.
Signal Name
CLKOUT
Phase-Locked Loop Signals
Signal Description
Clock Output-Provides output clock synchronized internal core clock phase. enabled both multiplication division factors equal one, then CLKOUT also synchronized EXTAL. disabled, CLKOUT frequency half frequency EXTAL.
Type
Output
State During Reset
Chip-driven
PCAP
Input
Input
Capacitor-An input connecting off-chip capacitor filter. Connect capacitor terminal PCAP other terminal VCCP. used, PCAP tied VCC, GND, left floating.
PINIT
Input
Input
Initial-During assertion RESET, value PINIT written into enable (PEN) control (PCTL) register, determining whether enabled disabled. Nonmaskable Interrupt-After RESET deassertion during normal instruction processing, this Schmitt-trigger input negative-edge-triggered request internally synchronized CLKOUT. Note: PINIT/NMI tolerate
Input
External Memory Expansion Port (Port
Note: When DSP56309 enters low-power standby mode (stop wait), releases mastership tristates relevant Port signals: A[0-17], D[0-23], AA0/RAS0-AA3/RAS3, CAS.
1.5.1
External Address
Table 1-6. External Address Signals
Signal Description
Address Bus-When master, A[0-17] active-high outputs that specify address external program data memory accesses. Otherwise, signals tri-stated. minimize power dissipation, A[0-17] change state when external memory spaces being accessed.
Signal Name
A[0-17]
Type
Output
State During Reset, Stop, Wait
Tri-stated
DSP56309 Technical Data, Rev. Freescale Semiconductor
External Memory Expansion Port (Port
1.5.2
External Data
Table 1-7. External Data Signals
Signal Description
Data Bus-When master, D[0-23] active-high, bidirectional input/outputs that provide bidirectional data external program data memory accesses. Otherwise, D[0-23] tri-stated.
Signal Name
D[0-23]
Type
Input/ Output
State During Reset
Ignored Input
State During Stop Wait
Last state: Input: Ignored Output: Tri-stated
1.5.3
Signal Name
AA[0-3]
External Control
Table 1-8.
Type
Output
External Control Signals
Signal Description
State During Reset, Stop, Wait
Tri-stated
Address Attribute-When defined these signals used chip selects additional address lines. default defines priority scheme under which only signal asserted time. Setting priority disable (APD) (Bit Operating Mode Register, priority mechanism disabled lines used together four external lines that decoded externally into chip select signals. Address Strobe-When defined RAS, these signals used DRAM interface. These signals tri-statable outputs with programmable polarity.
RAS[0-3]
Output Output Tri-stated
Read Enable-When master, active-low output that asserted read external memory data (D[0-23]). Otherwise, tristated. Write Enable-When master, active-low output that asserted write external memory data (D[0-23]). Otherwise, signals tri-stated. Transfer Acknowledge-If DSP56309 master there external activity, DSP56309 master, input ignored. input data transfer acknowledge (DTACK) function that extend external cycle indefinitely. number wait states .infinity) added wait states inserted control register (BCR) keeping deasserted. typical operation, deasserted start cycle, asserted enable completion cycle, deasserted before next cycle. current cycle completes clock period after asserted synchronous CLKOUT. number wait states determined input BCR, whichever longer. used minimum number wait states external cycles. functionality, must programmed least wait state. zero wait state access cannot extended deassertion; otherwise, improper operation result. operate synchronously asynchronously depending setting Operating Mode Register. functionality cannot used during DRAM type accesses; otherwise improper operation result.
Output
Tri-stated
Input
Ignored Input
Output
Reset: Output (deasserted) State during Stop/Wait depends setting: Output, deasserted Maintains last state (that asserted, remains asserted)
Request-Asserted when requests mastership. deasserted when longer needs bus. asserted deasserted independently whether DSP56309 master slave. "parking" allows deasserted even though DSP56309 master. (See description "parking" signal description.) request hold (BRH) allows asserted under software control even though does need bus. typically sent external arbitrator that controls priority, parking, tenure each master same external bus. affected only requests external bus, never internal bus. During hardware reset, deasserted arbitration reset slave state.
DSP56309 Technical Data, Rev. Freescale Semiconductor
Signals/Connections
Table 1-8.
Signal Name
External Control Signals (Continued)
Signal Description
Grant-Asserted external arbitration circuit when DSP56309 becomes next master. When asserted, DSP56309 must wait until deasserted before taking mastership. When deasserted, mastership typically given current cycle. This occur middle instruction that requires more than external cycle execution. default operation this requires setup hold time specified Table 214. alternate mode invoked: asynchronous arbitration enable (ABE) (Bit Operating Mode Register. When this set, synchronized internally. This eliminates respective setup hold time requirements adds required delay between deassertion initial input assertion subsequent input.
Type
Input
State During Reset, Stop, Wait
Ignored Input
Input/ Output
Ignored Input
Busy-Indicates that active. Only after deasserted pending master become master (and then assert signal again). master keep asserted after ceasing activity regardless whether asserted deasserted. Called "bus parking," this allows current master reuse without rearbitration until another device requires bus. deasserted "active pull-up" method (that driven high then released held high external pull-up resistor). default operation this signal requires setup hold time specified Table 2-14. alternative mode invoked setting (Bit Operating Mode Register. When this set, synchronized internally. additional information. Note: requires external pull-up resistor.
Output
Tri-stated
Column Address Strobe-When master, active-low output used DRAM strobe column address. Otherwise, Mastership Enable (BME) DRAM control register cleared, signal tri-stated. Clock When master, BCLK active when Operating Mode Register Address Trace Enable set. When BCLK active synchronized CLKOUT internal PLL, BCLK precedes CLKOUT one-fourth clock cycle. Clock When master, BCLK inverse BCLK signal. Otherwise, signal tri-stated.
BCLK
Output
Tri-stated
BCLK
Output
Tri-stated
DSP56309 Technical Data, Rev. Freescale Semiconductor
Interrupt Mode Control
Interrupt Mode Control
interrupt mode control signals select chip operating mode comes hardware reset. After RESET deasserted, these inputs hardware interrupt request lines.
Table 1-9.
Signal Name
RESET
Interrupt Mode Control
Signal Description
Reset-Places chip Reset state resets internal phase generator. Schmitt-trigger input allows slowly rising input (such capacitor charging) reset chip reliably. When RESET signal deasserted, initial chip operating mode latched from MODA, MODB, MODC, MODD inputs. RESET signal must asserted after powerup. Mode Select A-MODA, MODB, MODC, MODD select initial chip operating modes, latched into Operating Mode Register when RESET signal deasserted. External Interrupt Request A-After reset, this input becomes levelsensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. processor STOP WAIT standby state IRQA asserted, processor exits STOP WAIT state.
Type
Input
State During Reset
Schmitt-trigger Input
MODA
Input
Schmitt-trigger Input
IRQA
Input
MODB
Input
Schmitt-trigger Input
Mode Select B-MODA, MODB, MODC, MODD select initial chip operating modes, latched into Operating Mode Register when RESET signal deasserted. External Interrupt Request B-After reset, this input becomes levelsensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. processor WAIT standby state IRQB asserted, processor exits WAIT state.
IRQB
Input
MODC
Input
Schmitt-trigger Input
Mode Select C-MODA, MODB, MODC, MODD select initial chip operating modes, latched into Operating Mode Register when RESET signal deasserted. External Interrupt Request C-After reset, this input becomes levelsensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. processor WAIT standby state IRQC asserted, processor exits WAIT state.
IRQC
Input
MODD
Input
Schmitt-trigger Input
Mode Select D-MODA, MODB, MODC, MODD select initial chip operating modes, latched into Operating Mode Register when RESET signal deasserted. External Interrupt Request D-After reset, this input becomes levelsensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. processor WAIT standby state IRQD asserted, processor exits WAIT state.
IRQD
Input
Note: These signals tolerant.
DSP56309 Technical Data, Rev. Freescale Semiconductor
Signals/Connections
Host Interface (HI08)
HI08 provides fast, 8-bit, parallel data port that connects directly host bus. HI08 supports variety standard buses connects directly number industry-standard microcomputers, microprocessors, DSPs, hardware.
1.7.1
Host Port Usage Considerations
Careful synchronization required when system reads multiple-bit registers that written another asynchronous system. This common problem when asynchronous systems connected they Host port). considerations proper operation discussed Table 1-10.
Table 1-10.
Action
Asynchronous read receive byte registers
Host Port Usage Considerations
Description
When reading receive byte registers, Receive register High (RXH), Receive register Middle (RXM), Receive register (RXL), host interface programmer should interrupts poll Receive register Data Full (RXDF) flag that indicates data available. This assures that data receive byte registers valid. host interface programmer should write transmit byte registers, Transmit register High (TXH), Transmit register Middle (TXM), Transmit register (TXL), unless Transmit register Data Empty (TXDE) indicating that transmit byte registers empty. This guarantees that transmit byte registers transfer valid data Host Receive (HRX) register. host interface programmer must change Host Vector (HV) register only when Host Command (HC) clear. This practice guarantees that interrupt control logic receives stable vector.
Asynchronous write transmit byte registers
Asynchronous write host vector
1.7.2
Host Port Configuration
HI08 signal functions vary according programmed configuration interface determined bits HI08 Port Control Register.
Table 1-11.
Signal Name
H[0-7]
Host Interface
Signal Description
Type
Input/Output
State During Reset1,2
Ignored Input
Host Data-When HI08 programmed interface with non-multiplexed host function selected, these signals lines bidirectional Data bus. Host Address-When HI08 programmed interface with multiplexed host function selected, these signals lines bidirectional multiplexed Address/Data bus. Port 0-7-When HI08 configured GPIO through HI08 Port Control Register, these signals individually programmed inputs outputs through HI08 Data Direction Register.
HAD[0-7]
Input/Output
PB[0-7]
Input Output
DSP56309 Technical Data, Rev. Freescale Semiconductor
Host Interface (HI08)
Table 1-11.
Signal Name
Host Interface (Continued)
Signal Description
Host Address Input 0-When HI08 programmed interface with nonmultiplexed host function selected, this signal line host address input bus. Host Address Strobe-When HI08 programmed interface with multiplexed host function selected, this signal host address strobe (HAS) Schmitt-trigger input. polarity address strobe programmable configured active-low (HAS) following reset. Port 8-When HI08 configured GPIO through HI08 Port Control Register, this signal individually programmed input output through HI08 Data Direction Register.
Type
Input
State During Reset1,2
Ignored Input
HAS/HAS
Input
Input Output
Input
Ignored Input
Host Address Input 1-When HI08 programmed interface with nonmultiplexed host function selected, this signal line host address (HA1) input bus. Host Address 8-When HI08 programmed interface with multiplexed host function selected, this signal line host address (HA8) input bus. Port 9-When HI08 configured GPIO through HI08 Port Control Register, this signal individually programmed input output through HI08 Data Direction Register.
Input
Input Output
Input
Ignored Input
Host Address Input 2-When HI08 programmed interface with nonmultiplexed host function selected, this signal line host address (HA2) input bus. Host Address 9-When HI08 programmed interface with multiplexed host function selected, this signal line host address (HA9) input bus. Port 10-When HI08 configured GPIO through HI08 Port Control Register, this signal individually programmed input output through HI08 Data Direction Register.
Input
PB10
Input Output
HCS/HCS
Input
Ignored Input
Host Chip Select-When HI08 programmed interface with nonmultiplexed host function selected, this signal host chip select (HCS) input. polarity chip select programmable configured active-low (HCS) after reset. Host Address 10-When HI08 programmed interface with multiplexed host function selected, this signal line host address (HA10) input bus. Port 13-When HI08 configured GPIO through HI08 Port Control Register, this signal individually programmed input output through HI08 Data Direction Register.
HA10
Input
PB13
Input Output
Input
Ignored Input
Host Read/Write-When HI08 programmed interface with singledata-strobe host function selected, this signal Host Read/Write (HRW) input. Host Read Data-When HI08 programmed interface with doubledata-strobe host function selected, this signal strobe Schmitt-trigger input. polarity data strobe programmable configured active-low (HRD) after reset. Port 11-When HI08 configured GPIO through HI08 Port Control Register, this signal individually programmed input output through HI08 Data Direction Register.
HRD/HRD
Input
PB11
Input Output
DSP56309 Technical Data, Rev. Freescale Semiconductor
Signals/Connections
Table 1-11.
Signal Name
HDS/HDS
Host Interface (Continued)
Signal Description
Host Data Strobe-When HI08 programmed interface with singledata-strobe host function selected, this signal host data strobe (HDS) Schmitt-trigger input. polarity data strobe programmable configured active-low (HDS) following reset. Host Write Data-When HI08 programmed interface with doubledata-strobe host function selected, this signal host write data strobe (HWR) Schmitt-trigger input. polarity data strobe programmable configured active-low (HWR) following reset. Port 12-When HI08 configured GPIO through HI08 Port Control Register, this signal individually programmed input output through HI08 Data Direction Register.
Type
Input
State During Reset1,2
Ignored Input
HWR/HWR
Input
PB12
Input Output
HREQ/HREQ
Output
Ignored Input
Host Request-When HI08 programmed interface with single host request host function selected, this signal host request (HREQ) output. polarity host request programmable configured active-low (HREQ) following reset. host request programmed driven open-drain output. Transmit Host Request-When HI08 programmed interface with double host request host function selected, this signal transmit host request (HTRQ) output. polarity host request programmable configured active-low (HTRQ) following reset. host request programmed driven open-drain output. Port 14-When HI08 configured GPIO through HI08 Port Control Register, this signal individually programmed input output through HI08 Data Direction Register.
HTRQ/HTRQ
Output
PB14
Input Output
HACK/HACK
Input
Ignored Input
Host Acknowledge-When HI08 programmed interface with single host request host function selected, this signal host acknowledge (HACK) Schmitt-trigger input. polarity host acknowledge programmable configured active-low (HACK) after reset. Receive Host Request-When HI08 programmed interface with double host request host function selected, this signal receive host request (HRRQ) output. polarity host request programmable configured active-low (HRRQ) after reset. host request programmed driven open-drain output. Port 15-When HI08 configured GPIO through HI08 Port Control Register, this signal individually programmed input output through HI08 Data Direction Register.
HRRQ/HRRQ
Output
PB15
Input Output
Notes:
Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, signal tri-stated. Wait processing state does affect signal state. inputs tolerant.
DSP56309 Technical Data, Rev. 1-10 Freescale Semiconductor
Enhanced Synchronous Serial Interface (ESSI0)
Enhanced Synchronous Serial Interface (ESSI0)
synchronous serial interfaces (ESSI0 ESSI1) provide full-duplex serial port serial communication with variety serial devices, including more industry-standard codecs, other DSPs, microprocessors, peripherals that implement serial peripheral interface (SPI).
Table 1-12.
Signal Name
SC00
Enhanced Synchronous Serial Interface
Signal Description
Serial Control 0-For asynchronous mode, this signal used receive clock (Schmitt-trigger input). synchronous mode, this signal used either transmitter output serial flag Port 0-The default configuration following reset GPIO input PC0. When configured PC0, signal direction controlled through Port Direction Register. signal configured ESSI signal SC00 through Port Control Register.
Type
Input Output
State During Reset1,2
Ignored Input
Input Output
SC01
Input/Output
Ignored Input
Serial Control 1-For asynchronous mode, this signal receiver frame sync I/O. synchronous mode, this signal used either transmitter output serial flag Port 1-The default configuration following reset GPIO input PC1. When configured PC1, signal direction controlled through Port Direction Register. signal configured ESSI signal SC01 through Port Control Register.
Input Output
SC02
Input/Output
Ignored Input
Serial Control Signal 2-The frame sync both transmitter receiver synchronous mode, transmitter only asynchronous mode. When configured output, this signal internally generated frame sync signal. When configured input, this signal receives external frame sync signal transmitter (and receiver synchronous operation). Port 2-The default configuration following reset GPIO input PC2. When configured PC2, signal direction controlled through Port Direction Register. signal configured ESSI signal SC02 through Port Control Register.
Input Output
SCK0
Input/Output
Ignored Input
Serial Clock-Provides serial rate clock ESSI. SCK0 clock input output, used both transmitter receiver synchronous modes transmitter asynchronous modes. Although external serial clock independent asynchronous system clock, must exceed minimum clock cycle time (that system clock frequency must least three times external ESSI clock frequency). ESSI needs least three phases inside each half serial clock.
Input Output
Port 3-The default configuration following reset GPIO input PC3. When configured PC3, signal direction controlled through Port Direction Register. signal configured ESSI signal SCK0 through Port Control Register. Ignored Input Serial Receive Data-Receives serial data transfers data ESSI Receive Shift Register. SRD0 input when data received. Port 4-The default configuration following reset GPIO input PC4. When configured PC4, signal direction controlled through Port Direction Register. signal configured ESSI signal SRD0 through Port Control Register.
SRD0
Input
Input Output
DSP56309 Technical Data, Rev. Freescale Semiconductor 1-11
Signals/Connections
Table 1-12.
Signal Name
STD0
Enhanced Synchronous Serial Interface (Continued)
State During Reset1,2
Ignored Input
Type
Output
Signal Description
Serial Transmit Data-Transmits data from Serial Transmit Shift Register. STD0 output when data transmitted. Port 5-The default configuration following reset GPIO input PC5. When configured PC5, signal direction controlled through Port Direction Register. signal configured ESSI signal STD0 through Port Control Register.
Input Output
Notes:
Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, signal tri-stated. Wait processing state does affect signal state. inputs tolerant.
Enhanced Synchronous Serial Interface (ESSI1)
Table 1-13.
Signal Name
SC10
Enhanced Serial Synchronous Interface
Signal Description
Serial Control 0-For asynchronous mode, this signal used receive clock (Schmitt-trigger input). synchronous mode, this signal used either transmitter output serial flag Port 0-The default configuration following reset GPIO input PD0. When configured PD0, signal direction controlled through Port Direction Register. signal configured ESSI signal SC10 through Port Control Register.
Type
Input Output
State During Reset1,2
Ignored Input
Input Output
SC11
Input/Output
Ignored Input
Serial Control 1-For asynchronous mode, this signal receiver frame sync I/O. synchronous mode, this signal used either Transmitter output Serial Flag Port 1-The default configuration following reset GPIO input PD1. When configured PD1, signal direction controlled through Port Direction Register. signal configured ESSI signal SC11 through Port Control Register.
Input Output
SC12
Input/Output
Ignored Input
Serial Control Signal 2-The frame sync both transmitter receiver synchronous mode transmitter only asynchronous mode. When configured output, this signal internally generated frame sync signal. When configured input, this signal receives external frame sync signal transmitter (and receiver synchronous operation). Port 2-The default configuration following reset GPIO input PD2. When configured PD2, signal direction controlled through Port Direction Register. signal configured ESSI signal SC12 through Port Control Register.
Input Output
DSP56309 Technical Data, Rev. 1-12 Freescale Semiconductor
Enhanced Synchronous Serial Interface (ESSI1)
Table 1-13.
Signal Name
SCK1
Enhanced Serial Synchronous Interface (Continued)
State During Reset1,2
Ignored Input
Type
Input/Output
Signal Description
Serial Clock-Provides serial rate clock ESSI. SCK1 clock input output used both transmitter receiver synchronous modes transmitter asynchronous modes. Although external serial clock independent asynchronous system clock, must exceed minimum clock cycle time (that system clock frequency must least three times external ESSI clock frequency). ESSI needs least three phases inside each half serial clock.
Input Output
Port 3-The default configuration following reset GPIO input PD3. When configured PD3, signal direction controlled through Port Direction Register. signal configured ESSI signal SCK1 through Port Control Register. Ignored Input Serial Receive Data-Receives serial data transfers data ESSI Receive Shift Register. SRD1 input when data being received. Port 4-The default configuration following reset GPIO input PD4. When configured PD4, signal direction controlled through Port Direction Register. signal configured ESSI signal SRD1 through Port Control Register. Ignored Input Serial Transmit Data-Transmits data from Serial Transmit Shift Register. STD1 output when data being transmitted. Port 5-The default configuration following reset GPIO input PD5. When configured PD5, signal direction controlled through Port Direction Register. signal configured ESSI signal STD1 through Port Control Register.
SRD1
Input
Input Output
STD1
Output
Input Output
Notes:
Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, signal tri-stated. Wait processing state does affect signal state. inputs tolerant.
DSP56309 Technical Data, Rev. Freescale Semiconductor 1-13
Signals/Connections
1.10 Serial Communication Interface (SCI)
provides full duplex port serial communication with other DSPs, microprocessors, peripherals such modems.
Table 1-14.
Signal Name
Input
Serial Communication Interface
Signal Description
Serial Receive Data-Receives byte-oriented serial data transfers Receive Shift Register. Port 0-The default configuration following reset GPIO input PE0. When configured PE0, signal direction controlled through Port Direction Register. signal configured signal through Port Control Register.
Type
State During Reset1,2
Ignored Input
Input Output
Output Input Output
Ignored Input
Serial Transmit Data-Transmits data from Transmit Data Register. Port 1-The default configuration following reset GPIO input PE1. When configured PE1, signal direction controlled through Port Direction Register. signal configured signal through Port Control Register.
SCLK
Input/Output
Ignored Input
Serial Clock-Provides input output clock used transmitter and/or receiver. Port 2-The default configuration following reset GPIO input PE2. When configured PE2, signal direction controlled through Port Direction Register. signal configured signal SCLK through Port Control Register.
Input Output
Notes:
Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, signal tri-stated. Wait processing state does affect signal state. inputs tolerant.
DSP56309 Technical Data, Rev. 1-14 Freescale Semiconductor
Timers
1.11 Timers
DSP56309 three identical independent timers. Each timer internal external clocking either interrupt DSP56309 after specified number events (clocks) signal external device after counting specific number internal events.
Table 1-15.
Signal Name
TIO0
Triple Timer Signals
Signal Description
Type
Input Output
State During Reset1,2
Ignored Input
Timer Schmitt-Trigger Input/Output- When Timer functions external event counter measurement mode, TIO0 used input. When Timer functions watchdog, timer, pulse modulation mode, TIO0 used output. default mode after reset GPIO input. TIO0 changed output configured timer through Timer Control/Status Register (TCSR0).
TIO1
Input Output
Ignored Input
Timer Schmitt-Trigger Input/Output- When Timer functions external event counter measurement mode, TIO1 used input. When Timer functions watchdog, timer, pulse modulation mode, TIO1 used output. default mode after reset GPIO input. TIO1 changed output configured timer through Timer Control/Status Register (TCSR1).
TIO2
Input Output
Ignored Input
Timer Schmitt-Trigger Input/Output- When Timer functions external event counter measurement mode, TIO2 used input. When Timer functions watchdog, timer, pulse modulation mode, TIO2 used output. default mode after reset GPIO input. TIO2 changed output configured timer through Timer Control/Status Register (TCSR2).
Notes:
Stop state, signal maintains last state follows: last state input, signal ignored input. last state output, signal tri-stated. Wait processing state does affect signal state. inputs tolerant.
DSP56309 Technical Data, Rev. Freescale Semiconductor 1-15
Signals/Connections
1.12 JTAG OnCE Interface
DSP56300 family particular DSP56309 support circuit-board test strategies based IEEE® Std. 1149.1test access port boundary scan architecture, industry standard developed under sponsorship Test Technology Committee IEEE JTAG. OnCE module provides means interface nonintrusively with DSP56300 core peripherals that examine registers, memory, on-chip peripherals. Functions OnCE module provided through JTAG signals. programming models, chapter debugging support DSP56300 Family Manual.
Table 1-16.
Signal Name
JTAG/OnCE Interface
Signal Description
Test Clock-A test clock input signal synchronize JTAG test logic. Test Data Input-A test data serial input signal test instructions data. sampled rising edge internal pull-up resistor. Test Data Output-A test data serial output signal test instructions data. actively driven shift-IR shift-DR controller states. changes falling edge TCK. Test Mode Select-Sequences test controller's state machine. sampled rising edge internal pull-up resistor. Test Reset-Initializes test controller asynchronously. TRST internal pull-up resistor. TRST must asserted after powerup. Debug Event-As input, initiates Debug mode from external command controller, and, open-drain output, acknowledges that chip entered Debug mode. input, causes DSP56300 core finish executing current instruction, save instruction pipeline information, enter Debug mode, wait commands entered from debug serial input line. This signal asserted output three clock cycles when chip enters Debug mode result debug request result meeting breakpoint condition. internal pull-up resistor. This signal standard part JTAG controller. signal connects directly OnCE module initiate debug mode directly provide direct external indication that chip entered Debug mode. other interface with OnCE module must occur through JTAG port.
Type
Input Input Output
State During Reset
Input Input Tri-stated
TRST
Input Input Input/ Output (open-drain)
Input Input Input
Note: inputs tolerant.
DSP56309 Technical Data, Rev. 1-16 Freescale Semiconductor
Specifications
Note: DSP56309 fabricated high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs outputs. DSP56309 specifications preliminary from design simulations, fully tested guaranteed. Finalized specifications will published after full characterization device qualifications complete.
Maximum Ratings
CAUTION
This device contains circuitry protecting against damage high static voltage electrical fields; however, normal precautions should taken avoid exceeding maximum voltage ratings. Reliability enhanced unused inputs tied appropriate logic voltage level (for example, either VCC).
calculation timing requirements, adding maximum value specification minimum value another specification does yield reasonable sum. maximum specification calculated using worst case variation process parameter values direction. minimum specification calculated using worst case same parameters opposite direction. Therefore, "maximum" value specification never occurs same device that "minimum" value another specification; adding maximum minimum represents condition that never exist.
Absolute Maximum Ratings
Table 2-1.
Rating
Supply Voltage input voltages excluding tolerant" inputs tolerant" input voltages2 Current drain excluding Operating temperature range Storage temperature Notes:
Absolute Maximum Ratings1
Symbol
VIN5 TSTG
Value
Unit
+4.0 -0.3 +100 +150
Absolute maximum ratings stress ratings only, functional operation maximum guaranteed. Stress beyond maximum rating affect device reliability cause permanent damage device. power-up, ensure that voltage difference between tolerant pins chip never exceeds
DSP56309 Technical Data, Rev. Freescale Semiconductor
Specifications
Thermal Characteristics
Table 2-2.
Characteristic
Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2 Thermal characterization parameter Notes:
Thermal Characteristics
TQFP Value
49.3
Symbol
MAP-BGA3 Value
49.4 12.0
MAP-BGA4 Value
28.5
Unit
°C/W °C/W °C/W
Junction-to-ambient thermal resistance based measurements horizontal single-sided printed circuit board JEDEC Specification JESD51-3. Junction-to-case thermal resistance based measurements using cold plate SEMI G30-88, with exception that cold plate temperature used case temperature. These simulated values. note test board conditions. These simulated values. test board 2-ounce signal layers 1-ounce solid ground planes internal test board.
Electrical Characteristics
Table 2-3.
Characteristics
Supply voltage Input high voltage D[0-23], MOD1/IRQ1, RESET, PINIT/NMI JTAG/ESSI/SCI/Timer/HI08 pins EXTAL8 Input voltage D[0-23], MOD1/IRQ1, RESET, PINIT JTAG/ESSI/SCI/Timer/HI08 pins EXTAL8 Input leakage current High impedance (off-state) input current Output high voltage (IOH -0.4 mA)5,7 CMOS (IOH µA)5 Output voltage (IOL open-drain pins mA)5,7 CMOS (IOL Internal supply current2: Normal mode Wait mode3 Stop mode4 supply current Input capacitance5
Electrical Characteristics6
Symbol
Unit
VIHP VIHX
5.25
VILP VILX ITSI
-0.3 -0.3 -0.3
0.01
0.01
ICCI ICCW ICCS
DSP56309 Technical Data, Rev. Freescale Semiconductor
Electrical Characteristics
Table 2-3.
Characteristics
Notes:
Electrical Characteristics6 (Continued)
Symbol Unit
Refers MODA/IRQA, MODB/IRQB, MODC/IRQC, MODD/IRQD pins. Section provides formula compute estimated current requirements Normal mode. order obtain these results, inputs must terminated (that allowed float). Measurements based synthetic intensive benchmarks (see Appendix power consumption numbers this specification percent measured results this benchmark. This reflects typical applications. Typical internal supply current measured with 100°C. order obtain these results, inputs must terminated (that allowed float). order obtain these results, inputs that disconnected Stop mode must terminated (that allowed float). XTAL signals disabled during Stop state. Periodically sampled percent tested. -40°C +100 This characteristic does apply XTAL PCAP. Driving EXTAL VIHX high VILX value cause additional power consumption current). minimize power consumption, minimum VIHX should lower than maximum VILX should higher than
Electrical Characteristics
timing waveforms shown electrical characteristics section tested with maximum minimum pins except EXTAL, which tested using input levels shown Note previous table. timing specifications, which referenced device input signal, measured production with respect percent point respective input signal transition. DSP56309 output levels measured with production test machine reference levels respectively. Note: Although minimum value frequency EXTAL MHz, device test conditions rated speed.
2.5.1
Internal Clocks
Table 2-4.
Characteristics Symbol
MF)/ (PDF Ef/2
Internal Clocks, CLKOUT
Expression1,
Internal operation frequency CLKOUT with enabled Internal operation frequency CLKOUT with disabled Internal clock CLKOUT high period With disabled With enabled With enabled
0.49 DF/MF 0.47 DF/MF 0.49 DF/MF 0.47 DF/MF
0.51 DF/MF 0.53 DF/MF 0.51 DF/MF 0.53 DF/MF
Internal clock CLKOUT period With disabled With enabled With enabled
DF/MF
Internal clock CLKOUT cycle time with enabled
DSP56309 Technical Data, Rev. Freescale Semiconductor
Specifications
Table 2-4.
Characteristics
Internal clock CLKOUT cycle time with disabled Instruction cycle time Notes:
Internal Clocks, CLKOUT (Continued)
Expression1,
Symbol
ICYC
Division Factor; External frequency; External clock cycle; Multiplication Factor; Predivision Factor; internal clock cycle Clock Generation section DSP56300 Family Manual detailed discussion PLL.
2.5.2
External Clock Operation
DSP56309 system clock derived from on-chip oscillator externally supplied. on-chip oscillator, connect crystal associated resistor/capacitor components EXTAL XTAL; examples shown Figure 2-1.
EXTAL
XTAL Note: Make sure that PCTL Register: XTLD (bit fOSC kHz, XTLR (bit
Suggested Component Values: fOSC fOSC Calculations were done 4/20 crystal with following parameters: CLof 30/20 series resistance 100/20 drive level
XTAL1
Fundamental Frequency Crystal Oscillator
Figure 2-1.
Crystal Oscillator Circuits
externally-supplied square wave voltage source used, disable internal oscillator circuit during bootup setting XTLD (PCTL Register 1-see DSP56309 User's Manual). external square wave source connects EXTAL; XTAL physically connected board socket. Figure shows relationship between EXTAL input internal clock CLKOUT.
EXTAL VILX CLKOUT with disabled Midpoint VIHX
Note:
midpoint (VIHX VILX).
CLKOUT with enabled
Figure 2-2.
External Clock Timing
DSP56309 Technical Data, Rev. Freescale Semiconductor
Electrical Characteristics
Table 2-5.
Clock Operation
Symbol
100.0
Characteristics
Frequency EXTAL (EXTAL Frequency) rise fall time this external clock should maximum. EXTAL input high1, With disabled (46.7%-53.3% duty cycle6) With enabled (42.5%-57.5% duty cycle6) EXTAL input With disabled (46.7%-53.3% duty cycle6) With enabled (42.5%-57.5% duty cycle6) EXTAL cycle time2 With disabled With enabled Internal clock change from EXTAL fall with disabled a.Internal clock rising edge from EXTAL rising edge with enabled MHz) Internal clock falling edge from EXTAL falling edge with enabled MHz)3,5
4.67 4.25 4.67 4.25 10.00 10.00
157.0 157.0 273.1 11.0
ICYC 20.0 10.00
Instruction cycle time ICYC (see Table 2-4) (46.7%-53.3% duty cycle) With disabled With enabled
8.53
Notes:
Measured percent input transition. maximum value enabled given minimum frequency (see Table 2-4) maximum Periodically sampled percent tested. maximum value enabled given minimum frequency maximum skew guaranteed other value. indicated duty cycle specified maximum frequency which part rated. minimum clock high time required correction operation, however, remains same lower operating frequencies; therefore, when lower clock frequency used, signal symmetry vary from specified duty cycle long minimum high time time requirements met.
2.5.3
Phase Lock Loop (PLL) Characteristics
Table 2-6.
Characteristics
Characteristics
Unit
Voltage Controlled Oscillator (VCO) frequency when enabled 2/PDF) external capacitor (PCAP VCCP) (CPCAP1) Note:
(580
(780 1470
PCAP value capacitor (connected between PCAP VCCP) computed using appropriate expression listed above.
DSP56309 Technical Data, Rev. Freescale Semiconductor
Specifications
2.5.4
Reset, Stop, Mode Select, Interrupt Timing
Table 2-7. Reset, Stop, Mode Select, Interrupt Timing6
Characteristics
Delay from RESET assertion pins reset value3 Required RESET duration4 Power external clock generator, disabled Power external clock generator, enabled Power internal oscillator During STOP, XTAL disabled (PCTL During STOP, XTAL enabled (PCTL During normal operation Delay from asynchronous RESET deassertion first external address output (internal reset deassertion)5 Minimum Maximum Synchronous reset set-up time from RESET deassertion CLKOUT Transition Minimum Maximum Synchronous reset deasserted, delay time from CLKOUT Transition first external address output Minimum Maximum Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory access address valid Caused first interrupt instruction fetch Caused first interrupt instruction execution Delay from IRQA, IRQB, IRQC, IRQD, assertion generalpurpose transfer output valid caused first interrupt instruction execution Delay from address output valid caused first interrupt instruction execute interrupt request deassertion level sensitive fast interrupts1, Delay from assertion interrupt request deassertion level sensitive fast interrupts1, Delay from assertion interrupt request deassertion level sensitive fast interrupts1, DRAM SRAM SRAM SRAM Synchronous interrupt set-up time from IRQA, IRQB, IRQC, IRQD, assertion CLKOUT Transition Synchronous interrupt delay time from CLKOUT Transition first external address output valid caused first instruction fetch after coming Wait Processing state Minimum Maximum
Expression
1000 75000 75000 500.0 10.0 0.75 0.75 25.0 25.0
Unit
26.0
3.25 20.25
34.5
212.5
10.0
3.25 20.25
33.5 30.0
203.5
4.25 7.25
44.5 74.5 105.0
3.75) 10.94
Note
3.25) 10.94
Note
3.5) 10.94 3.5) 10.94 10.94 2.5) 10.94
Note Note Note Note
8.25 24.75
83.5
252.5
DSP56309 Technical Data, Rev. Freescale Semiconductor
Electrical Characteristics
Table 2-7.
Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics
Duration IRQA assertion recover from Stop state Delay from IRQA assertion fetch first instruction (when exiting Stop)2, active during Stop (PCTL Stop delay enabled (Operating Mode Register active during Stop (PCTL Stop delay enabled (Operating Mode Register active during Stop (PCTL (Implies Stop Delay) Duration level sensitive IRQA assertion ensure interrupt service (when exiting Stop)2, active during Stop (PCTL Stop delay enabled (Operating Mode Register active during Stop (PCTL Stop delay enabled (Operating Mode Register active during Stop (PCTL (implies Stop delay) Interrupt Request Rate HI08, ESSI, SCI, Timer IRQ, (edge trigger) IRQ, (level trigger) Request Rate Data read from HI08, ESSI, Data write HI08, ESSI, Timer IRQ, (edge trigger) Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory (DMA source) access address valid
Expression
Unit
(128 PLC/2) (23.75 232.5 12.3 0.5) (8.25 0.5) 87.5 97.5
(128K PLC/2) (20.5 0.5) Maximum: Maximum: Minimum: 4.25
13.6 12.3 55.0 30.3
120.0 80.0 80.0 120.0 60.0 70.0 20.0 30.0
DSP56309 Technical Data, Rev. Freescale Semiconductor
Specifications
Table 2-7.
Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Notes:
Characteristics
Expression
Unit
When fast interrupts used IRQA, IRQB, IRQC, IRQD defined level-sensitive, timings through apply prevent multiple interrupt service. avoid these timing restrictions, deasserted Edge-triggered mode recommended when fast interrupts used. Long interrupts recommended Level-sensitive mode. This timing depends several settings: disable, using internal oscillator (PLL Control Register (PCTL) oscillator disabled during Stop (PCTL stabilization delay required assure that oscillator stable before programs executed. Resetting Stop delay (Operating Mode Register provides proper delay. While Operating Mode Register set, recommended, these specifications guarantee timings that case. disable, using internal oscillator (PCTL oscillator enabled during Stop (PCTL 17=1), stabilization delay required recovery minimal (Operating Mode Register setting ignored). disable, using external clock (PCTL stabilization delay required recovery time defined PCTL Operating Mode Register settings. enable, PCTL shutdown during Stop. Recovering from Stop requires locked. lock procedure duration, Lock Cycles (PLC), range 1000 cycles. This procedure occurs parallel with stop delay counter, stop recovery ends when last these events occurs. stop delay counter completes count lock procedure completion. value disable maximum value 4096 (maximum divided desired internal frequency (that 4096/66 µs). During stabilization period, constant, their width vary, timing vary well. Periodically sampled percent tested. Value depends clock source: external clock generator, RESET duration measured while RESET asserted, valid, EXTAL input active valid. internal oscillator, RESET duration measured while RESET asserted valid. specified timing reflects crystal oscillator stabilization time after power-up. This number affected both specifications crystal other components connected oscillator reflects worst case conditions. When valid, other "required RESET duration" conditions specified above) have been met, device circuitry uninitialized state that result significant power consumption heat-up. Designs should minimize this state shortest possible duration. does lose lock. -40°C +100°C, number wait states (measured clock cycles, number TC). expression compute maximum value. RESET
Pins Reset Value
A[0-17]
First Fetch
Figure 2-3.
Reset Timing
DSP56309 Technical Data, Rev. Freescale Semiconductor
Electrical Characteristics
CLKOUT
RESET
A[0-17]
Figure 2-4.
Synchronous Reset Timing
A[0-17]
First Interrupt Instruction Execution/Fetch
IRQA, IRQB, IRQC, IRQD,
First Interrupt Instruction Execution
General Purpose
IRQA, IRQB, IRQC, IRQD,
General-Purpose Figure 2-5. External Fast Interrupt Timing
DSP56309 Technical Data, Rev. Freescale Semiconductor
Specifications
IRQA, IRQB, IRQC, IRQD,
IRQA, IRQB, IRQC, IRQD,
Figure 2-6.
External Interrupt Timing (Negative Edge-Triggered)
CLKOUT
IRQA, IRQB, IRQC, IRQD,
A[0-17]
Figure 2-7.
Synchronous Interrupt from Wait State Timing
RESET
IRQA, IRQB, IRQC, IRQD,
MODA, MODB, MODC, MODD, PINIT
Figure 2-8.
Operating Mode Select Timing
DSP56309 Technical Data, Rev. 2-10 Freescale Semiconductor
Electrical Characteristics
IRQA
A[0-17]
First Instruction Fetch
Figure 2-9.
Recovery from Stop State Using IRQA
IRQA
A[0-17] First IRQA Interrupt Instruction Fetch
Figure 2-10.
Recovery from Stop State Using IRQA Interrupt Service
A[0-17]
Source Address
IRQA, IRQB, IRQC, IRQD, First Interrupt Instruction Execution
Figure 2-11.
External Memory Access (DMA Source) Timing
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-11
Specifications
2.5.5
External Memory Expansion Port (Port
2.5.5.1 SRAM Timing
Table 2-8.
SRAM Read Write Accesses
Symbol
Characteristics
Address valid assertion pulse width2
Expression1
-4.0 -4.0 -4.0 0.25 0.75 1.25 -4.0 -4.0 0.5) 0.25 1.25 2.25 0.75) 0.25) 0.75) -0.25) 0.25 1.25 2.25 0.75 -3.7 0.25 -0.25 -3.7
Unit
16.0 56.0 106.0 10.5 11.0 16.0 31.0 18.5 13.5 10.5 20.5 -1.2 -6.2
12.5
Address valid assertion
assertion pulse width
deassertion address valid
Address valid input data valid assertion input data valid deassertion data valid (data hold time) Address valid deassertion
tAA, tOHZ (tDW
Data valid deassertion (data setup time) Data hold time from deassertion
assertion data active
DSP56309 Technical Data, Rev. 2-12 Freescale Semiconductor
Electrical Characteristics
Table 2-8.
SRAM Read Write Accesses (Continued)
Symbol
Characteristics
deassertion data high impedance
Expression1
0.25 1.25 2.25 1.25 2.25 3.25 0.75 1.75 2.75 -4.0 -4.0 -4.0 -4.0 -4.0 0.25) 0.25 -2.0 1.25 2.25 0.25
Unit
18.5 28.5 13.5 23.5 21.0 31.0 10.5 20.5
12.7 22.7
Previous deassertion data active (write)
deassertion time
deassertion time
Address valid assertion assertion pulse width deassertion address valid
Notes:
setup before deassertion4 hold after deassertion
number wait states specified BCR. expression used compute number listed minimum maximum value, appropriate. Timings 100, guaranteed design, tested. timings measured from Vcc. Timing relative deassertion edge even remains asserted. -40°C +100°C,
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-13
Specifications
A[0-17] AA[0-3]
D[0-23] Note: Address lines A[0-17] hold their state after read write operation. AA[0-3] hold their state after read write operation. Data
Figure 2-12.
SRAM Read Access
A[0-17] AA[0-3]
D[0-23] Note: Address lines A[0-17] hold their state after read write operation. AA[0-3] hold their state after read write operation. Data
Figure 2-13.
SRAM Write Access
DSP56309 Technical Data, Rev. 2-14 Freescale Semiconductor
Electrical Characteristics
2.5.5.2 DRAM Timing
selection guides Figure 2-14 Figure 2-17 primary selection only. Final selection should based timing following tables. example, selection guide suggests that four wait states must used operation with Page Mode DRAM. However, consulting appropriate table, designer evaluate whether fewer wait states might suffice determining which timing prevents operation MHz, running chip slightly lower frequency (for example, MHz), using faster DRAM becomes available), manipulating control factors such capacitive resistive load improve overall system performance.
DRAM type (tRAC Note: This figure should used primary selection. exact detailed timings, following tables.
Chip frequency (MHz)
Wait states Wait states
Wait states Wait states
Figure 2-14.
DRAM Page Mode Wait State Selection Guide
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-15
Specifications
Table 2-9.
DRAM Page Mode Timings, Three Wait States1,2,3
Symbol Expression4
Unit
40.0
Characteristics
Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses
tCAC tOFF tRSH tRHCP tCAS
35.0
14.3 24.3 19.3
assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion assertion BRW[1-0] 01-not applicable BRW[1-0] BRW[1-0] deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid6 assertion data active deassertion data high impedance
4.75 6.75
21.0 41.0 16.0 41.5 61.5 11.0 21.0 36.0 18.3 30.5 33.2 28.2 21.0 31.0
tCRP
Notes:
tASC tCAH tRAL tRCS tRCH tWCH tRWL tCWL tWCS tROH
-4.0 1.25 0.75 2.25 3.75 3.25 1.25
0.75 0.25
number wait states Page mode access specified DRAM Control Register. refresh period specified DRAM Control Register. asynchronous delays specified expressions valid DSP56309. timings calculated worst case. Some timings better specific cases (for example, equals read-after-read write-after-write sequences). expression used compute number listed minimum maximum value listed, appropriate. BRW[1-0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of pageaccess. deassertion always occurs after deassertion; therefore, restricted timing tOFF
DSP56309 Technical Data, Rev. 2-16 Freescale Semiconductor
Electrical Characteristics
Table 2-10.
DRAM Page Mode Timings, Four Wait States1,2,3
Symbol Expression4
2.75 3.75
Unit
50.0
Characteristics
Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses
tCAC tOFF tRSH tRHCP tCAS
45.0
21.8 31.8 26.8
assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion assertion BRW[1-0] 01-Not applicable BRW[1-0] BRW[1-0] deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid6 assertion data active deassertion data high impedance
5.25 7.25
31.0 56.0 21.0 46.5 66.5 16.0 31.0 46.0 28.3 40.5 43.2 33.2 31.0 41.0
tCRP
Notes:
tASC tCAH tRAL tRCS tRCH tWCH tRWL tCWL tWCS tROH
-4.0 1.25 1.25 3.25 4.75 -4.3 3.75 1.25 3.25
0.75 0.25
number wait states Page mode access specified DRAM Control Register. refresh period specified DRAM Control Register. asynchronous delays specified expressions valid DSP56309. timings calculated worst case. Some timings better specific cases (for example, equals read-after-read write-after-write sequences). expressions used calculate maximum minimum value listed, appropriate. BRW[1-0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion always occurs after deassertion; therefore, restricted timing tOFF
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-17
Specifications
A[0-17] Column Address D[0-23] Data Data Data Column Address Last Column Address
Figure 2-15.
DRAM Page Mode Write Accesses
Column Address Column Address D[0-23] Data Data Last Column Address
A[0-17]
Data
Figure 2-16.
DRAM Page Mode Read Accesses
DSP56309 Technical Data, Rev. 2-18 Freescale Semiconductor
Electrical Characteristics
DRAM Type (tRAC
Note:
This figure should used primary selection. exact detailed timings, following tables.
Wait States Wait States
Chip Frequency (MHz)
Wait States Wait States
Figure 2-17. Table 2-11.
DRAM Out-of-Page Wait State Selection Guide
DRAM Out-of-Page Refresh Timings, Eleven Wait States1,2
Symbol
tRAC tCAC tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR 4.25 7.75 5.25 6.25 3.75 1.75 5.75 4.25 4.25
Characteristics
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion
Expression3
6.25 3.75
Unit
120.0 38.5 73.5 48.5 58.5 33.5 21.0 13.5 53.5 36.5 38.5
55.5 30.5 38.0 29.0 21.5
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-19
Specifications
Table 2-11.
Notes:
DRAM Out-of-Page Refresh Timings, Eleven Wait States1,2 (Continued)
Characteristics Symbol
tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tWCS tCSR tRPC tROH
Expression3
1.75 0.75 5.25 7.75 1.75 0.25 11.5 11.75 -4.3 10.25 -4.3 5.75 5.25 7.75 2.75 11.5 -7.0
Unit
93.0 13.5 48.5 73.5 56.0 26.0 13.8 45.8 70.8 110.5 113.2 98.2 53.5 48.5 73.5 60.7 11.0 23.5 111.0
assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion
assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid deassertion data valid assertion data active deassertion data high impedance
0.75 0.25
number wait states out-of-page access specified DRAM Control Register. refresh period specified DRAM Control Register. expression compute maximum minimum value listed both expression includes Either tRCH tRRH must satisfied read cycles. deassertion always occurs after deassertion; therefore, restricted timing tOFF
DSP56309 Technical Data, Rev. 2-20 Freescale Semiconductor
Electrical Characteristics
Table 2-12.
Notes:
DRAM Out-of-Page Refresh Timings, Fifteen Wait States1,2
Symbol
tRAC tCAC tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tWCS tCSR tRPC tROH 0.75 0.25
Characteristics
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid deassertion data valid5 assertion data active deassertion data high impedance
Expression3
8.25 4.75 6.25 9.75 6.25 8.25 4.75 2.75 7.75 6.25 6.25 2.75 0.75 6.25 9.75 1.75 0.25 15.5 15.75 -4.3 14.25 -4.3 8.75 6.25 9.75 4.75 15.5 -5.7
Unit
160.0 58.5 93.5 58.5 78.5 43.5 33.0 25.5 73.5 56.5 58.5 23.5 58.5 93.5 66.0 46.2 13.8 55.8 90.8 150.5 153.2 138.2 83.5 58.5 93.5 90.7 11.0 43.5 151.0
76.8 41.8 49.3 37.0 29.5 134.3
number wait states out-of-page access specified DRAM Control Register. refresh period specified DRAM Control Register. expression compute maximum minimum value listed both expression includes Either tRCH tRRH must satisfied read cycles. deassertion always occurs after deassertion; therefore, restricted timing tOFF
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-21
Specifications
A[0-17] Address D[0-23] Data Column Address
Figure 2-18.
DRAM Out-of-Page Read Access
DSP56309 Technical Data, Rev. 2-22 Freescale Semiconductor
Electrical Characteristics
Column Address
A[0-17]
Address
D[0-23]
Data
Figure 2-19.
DRAM Out-of-Page Write Access
Figure 2-20.
DRAM Refresh Access
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-23
Specifications
2.5.5.3 Synchronous Timings
Table 2-13.
External Synchronous Timings1,2
Expression3,4,5
0.25
Unit
10.0
Characteristics
CLKOUT high address, valid6 CLKOUT high address, invalid valid CLKOUT high (set-up time) CLKOUT high invalid (hold time) CLKOUT high data active CLKOUT high data valid CLKOUT high data invalid CLKOUT high data high impedance Data valid CLKOUT high (set-up) CLKOUT high data invalid (hold) CLKOUT high assertion CLKOUT high deassertion CLKOUT high assertion
0.25
0.25 0.25 0.25 0.25
maximum: 0.75 maximum:
Notes:
CLKOUT high deassertion
external synchronous timings only reference clock relative timings. Synchronous Arbitration recommended. Asynchronous mode whenever possible. number wait states specified BCR. assertion refers next rising edge CLKOUT. expression compute maximum minimum value listed, appropriate. timing 210, minimum absolute value. T198 T199 valid Address Trace mode Operating Mode Register set. when this mode enabled, status (See T212) determine whether access referenced A[0-17] internal external.
DSP56309 Technical Data, Rev. 2-24 Freescale Semiconductor
Electrical Characteristics
CLKOUT A[0-17] AA[0-3]
D[0-23] D[0-23] Data Data
Note: Address lines A[0-17] hold their state after read write operation. AA[0-3] hold their state after read write operation.
Figure 2-21.
Synchronous Timings (BCR Controlled)
CLKOUT A[0-17] AA[0-3] D[0-23] D[0-23] Data Data
Note: Address lines A[0-17] hold their state after read write operation. AA[0-3] hold their state after read write operation.
Figure 2-22.
Synchronous Timings Controlled)
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-25
Specifications
2.5.5.4 Arbitration Timings
Table 2-14. Arbitration Timings1
Expression2 Unit
Notes: CLKOUT high assertion/deassertion3 asserted/deasserted CLKOUT high (setup) CLKOUT high deasserted/asserted (hold) deassertion CLKOUT high (input set-up) CLKOUT high assertion (input hold) CLKOUT high assertion (output) CLKOUT high deassertion (output) high high impedance (output) CLKOUT high address controls active CLKOUT high address controls high impedance CLKOUT high active CLKOUT high deassertion CLKOUT high high impedance 0.25 0.75 0.25 maximum: 0.25 0.75
Characteristics
Synchronous arbitration recommended. Asynchronous mode whenever possible. expression used compute maximum minimum value listed, appropriate. timing 223, minimum absolute value. T212 valid Address Trace mode when Operating Mode Register set. deasserted internal accesses asserted external accesses.
DSP56309 Technical Data, Rev. 2-26 Freescale Semiconductor
Electrical Characteristics
CLKOUT
A[0-17] AA[0-3] Note: Address lines A[0-17] hold their state after read write operation. AA[0-3] hold their state after read write operation.
Figure 2-23.
Acquisition Timings
CLKOUT
A[0-17] AA[0-3] Note: Address lines A[0-17] hold their state after read write operation. AA[0-3] hold their state after read write operation.
Figure 2-24.
Release Timings Case (BRT Operating Mode Register Cleared)
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-27
Specifications
CLKOUT
A[0-17] AA[0-3]
Note: Address lines A[0-17] hold their state after read write operation. AA[0-3] hold their state after read write operation.
Figure 2-25.
Release Timings Case (BRT Operating Mode Register Set)
DSP56309 Technical Data, Rev. 2-28 Freescale Semiconductor
Electrical Characteristics
2.5.5.5 Asynchronous Arbitration Timings
Table 2-15.
Notes:
Asynchronous Timings1,
Expression3
MHz4 Unit
Characteristics
assertion window from input deassertion5 Delay from assertion assertion5
Operating Mode Register must enter Asynchronous Arbitration mode. Asynchronous Arbitration mode active, none timings Table 2-14 required. expression used compute maximum minimum value listed, appropriate. Asynchronous Arbitration mode recommended operation MHz. order guarantee timings 250, 251, inputs must asserted different DSP56300 devices same non-overlap manner shown Figure 2-26.
250+251
Figure 2-26.
Asynchronous Arbitration Timing
asynchronous arbitration enabled internal synchronization circuits inputs. These synchronization circuits delay from external signal until exposed internal logic. result this delay, DSP56300 part assume mastership assert some time after deasserted. This reason timing 250. Once asserted, there synchronization delay from assertion time this assertion exposed other DSP56300 components that potential masters same bus. input asserted before that time, asserted deasserted, another DSP56300 component assume mastership same time. Therefore, some non-overlap period between input active another input active required. Timing ensures that overlaps avoided.
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-29
Specifications
2.5.6
Host Interface Timing
Table 2-16. Host Interface Timings1,2,12
Expression
19.9 31.6
Characteristic10
Read data strobe assertion width5 HACK assertion width Read data strobe deassertion width5 HACK deassertion width Read data strobe deassertion width5 after "Last Data Register" reads8,11, between consecutive CVR, ICR, reads3 HACK deassertion width after "Last Data Register" reads8,11 Write data strobe assertion width6 Write data strobe deassertion HACK write deassertion width after ICR, "Last Data Register" writes after writes, after TXH:TXM:TXL writes (with HLEND= after TXL:TXM:TXH writes (with HLEND width8
Unit
13.2
31.8 16.5
assertion width deassertion data strobe assertion
deassertion6
24.5 19.3
Host data input setup time before write data strobe Host data input hold time after write data strobe
deassertion6
Read data strobe assertion output data active from high impedance HACK assertion output data active from high impedance Read data strobe assertion output data valid5 HACK assertion output data valid Read data strobe deassertion output data high impedance5 HACK deassertion output data high impedance Output data hold time after read data strobe deassertion5 Output data hold time after HACK deassertion assertion read data strobe deassertion5 assertion write data strobe deassertion assertion output data valid hold time after data strobe deassertion4
19.9
Address (HAD[0-7]) setup time before deassertion (HMUX=1) Address (HAD[0-7]) hold time after deassertion (HMUX=1) HA[8-10] (HMUX=1), HA[0-2] (HMUX=0), HR/W setup time before data strobe assertion4 Read Write HA[8-10] (HMUX=1), HA[0-2] (HMUX=0), HR/W hold time after data strobe deassertion4 Delay from read data strobe deassertion host request assertion "Last Data Register" read5, Delay from write data strobe deassertion host request assertion "Last Data Register" write6,
15.3 20.3
DSP56309 Technical Data, Rev. 2-30 Freescale Semiconductor
Electrical Characteristics
Table 2-16.
Notes:
Host Interface Timings1,2,12 (Continued)
Expression
19.3 300.0
Characteristic10
Delay from data strobe assertion host request deassertion "Last Data Register" read write (HROD=0) Delay from data strobe assertion host request deassertion "Last Data Register" read write (HROD=1, open drain host request)4,
Unit
Programmer's Model section chapter HI08 DSP56309 User's Manual. timing diagrams below, controls pins drawn active low. polarity programmable. This timing applicable only consecutive reads from these registers executed. data strobe Host Read (HRD) Host Write (HWR) Dual Data Strobe mode Host Data Strobe (HDS) Single Data Strobe mode. read data strobe Dual Data Strobe mode Single Data Strobe mode. write data strobe Dual Data Strobe mode Single Data Strobe mode. host request HREQ Single Host Request mode HRRQ HTRQ Double Host Request mode. "Last Data Register" register address which last location read written data transfers. This RXL/TXL Endian mode (HLEND HLEND Interface Control Register 7-ICR[7]), RXH/TXH Little Endian mode (HLEND this calculation, host request signal pulled resistor Open-drain mode. -40°C +100 This timing applicable only read from "Last Data Register" followed read from RXL, RXM, registers without first polling RXDF HREQ bits, waiting assertion HREQ signal. After external host writes value ICR, HI08 ready operation after three clock cycles Tc).
HACK H[0-7] HREQ Note: read only MC680xx host processor non-multiplexed mode.
Figure 2-27.
Host Interrupt Vector Register (IVR) Read Timing Diagram
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-31
Specifications
HA[2-0] H[7-0] HREQ (single host request) HRRQ (double host request)
Figure 2-28.
Read Timing Diagram, Non-Multiplexed Bus, Single Data Strobe
HA[2-0]
H[7-0] HREQ (single host request) HRRQ (double host request)
Figure 2-29.
Read Timing Diagram, Non-Multiplexed Bus, Double Data Strobe
DSP56309 Technical Data, Rev. 2-32 Freescale Semiconductor
Electrical Characteristics
HA[2-0] H[7-0] HREQ (single host request) HTRQ (double host request)
Figure 2-30.
Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe
HA[2-0]
H[7-0] HREQ (single host request) HTRQ (double host request)
Figure 2-31.
Write Timing Diagram, Non-Multiplexed Bus, Double Data Strobe
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-33
Specifications
HA[10-8]
HAD[7-0] Address HREQ (single host request) HRRQ (double host request) Data
Figure 2-32.
Read Timing Diagram, Multiplexed Bus, Single Data Strobe
HA[10-8]
HAD[7-0] Address HREQ (single host request) HRRQ (double host request) Data
Figure 2-33.
Read Timing Diagram, Multiplexed Bus, Double Data Strobe
DSP56309 Technical Data, Rev. 2-34 Freescale Semiconductor
Electrical Characteristics
HA[10-8] HAD[7-0] Address Data HREQ (single host request) HTRQ (double host request)
Figure 2-34.
Write Timing Diagram, Multiplexed Bus, Single Data Strobe
HA[10-8]
HAD[7-0] Address Data HREQ (single host request) HTRQ (double host request)
Figure 2-35.
Write Timing Diagram, Multiplexed Bus, Double Data Strobe
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-35
Specifications
2.5.7
Timing
Table 2-17. Timings
Symbol
tSCC2
Notes:
Characteristics1
Synchronous clock cycle Clock period Clock high period Output data setup clock falling edge (internal clock) Output data hold after clock rising edge (internal clock) Input data setup time before clock rising edge (internal clock) Input data valid before clock rising edge (internal clock) Clock falling edge output data valid (external clock) Output data hold after clock rising edge (external clock) Input data setup time before clock rising edge (external clock) Input data hold time after clock rising edge (external clock) Asynchronous clock cycle Clock period Clock high period Output data setup clock rising edge (internal clock) Output data hold after clock rising edge (internal clock)
Expression
tSCC/2 10.0 tSCC/2 10.0 17.0 tSCC tSCC/4 -0.5 tSCC/4 25.0 tSCC/4 -5.5 53.3 16.7 16.7 15.0 50.0 18.0
Unit
19.5 32.0
tACC
tACC/2 10.0 tACC/2 10.0 tACC/2 30.0 tACC/2 30.0
640.0 310.0 310.0 290.0 290.0
40°C +100 tSCC synchronous clock cycle time (for internal clock, tSCC determined clock control register tACC asynchronous clock cycle time; value given Clock mode (for internal clock, tACC determined clock control register TC). expression used compute number listed minimum maximum value appropriate.
DSP56309 Technical Data, Rev. 2-36 Freescale Semiconductor
Electrical Characteristics
SCLK (Output) Data Valid Data Valid
Internal Clock
SCLK (Input) Data Valid Data Valid
External Clock Figure 2-36. Synchronous Mode Timing
SCLK (Output) Data Valid
Figure 2-37.
Asynchronous Mode Timing
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-37
Specifications
2.5.8
ESSI0/ESSI1 Timing
Table 2-18. ESSI Timings
Symbol
tSSICC
Clock cycle1
Characteristics4,
Expression9
10.0 -10.0
30.0 40.0 10.0 15.0 10.0 15.0 10.0 19.0 23.0 23.0 19.0
37.0 22.0 37.0 22.0 39.0 37.0 39.0 37.0 36.0 21.0 37.0 22.0 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0
Condition5
Unit
Clock high period internal clock external clock Clock period internal clock external clock rising edge (bit-length) high rising edge (bit-length) rising edge (word-length-relative) high2 rising edge (word-length-relative) rising edge (word-length) high rising edge (word-length) Data set-up time before (SCK Synchronous mode) falling edge Data hold time after falling edge input (bl, high before falling edge2 input (wl)6 high before falling edge input hold time after falling edge Flags input set-up before falling edge Flags input hold time after falling edge rising edge (bit-length) high rising edge (bit-length) rising edge (word-length-relative) high2 rising edge (word-length-relative) low2 rising edge (word-length) high rising edge (word-length) rising edge data enable from high impedance
DSP56309 Technical Data, Rev. 2-38 Freescale Semiconductor
Electrical Characteristics
Table 2-18.
Notes:
ESSI Timings (Continued)
Symbol Expression9
34.0 20.0 20.08 10.0 31.0 16.0 34.0 20.0 27.0 31.0 32.0 18.0
Characteristics4,
rising edge transmitter drive enable assertion rising edge data valid rising edge data high impedance3 rising edge transmitter drive enable deassertion3 input (bl, wr)6 set-up time before falling edge2 input (wl) data enable from high impedance input (wl) transmitter drive enable assertion input (wl) set-up time before falling edge input hold time after falling edge Flag output valid after rising edge
Condition5
Unit
21.0 21.0
internal clock, external clock cycle defined Icyc (see Timing ESSI Control Register. word-length-relative frame sync signal waveform operates same bit-length frame sync signal waveform, spreads from serial clock before first clock (same Length Frame Sync signal) until before last clock first word frame. Periodically sampled percent tested 40°C +100 (SCK Pin) transmit clock (SC0 Pin) receive clock (SC2 Pin) transmit frame sync (SC1 Pin) receive frame sync internal clock external clock internal clock, Asynchronous mode (asynchronous implies that different clocks) Internal Clock, Synchronous mode (synchronous implies that same clock) length; word length; word length relative. core writes transmit register during last cycle before causing underrun error, delay (0.5 TC). expression used compute number listed minimum maximum value appropriate.
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-39
Specifications
(Input/ Output) (Bit) (Word) Data Transmitter Drive Enable (Bit) (Word) Flags Note: Network mode, output flag transitions occur start each time slot within frame. Normal mode, output flag state asserted entire frame period. Note First Last
Figure 2-38.
ESSI Transmitter Timing
DSP56309 Technical Data, Rev. 2-40 Freescale Semiconductor
Electrical Characteristics
(Input/ Output) (Bit) (Word) Data (Bit) (Word) Flags First Last
Figure 2-39.
ESSI Receiver Timing
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-41
Specifications
2.5.9
Timer Timing
Table 2-19. Timer Timing1
Expression2
Unit
10.0 22.0 22.0
Characteristics
High Timer set-up time from (Input) assertion CLKOUT rising edge Synchronous timer delay time from CLKOUT rising edge external memory access address valid caused first interrupt instruction execution CLKOUT rising edge (Output) assertion Minimum Maximum CLKOUT rising edge (Output) deassertion Minimum Maximum
10.25
103.5
19.8 19.8
24.8 24.8
Notes:
40°C +100 expression used compute number listed minimum maximum value appropriate.
Figure 2-40.
Timer Event Input Restrictions
CLKOUT
(Input)
Address First Interrupt Instruction Execution
Figure 2-41.
Timer Interrupt Generation
CLKOUT (Output)
Figure 2-42.
External Pulse Generation
DSP56309 Technical Data, Rev. 2-42 Freescale Semiconductor
Electrical Characteristics
2.5.10 GPIO Timing
Table 2-20.
Note:
GPIO Timing
Expression
Minimum: 6.75 67.5
Characteristics
CLKOUT edge GPIO valid (GPIO delay time) CLKOUT edge GPIO valid (GPIO hold time) GPIO valid CLKOUT edge (GPIO set-up time) CLKOUT edge GPIO valid (GPIO hold time) Fetch CLKOUT edge before GPIO change 40°C +100
Unit
CLKOUT (Output) GPIO (Output) GPIO (Input) Valid
A[0-17] Fetch instruction MOVE X0,X:(R0); contains value GPIO contains address GPIO data register.
Figure 2-43.
GPIO Timing
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-43
Specifications
2.5.11 JTAG Timing
Table 2-21.
Notes:
JTAG Timing
frequencies Unit
22.0 40.0 40.0 44.0 44.0 45.0 20.0 24.0 25.0 100.0 40.0
Characteristics
frequency operation (1/(TC maximum MHz) cycle time Crystal mode clock pulse width measured rise fall times Boundary scan input data setup time Boundary scan input data hold time output data valid output high impedance TMS, data setup time TMS, data hold time data valid high impedance TRST assert time TRST setup time
-40°C +100 timings apply OnCE module data transfers because uses JTAG port interface.
(Input)
Figure 2-44.
Test Clock Input Timing Diagram
DSP56309 Technical Data, Rev. 2-44 Freescale Semiconductor
Electrical Characteristics
(Input)
Data Inputs Data Outputs Data Outputs Data Outputs
Input Data Valid
Output Data Valid
Output Data Valid
Figure 2-45.
Boundary Scan (JTAG) Timing Diagram
(Input) (Input)
Input Data Valid
(Output) (Output) (Output)
Output Data Valid
Output Data Valid
Figure 2-46.
(Input)
Test Access Port Timing Diagram
TRST (Input)
Figure 2-47.
TRST Timing Diagram
DSP56309 Technical Data, Rev. Freescale Semiconductor 2-45
Specifications
2.5.12 OnCE Module TimIng
Table 2-22.
Note:
OnCE Module Timing
Expression
22.0 10.0 30.0
Characteristics
frequency operation assertion time order enter Debug mode Response time when DSP56309 executing instructions from internal memory Debug acknowledge assertion time
20.0 25.0
22.0 67.0
Unit
-40°C +100
Figure 2-48.
OnCE-Debug Request
DSP56309 Technical Data, Rev. 2-46 Freescale Semiconductor
Packaging
This section includes diagrams DSP56309 package pin-outs tables showing signals described Chapter allocated each package. DSP56309 available package types: 144-pin Thin Quad Flat Pack (TQFP) 196-pin Molded Array Process-Ball Grid Array (MAP-BGA)
DSP56309 Technical Data, Rev. Freescale Semiconductor
Packaging
TQFP Package Description
bottom views TQFP package shown Figure Figure with their pin-outs.
GNDD VCCD GNDA VCCQH GNDQ GNDA VCCA GNDA VCCA GNDA VCCA
VCCD GNDD VCCD GNDD VCCQL GNDQ VCCD GNDD MODD MODC MODB MODA
TRST
(Top View)
SC12 SC11
Orientation Mark
GNDC VCCC BCLK BCLK CLKOUT GNDC VCCC VCCQL EXTAL GNDQ XTAL VCCQH GNDP1 GNDP PCAP VCCP RESET HAD0 HAD1 HAD2 HAD3 GNDH VCCH HAD4
Notes:
Because size constraints this figure, only name shown multiplexed pins. Refer Table Table detailed information about functions signal names.
Figure 3-1.
PINIT SRD0 VCCS GNDS STD0 SC10 SC00 SCLK SCK1 SCK0 VCCQL GNDQ VCCQH HACK HREQ VCCS GNDS TIO2 TIO1 TIO0 HAD7 HAD6 HAD5
SRD1 STD1 SC02 SC01
DSP56309 Thin Quad Flat Pack (TQFP), View
DSP56309 Technical Data, Rev. Freescale Semiconductor
TQFP Package Description
VCCA GNDA VCCA GNDA VCCA GNDA GNDQ VCCQL VCCQH GNDA VCCD GNDD
(Bottom View)
GNDC VCCC
BCLK
BCLK CLKOUT GNDC VCCC VCCQL EXTAL GNDQ XTAL
VCCQH GNDP1 GNDP PCAP VCCP
RESET
VCCD GNDD VCCD GNDD VCCQL GNDQ VCCD GNDD MODD MODC MODB MODA
TRST
HAD0 HAD1 HAD2 HAD3 GNDH VCCH HAD4
Orientation Mark side)
SC12 SC11
HAD5 HAD6 HAD7 TIO0 TIO1 TIO2 GNDS VCCS HREQ HACK VCCQH GNDQ VCCQL SCK0 SCK1 SCLK SC00 SC10 STD0 GNDS VCCS SRD0 PINIT
Notes:
Because size constraints this figure, only name shown multiplexed pins. Refer Table Table detailed information about functions signal names.
Figure 3-2.
DSP56309 Thin Quad Flat Pack (TQFP), Bottom View
DSP56309 Technical Data, Rev. Freescale Semiconductor
SC01 SC02 STD1 SRD1
Packaging
Table 3-1.
DSP56309 TQFP Signal Identification Number
GNDS TIO2 TIO1 TIO0 HCS/HCS, HA10, PB13 HA2, HA9, PB10 HA1, HA8, HA0, HAS/HAS, HAD7, HAD6, HAD5, HAD4, VCCH GNDH HAD3, HAD2, HAD1, HAD0, RESET VCCP PCAP GNDP GNDP1 VCCQH AA3/RAS3
Signal Name
SRD1 STD1 SC02 SC01 PINIT/NMI SRD0 VCCS GNDS STD0 SC10 SC00 SCLK SCK1 SCK0 VCCQL GNDQ VCCQH HDS/HDS, HWR/HWR, PB12 HRW, HRD/HRD, PB11 HACK/HACK, HRRQ/HRRQ, PB15 HREQ/HREQ, HTRQ/HTRQ, PB14 VCCS
Signal Name
AA2/RAS2 XTAL GNDQ EXTAL VCCQL VCCC GNDC CLKOUT BCLK BCLK VCCC GNDC AA1/RAS1 AA0/RAS0 VCCA GNDA
Signal Name
DSP56309 Technical Data, Rev. Freescale Semiconductor
TQFP Package Description
Table 3-1.
Notes: VCCA GNDA VCCA GNDA GNDQ VCCQL VCCQH GNDA
DSP56309 TQFP Signal Identification Number (Continued)
VCCD GNDD VCCD GNDD VCCD GNDD
Signal Name
Signal Name
VCCQL GNDQ VCCD GNDD
Signal Name
MODD/IRQD MODC/IRQC MODB/IRQB MODA/IRQA TRST SC12 SC11
Signal names based configured functionality. Most pins supply single signal. Some pins provide signal with dual functionality, such MODx/IRQx pins that select operating mode after RESET deasserted interrupt lines during operation. Some signals have configurable polarity; these names shown with without overbars, such HAS/HAS. Some pins have more configurable functions; names assigned these pins indicate function specific configuration. example, data line non-multiplexed mode, data/address line HAD7 multiplexed mode, GPIO line when GPIO function enabled this pin.
DSP56309 Technical Data, Rev. Freescale Semiconductor
Packaging
Table 3-2.
Signal Name
BCLK BCLK
DSP56309 TQFP Signal Identification Name
Signal Name
CLKOUT
Signal Name
EXTAL GNDA GNDA GNDA GNDA GNDC GNDC GNDD GNDD GNDD GNDD GNDH GNDP GNDP1 GNDQ GNDQ GNDQ GNDQ GNDS GNDS
DSP56309 Technical Data, Rev. Freescale Semiconductor
TQFP Package Description
Table 3-2.
Signal Name
HA10 HACK/HACK HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAS/HAS HCS/HCS HDS/HDS
DSP56309 TQFP Signal Identification Name (Continued)
Signal Name
HRD/HRD HREQ/HREQ HRRQ/HRRQ HTRQ/HTRQ HWR/HWR IRQA IRQB IRQC IRQD MODA MODB MODC MODD PB10 PB11 PB12 PB13 PB14 PB15
Signal Name
PCAP PINIT RAS0 RAS1
DSP56309 Technical Data, Rev. Freescale Semiconductor
Packaging
Table 3-2.
Signal Name
RAS2 RAS3 RESET SC00 SC01 SC02 SC10 SC11 SC12 SCK0 SCK1 SCLK SRD0 SRD1 STD0
DSP56309 TQFP Signal Identification Name (Continued)
Signal Name
STD1 TIO0 TIO1 TIO2 TRST VCCA VCCA VCCA VCCC VCCC VCCD
Signal Name
VCCD VCCD VCCD VCCH VCCP VCCQH VCCQH VCCQH VCCQL VCCQL VCCQL VCCQL VCCS VCCS XTAL
DSP56309 Technical Data, Rev. Freescale Semiconductor
TQFP Package Mechanical Drawing
TQFP Package Mechanical Drawing
0.20
TIPS
0.20
ident
140X
X=L,
View
View
View
144X
Notes: Dimensions tolerancing ASME Y14.5, 1994. Dimensions millimeters. Datums determined seating plane, datum Dimensions determined seating plane, datum Dimensions include mold protrusion. Allowable protrusion 0.25 side. Dimensions include mold mismatch determined datum plane Dimension does include dambar protrusion. Allowable dambar protrusion shall cause dimension exceed 0.35. Millimeters 20.00 10.00 20.00 10.00 1.40 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.45 0.75 0.17 0.23 0.50 0.09 0.20 0.50 0.25 0.13 0.20 0.13 0.20 22.00 11.00 22.00 11.00 0.25 1.00 0.09 0.16
Seating plane
Plating
0.05
0.08
Base metal
0.25
Gage plane
View
Section J1-J1
(rotated
CASE 918-03 ISSUE Figure 3-3. DSP56309 Mechanical Information, 144-pin TQFP Package
DSP56309 Technical Data, Rev. Freescale Semiconductor
Packaging
MAP-BGA Package Description
bottom views MAP-BGA package shown Figure Figure with their pin-outs.
View
SC11 MODB VCCD
SRD1
SC12
TRST
MODD
SC02
STD1
MODA MODC
VCCQL
VCCD
VCCD
PINIT
SC01
VCCD
STD0
VCCS
SRD0
SC10
SC00
VCCQH
SCK1
SCLK
VCCQL
VCCQH VCCQL
SCK0
VCCA
HACK
VCCS
HREQ
TIO2
VCCA
TIO1
TIO0
VCCA
VCCH
VCCP
VCCQH EXTAL
BCLK
RESET GNDP
VCCQL
BCLK
VCCC
PCAP GNDP1
XTAL
VCCC
Figure 3-4.
DSP56309 Molded Array Process-Ball Grid Array (MAP-BGA), View
DSP56309 Technical Data, Rev. 3-10 Freescale Semiconductor
MAP-BGA Package Description
Bottom View
VCCD MODB SC11
MODD
TRST
SC12
SRD1
VCCD
VCCD
VCCQL
MODC MODA
STD1
SC02
VCCD
SC01
PINIT
SRD0
VCCS
STD0
VCCQH
SC00
SC10
VCCQL
SCLK
SCK1
VCCA
SCK0
VCCQL VCCQH
HACK
VCCA
TIO2
HREQ
VCCS
VCCA
TIO0
TIO1
BCLK
EXTAL VCCQH
VCCP
VCCH
VCCC
BCLK
VCCQL
GNDP
RESET
VCCC
XTAL
GNDP1 PCAP
Figure 3-5.
DSP56309 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View
DSP56309 Technical Data, Rev. Freescale Semiconductor 3-11
Packaging
Table 3-3.
DSP56309 MAP-BGA Signal Identification Number
Signal Name
Connected (NC), reserved SC11 MODB/IRQB VCCD SRD1 SC12 TRST MODD/IRQD
Signal Name
SC02 STD1 MODA/IRQA MODC/IRQC VCCQL VCCD VCCD PINIT/NMI SC01
Signal Name
VCCD STD0 VCCS SRD0 SC10 SC00
DSP56309 Technical Data, Rev. 3-12 Freescale Semiconductor
MAP-BGA Package Description
Table 3-3.
DSP56309 MAP-BGA Signal Identification Number
(Continued)
Signal Name
VCCS HREQ/HREQ, HTRQ/HTRQ, PB14 TIO2 VCCA
Signal Name
Signal Name
SCK0
VCCQH SCK1 SCLK
VCCA HACK/HACK, HRRQ/HRRQ, PB15 HRW, HRD/HRD, PB11 HDS/HDS, HWR/HWR, PB12 HAD6, HAD7,
VCCQL VCCQH VCCQL VCCA
HCS/HCS, HA10, PB13 TIO1 TIO0 HAD5, HAD3, HAD1,
DSP56309 Technical Data, Rev. Freescale Semiconductor 3-13
Packaging
Table 3-3.
Notes:
DSP56309 MAP-BGA Signal Identification Number
(Continued)
Signal Name
PCAP AA2/RAS2 XTAL VCCC AA1/RAS1
Signal Name
HA1, HA8, HA2, HA9, PB10 HA0, HAS/HAS, VCCH HAD0, VCCP VCCQH EXTAL CLKOUT BCLK
Signal Name
HAD4, HAD2, RESET GNDP AA3/RAS3 VCCQL BCLK VCCC AA0/RAS0
Signal names based configured functionality. Most connections supply single signal. Some connections provide signal with dual functionality, such MODx/IRQx pins that select operating mode after RESET deasserted interrupt lines during operation. Some signals have configurable polarity; these names shown with without overbars, such HAS/HAS. Some connections have more configurable functions; names assigned these connections indicate function specific configuration. example, connection data line non-multiplexed mode, data/address line HAD7 multiplexed mode, GPIO line when GPIO function enabled this pin. Unlike TQFP package, most pins connected internally center connection array heat sink chip. Therefore, except GNDP that support PLL, other signals support individual subsystems chip.
DSP56309 Technical Data, Rev. 3-14 Freescale Semiconductor
MAP-BGA Package Description
Table 3-4.
Signal Name
BCLK BCLK
DSP56309 MAP-BGA Signal Identification Name
Signal Name
CLKOUT
Signal Name
EXTAL
DSP56309 Technical Data, Rev. Freescale Semiconductor 3-15
Packaging
Table 3-4.
Signal Name
DSP56309 MAP-BGA Signal Identification Name (Continued)
Signal Name
GNDP
Signal Name
HA10 HACK/HACK HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAS/HAS HCS/HCS HDS/HDS HRD/HRD HREQ/HREQ HRRQ/HRRQ
DSP56309 Technical Data, Rev. 3-16 Freescale Semiconductor
MAP-BGA Package Description
Table 3-4.
Signal Name
HTRQ/HTRQ HWR/HWR IRQA IRQB IRQC IRQD MODA MODB MODC MODD PB10 PB11 PB12 PB13 PB14 PB15
DSP56309 MAP-BGA Signal Identification Name (Continued)
Signal Name
PCAP PINIT
Signal Name
RAS0 RAS1 RAS2 RAS3 RESET SC00 SC01 SC02 SC10 SC11 SC12 SCK0 SCK1 SCLK SRD0 SRD1 STD0 STD1 TIO0
DSP56309 Technical Data, Rev. Freescale Semiconductor 3-17
Packaging
Table 3-4.
Signal Name
TIO1 TIO2 TRST VCCA VCCA VCCA VCCC
DSP56309 MAP-BGA Signal Identification Name (Continued)
Signal Name
VCCC VCCD VCCD VCCD VCCD VCCH VCCP VCCQH VCCQH
Signal Name
VCCQH VCCQL VCCQL VCCQL VCCQL VCCS VCCS XTAL
MAP-BGA Package Mechanical Drawing
Figure 3-6.
DSP56309 Mechanical Information, 196-pin MAP-BGA Package
DSP56309 Technical Data, Rev.
3-18
Freescale Semiconductor
Design Considerations
Thermal Design Considerations
estimate chip junction temperature, obtained from this equation: Equation Where:
ambient temperature package junction-to-ambient thermal resistance °C/W power dissipation package
This section describes various areas consider when incorporating DSP56309 device into system design.
Historically, thermal resistance been expressed junction-to-case thermal resistance caseto-ambient thermal resistance, this equation: Equation Where:
package junction-to-ambient thermal resistance °C/W package junction-to-case thermal resistance °C/W package case-to-ambient thermal resistance °C/W
device-related cannot influenced user. user controls thermal environment change case-to-ambient thermal resistance, RCA. example, user change flow around device, heat sink, change mounting arrangement printed circuit board (PCB) otherwise change thermal dissipation capability area surrounding device PCB. This model most useful ceramic packages with heat sinks; some percent heat flow dissipated through case heat sink ambient environment. ceramic packages, situations where heat flow split between path case alternate path through PCB, analysis device thermal performance need additional modeling capability system-level thermal simulation tool. thermal performance plastic packages more dependent temperature which package mounted. Again, estimates obtained from satisfactorily answer whether thermal performance adequate, system-level model appropriate. complicating factor existence three common ways determine junction-to-case thermal resistance plastic packages. minimize temperature variation across surface, thermal resistance measured from junction outside surface package (case) closest chip mounting area when that surface proper heat sink.
DSP56309 Technical Data, Rev. Freescale Semiconductor
Design Considerations
define value approximately equal junction-to-board thermal resistance, thermal resistance measured from junction point which leads attach case. temperature package case (TT) determined thermocouple, thermal resistance computed from value obtained equation TT)/PD.
noted earlier, junction-to-case thermal resistances quoted this data sheet determined using first definition. From practical standpoint, that value also suitable determine junction temperature from case thermocouple reading forced convection environments. natural convection, junction-to-case thermal resistance estimate junction temperature from thermocouple reading case package will yield estimate junction temperature slightly higher than actual temperature. Hence, thermal metric, thermal characterization parameter been defined TT)/PD. This value gives better estimate junction temperature natural convection when surface temperature package used. Remember that surface temperature readings packages subject significant errors caused inadequate attachment sensor surface errors caused heat loss sensor. recommended technique attach 40-gauge thermocouple wire bead center package with thermally conductive epoxy.
Electrical Design Considerations
CAUTION
This device contains protective circuitry guard against damage high static voltage electrical fields. However, normal precautions advised avoid application voltages higher than maximum rated voltages this high-impedance circuit. Reliability operation enhanced unused inputs tied appropriate logic voltage level (for example, either VCC).
following list recommendations ensure correct operation. Provide low-impedance path from board power supply each from board ground each pin. least 0.01-0.1 bypass capacitors positioned close possible four sides package connect power source GND. Ensure that capacitor leads associated printed circuit traces that connect chip pins less than inch capacitor lead. least four-layer with inner layers GND. Because output signals have fast rise fall times, trace lengths should minimal. This recommendation particularly applies address data buses well IRQA, IRQB, IRQC, IRQD, pins. Maximum trace lengths order inches recommended.
DSP56309 Technical Data, Rev. Freescale Semiconductor
Power Consumption Considerations
Consider device loads well parasitic capacitance traces when calculate capacitance. This especially critical systems with higher capacitive loads that could create higher transient currents circuits. inputs must terminated (that allowed float) CMOS levels except three pins with internal pull-up resistors (TRST, TMS, DE). Take special care minimize noise levels VCCP, GNDP, GNDP1 pins. following pins must asserted after power-up: RESET TRST. multiple devices same board, check cross-talk excessive spikes supplies synchronous operation devices.
RESET
must asserted when chip powered stable EXTAL signal should supplied before deassertion RESET.
power-up, ensure that voltage difference between tolerant pins chip never exceeds
Power Consumption Considerations
Power dissipation issue portable applications. Some factors affecting current consumption described this section. Most current consumed CMOS devices alternating current (ac), which charging discharging capacitances pins internal nodes. Current consumption described this formula: Equation Where:
node/pin capacitance voltage swing frequency node/pin toggle Example 4-1. Current Consumption
Port address loaded with capacitance, operating with clock, toggling maximum possible rate MHz), current consumption expressed Equation
Equation 5.48 maximum internal current (ICCImax) value reflects typical possible switching internal buses bestcase operation conditions-not necessarily real application case. typical internal current (ICCItyp) value reflects average switching internal buses typical operating conditions. Perform following steps appl
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