8-bit Microcontroller Version 1.01 Acer Laboratories Inc.
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M6759
8-bit Microcontroller
Version 1.01
Acer Laboratories Inc.
M6759: Micro-controller
-Proprietary, Confidential, Preliminary-
M6759 8-bit Micro-controller
Section Features
8051 instruction compatible 8-bit microcontroller 8051/8052 compatible pinout Complete static design, wide range operation frequency from Large on-chip memory bytes built-in Multiple Times Programmable (MTP-ROM) program memory bytes on-chip SRAM, expandable external bytes address space Dual Data Pointer Four 8-bit bi-directional ports interrupts including external sources full-duplex serial UART ports compatible with standard 8052 Three timer/counters chip oscillator crystal Software Power-Down mode, supports Idle mode Power Down mode less power consumption Code Protection 4.5V~5.5V operation voltage, programming voltage 44-pin PLCC package
General Description M6759 8032/8052 instruction compatible 8-bit microcontroller with Flash firmware updating. combining versatile 8-bit with MTP-Flash, this device provides whole microcontroller system chip still remains feasibility general control systems variety applications. Furthermore, user-defined security registers protect firmware after code ready. M6759 contains following: non-volatile bytes Multiple Times Programmable program memory. volatile bytes read/write data memory four 8-bit ports, 16-bit timer/event counters (identical timers 80C51). 16-bit timer (identical Timer 8052). multi-source two-priority-level nested interrupt structure. serial interface (UART) on-chip oscillator.
Ver. 1.01, Document Number 6759DS02.doc Acer Labs: 11F, Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage www.ali.com.tw
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M6759: Micro-controller
Table Contents: Section Features General Description. Block Diagram. Section Description Section Function Description Data Space Addressing Dual Data Pointer Mode Idle Mode PowerDown Mode Reset Interrupt Processing Interrupt Masking Interrupt Priorities. Section Special Function Registers Control Status Register.13 Peripheral Device Registers.15 Section Peripheral Device Timer Operation Serial Interface Section Electrical Specifications Absolute Maximum Ratings D.C. Characteristics Characteristics.22 External Program Memory Read Cycle External Data Memory Read Cycle External Data Memory Write Cycle Shift Register Mode Timing Diagram Section Flash Programming Guide.26 Description Section Packaging Information.29 Worldwide Distributors Sales Offices:
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Ver.1.01, Doc. No.: 6759DS02.doc Acer Labs: 11F, no.45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage: www.ali.com.tw
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M6759: Micro-controller
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Block Diagram P0.7:0 P2.7:0 P1.7:0 P3.7:0
Port Drivers
Port Drivers
Port Drivers Serial Port Timer Interrupt Logic
Port Drivers
Port Latch
Port Latch
Port Latch
Data REG1 Data
Data Register REG2 Stack Pointer
Program Address Register
bytes Memory
Program Counter Incrementer Buffer DPTR Bytes
Data
Addr. Register
Instruction Register
Clocks Control
Ver. 1.01, Document Number 6759DS02.doc Acer Labs: 11F, Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage www.ali.com.tw
XTAL2 XTAL1
/EAVPP /PSEN
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M6759: Micro-controller
Section Description
Pinout Diagram 2.1.1 44-pin PLCC Package
T2EX
/INT0 /INT1
M6759
/EAVPP /PSEN
P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5
P1.4 P1.3 P1.2 P1.1 P1.0 P0.0 P0.1 P0.2 P0.3
M6759
P0.4 P0.5 P0.6 P0.7 /EAVPP /PSEN P2.7 P2.6 P2.5
2.1.2 44-pin Package
XTAL2 XTAL1
T2EX
/INT0 /INT1
M6759
/EAVPP /PSEN
P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5
P1.4 P1.3 P1.2 P1.1 P1.0 P0.0 P0.1 P0.2 P0.3
P3.6 P3.7 XTAL2 XTAL1 P2.0 P2.1 P2.2 P2.3 P2.4
P0.4 P0.5 P0.6 P0.7 /EAVPP /PSEN P2.7 P2.6 P2.5
M6759
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Ver.1.01, Doc. No.: 6759DS02.doc Acer Labs: 11F, no.45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage: www.ali.com.tw
XTAL2 XTAL1
P3.6 P3.7 XTAL2 XTAL1 P2.0 P2.1 P2.2 P2.3 P2.4
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M6759: Micro-controller
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Description Table:
assignments shown below listed based 44-pin PLCC package. additionally specified, further number reference throughout this datasheet default, referred 44-pin PLCC package. package, number assignment should shifted accordingly, comparatively shown Section Pinout Diagram.
Name (PLCC) Type P0.7-P0.0 36,37,38,39, 40,41,42, AD7-0 Description Power supply internal operation, input. Ground. Port bits bi-directional port with internal pull high. Multiplexed address/data bus. During time when high, memory address presented. When falls, port transitions bidirectional data bus. This used read external read/write external memory peripherals. Reset signal internal circuit, must kept clocks ensure being recognized internal circuit. This signal will affect internal SRAM. Crystal used external clock input. Crystal out, feedback XTAL1. Program Store Enable Output, commonly connected external memory chip enable during fetching MOVC operation. /PSEN goes high during reset condition. Address Latch Enable, used latch external address from multiplexed address/data bus, commonly connect latch enable family. This signal will forced high when device reset condition. Port bits bi-directional port with internal pull high. pins have alternate function shown below. External timer/counter trigger. External timer/counter Port bits bi-directional port with internal pull high. alternate function address This emits high-order address byte during fetches from external Program Memory during accesses external Data Memory that 16-bit addresses (MOVX DPTR). During accesses external Data Memory that 8-bit addresses (MOVX Ri), Port emits contents Special Function Register. Port 8-bit bi-directional port with internal pull high. reset condition this port with bits logic Port also have alternate function list below External data memory read strobe. External data memory write strobe. External timer/counter External timer/counter External interrupt (Negative Edge Detect). External interrupt (Negative Edge Detect). Serial port output. Serial port input. must externally held enable device fetch code from external program memory. /EAVPP held high, device executes from internal program memory. /EAVPP internal latched reset. This also receives programming voltage (VPP) during FLASH programming. These pins should connected purpose
XTAL1 XTAL2 /PSEN
P1.7-P1.0
9,8,7,6,5,4,3 T2EX (P1.1) (P1.0) P2.7-P2.0 31,30,29,28, 27,26,25, A15-A8
P3.7-P3.0
19,18,17,16, 15,14,13,
(P3.7) (P3.6) (P3.5) (P3.4) /INT1 (P3.3) /INT0 (P3.2) (P3.1) (P3.0) /EAVPP
1,12,23,34
Ver. 1.01, Document Number 6759DS02.doc Acer Labs: 11F, Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage www.ali.com.tw
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M6759: Micro-controller
Section Function Description
Data Space Addressing M6759 internal data memory that mapped into four separate segments: lower bytes RAM, upper bytes RAM, bytes Special Function Register (SFR), bytes auxiliary (ARAM). four segments are: Lower bytes (address 7FH) directly indirectly addressable. Upper bytes (address FFH) indirectly addressable only. Special Function Registers SFRs, (address FFH) directly addressable only. 256-bytes auxiliary (ARAM, 0000H-00FFH) indirectly accessed move external instruction, MOVX. Either direct indirect addressing access lower bytes. upper bytes accessed indirect address only. upper bytes occupy same address space SFRs. That means they have same address, physically separate from space. ARAM accessed indirect addressing MOVX instructions when ARAM_EN set. This part memory physically located on-chip, logically occupied first 256-bytes external data memory ARAM_EN set. ARAM indirectly addressed, using MOVX instruction combination with registers selected bank DPTR. access ARAM will affect ports P3.6 (/WR) P3.7 (/RD). ARAM_EN cleared, access external memory will performed same standard 8051. ARAM_EN DPTR contains value lower than 0100H, ARAM will accessed rather than external memory, DPTR contains value higher than 00FFH (i.e. 0100H FFFFH), external memory will accessed. ARAM_EN contains 00H, ARAM will accessed MOVX @Ri, #data instruction, contains non-zero value, external memory will accessed using MOVX @Ri, #data. example, MOVX DPTR, #data ARAM_EN DPTR contains 0030H, access ARAM address 030H rather than external memory. ARAM_EN DPTR contains 0130H, external memory address 0130H will accessed example: MOVX @R0, #data ARAM_EN set, contains 00H, contains 30H, access ARAM address will performed. ARAM_EN set, contains 01H, contains 30H, access external memory address 0130H will performed connected high byte address external RAM. Dual Data Pointer Data memory block moves accelerated using Dual Data Pointer (DPTR). standard 8051 DPTR 16-bit value that used address off-chip data peripherals. M6759, standard 16-bit data pointer called DPTR0 located address 83H. These standard locations. DPTR located called DPTR1. DPTR Select (DPS) chooses active pointer located location 86H. other bits register have effect user switches between data pointer toggling register 86H. increment (INC) instruction fastest accomplish this. DPTR-related instructions currently selected DPTR activity. Mode normal operation emitted constant rate oscillator frequency, used external timing clocking purpose. Note, however, that pulse skipped during each access external Data Memory. desired, setting location disable operation. With set, active only during MOVX instruction. Otherwise weakly pulled high. Setting ALE-disable effect micro-controller external execution mode.
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Memory
Program Space
/EAVPP=0V FFFFh FFFFh
/EAVPP=5V
External
Internal Flash
0000h
0000h
Data Space
ARAM_EN=1 FFFFh
External
Internal Upper bytes
space
0100h 00FFh 0000h 00FFh 0000h
Lower bytes
External
ARAM_EN=0
Internal
ARAM_EN=1
Ver. 1.01, Document Number 6759DS02.doc Acer Labs: 11F, Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage www.ali.com.tw
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M6759: Micro-controller
Idle Mode Idle mode, itself into sleep while on-chip peripherals remain active. instruction that sets PCON.0 last instruction executed normal operating mode before Idle mode activated. content special functions register remain unchanged, status (includes Stack Point, Program Counter, Program Status Word Accumulator) preserved this mode. There ways terminate Idle mode: Activation enabled interrupt will cause IDLE (PCON.0) cleared hardware terminating Idle mode. interrupt will serviced, returned instruction RETI. next instruction executed which follows instruction that wrote logic PCON.0. flag bits (PCON.2) (PCON.6) used determine whether interrupt received during normal execution during Idle mode. When Idle mode terminated interrupt, service routine examine status flag bits. second terminating Idle mode with external hardware reset.
external reset signal synchronous internal clock. port pins will maintain high internal pullups oscillator periods after goes low. While high, /PSEN weakly pulled high. After pulled low, will take about oscillator periods PSEN start clocking. this reason, other devices synchronized internal timings m6759. Driving /PSEN pins while reset active could cause device into indeterminate state. internal reset algorithm writes SFRs except port latches, Stack Pointer, SBUF. port latches initialized FFH, Stack Pointer 07H, SBUF indeterminate. internal affected reset. power content indeterminate. Interrupt Processing When enabled interrupt occurs, vectors address interrupt service routine (ISR) associated with that interrupt, listed Table executes completion unless another interrupt higher priority occurs. Each ends with RETI (return from interrupt) instruction. After executing RETI, returns next instruction that would have been executed interrupt occurred. only interrupted higher priority interrupt. That low-priority level interrupt only interrupted high-priority level interrupt. high-priority level cannot interrupted other interrupt. M6759 always completes instruction progress before servicing interrupt. instruction progress RETI, write access SFRs, M6759 completes additional instruction before servicing interrupt. Interrupt Masking (IE.7) global enable interrupts. When EA=1, each interrupt enabled/masked individual enable bit. When EA=0, interrupts masked.
PowerDown Mode Setting PCON.1 (PD) force enter Power Down mode. this mode, on-chip oscillator stopped save most power. functions stopped clock frozen, contents special functions register held. terminate Power Down mode, only hardware reset. Reset redefines SFRs does change on-chip RAM. reset should activated before restored normal operating level must held active long enough allow oscillator restart stably. Reset reset input, which input Schmitt Trigger. reset accomplished holding high least four oscillator periods while oscillator running. responds generating internal reset, with timing shown Reset Timing.
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Interrupt Priorities There stages interrupt priority assignment, interrupt level natural priority. interrupt level (high low) takes precedence over natural priority. interrupts assigned high priority. addition assigned priority level, each interrupt also natural priority, listed Table 3-2. Simultaneous Mode Idle Idle Power Down Power Down
interrupts with same priority level (for example, both high) resolved according their natural priority. example, /INT0 /INT1 both programmed high priority, /INT0 takes precedence. Once interrupt being serviced, only interrupt higher priority level interrupt service routine interrupt currently being serviced.
Program Memory /PSEN Port0 Port1 Port2 Internal Data Data Data External Float Data Address Internal Data Data Data External Float Data Data Table 3-1. Status External pins During Idle Power Down
Port3 Data Data Data Data
Reset Timing
clocks State3 State4 State5 State6 State1 State2 State3 State4 State5
XTAL1 INTERNAL RESET SIGNAL
/PSEN
ADDR clocks
INST
ADDR
INST
STATE
STATE
STATE
STATE
STATE
STATE
STATE
STATE3 STATE4 STATE5
XTAL1 INTERNAL RESET SIGNAL
/PSEN
ADDR INST ADDR
Ver. 1.01, Document Number 6759DS02.doc Acer Labs: 11F, Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage www.ali.com.tw
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Table 3-2. Interrupt Natural Vectors Priorities Interrupt /INT1 Description External interrupt Timer interrupt Timer interrupt Serial Port transmit receive interrupt Natural Priority Interrupt Vector
Interrupt /INT1
Description External interrupt External interrupt Timer interrupt
Enable TCON.1 TCON.5 TCON.7 SCON0.0 SCON0.1 T2CON.7 IE.1 IE.2
Priority Control IP.0 IP.2 IP.3 IP.5
IE.6
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Section Special Function Registers
Register Register DPL0 DPH0 DPL1 DPH1 PCON TCON TMOD LEMI AUXR SCON SBUF T2CON RCAP2L RCAP2H Addr IDLE LOWEMI *INT2E CP/RL2
SMOD GATE
GATE
STOP
*BRG1
*BRG0
*INT2I
ARAM_E
*EX2 *PX2 EXF2
RCLK
TCLK
EXEN2
C/T2
registers labeled with only used 68-pin package (not available now)
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Register Initial Value DPL0 DPH0 DPL1 DPH1 PCON TCON TMOD LEMI AUXR SCON SBUF T2CON RCAP2L RCAP2H
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Register Definition
Register, Data Pointer Select Register SEL. DPTR Select bit. When SEL=0, DPTR0 active pointer. When SEL=1, DPTR1 active pointer. PCON Register, Power Control Register Description SMOD, Double Baud Rate bit. Timer used generate baud rate SMOD=1, baud rate doubled when Serial Port used modes GF3- General Purpose Flag bit. Power Down bit. IDLE, Idle Mode bit. LEMI Register, Control Register Description LOWEMI, Setting bit. M6759 operate internal access mode, active only during MOVX instruction when LOWEMI=1. AUXR Register, Auxiliary Register Description ARAM_EN, Access Internal Auxiliary Enable bit. When ARMA_EN=0, access external will performed MOVX. When ARAM_EN=1, access internal auxiliary rather than external RAM. GF6-GF5. General Purpose Flag bit. Reserved. Register, Program Control Register Description Carry Flag. when last arithmetic operation results carry into (during addition) borrow from (during subtraction) high order nibble. Otherwise, this cleared arithmetic operations. Auxiliary Carry Flag. when last arithmetic operation results carry into (during addition) borrow from (during subtraction) high order nibble. Otherwise, this cleared arithmetic operations. User Flag user addressable. Generates purpose flag software control. RS1-0, Register Bank Select Bank Selected Register Bank address 00h-07h Register Bank address 08h-0Fh Register Bank address 10h-17h Register Bank address 17h-1Fh Overflow Flag. when last arithmetic operation resulted carry (addition), borrow (subtraction), overflow (multiply divide). Otherwise, this cleared arithmetic operations. User Flag user addressable. Generator purpose flag software control. Parity Flag. when modulo-2 bits accumulator (odd parity), clear even parity.
Ver. 1.01, Document Number 6759DS02.doc Acer Labs: 11F, Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768Homepage www.ali.com.tw
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M6759: Micro-controller
Register Global Interrupt Enable. Controls masking interrupts except power fail interrupt. EA=0 disable interrupts overrides individual interrupt enable bits). When EA=1, each interrupt enabled masked individual enable bit. Reserved. ET2, Enable External Timer ET2=0 disables Timer interrupt (TF2). ET2=1 enables interrupts generated flag. ES0, Enable Serial Port Interrupt. ES0=0 disables Serial Port interrupts (TI_0 RI_0). ES0=1 enables interrupts generated TI_0 RI_0 flag. ET1, Enable External Timer ET1=0 disables Timer interrupt (TF1). ET1=1 enables interrupts generated flag. EX1, Enable External Interrupt EX1=0 disables external interrupt (/INT1). EX1=1 enables interrupts generated /INT1. ET0, Enable External Timer ET0=0 disables Timer interrupt (TF0). ET0=1 enables interrupts generated flag. EX0, Enable External Interrupt EX0=0 disables external interrupt (/INT0). EX0=1 enables interrupts generated /INT0. Register Description Reserved, read Reserved. PT2, Timer Interrupt Priority Control. PT2=0 sets Timer interrupt (TF2) priority. PT2=1 sets Timer interrupt high priority. PS0, Serial Port Interrupt Priority Control. PS0=0 sets Serial Port interrupts (TI_0 RI_0) priority. PS0=1 sets Serial Port high priority. PT1, Timer Interrupt Priority Control. PT1=0 sets Timer interrupt (TF1) priority. PT1=1 sets Timer interrupt high priority. PX1, External Interrupt Priority Control. PX1=0 sets external interrupt (/INT1) priority. PX1=1 sets external interrupt high priority. PT0, Timer Interrupt Priority Control. PT0=0 sets Timer interrupt (TF0) priority. PT0=1 sets Timer interrupt high priority. PX0, External Interrupt Priority Control. PX0=0 sets external interrupt (/INT0) priority. PX0=1 sets external interrupt high priority.
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Peripheral Device Registers Description TF1, Timer Overflow Flag. when Time count overflows clears when processor vectors interrupt service routine. TR1, Timer Control. enable counting Timer TF0, Timer Overflow Flag. when Time count overflows clears when processor vectors interrupt service routine. TR0, Timer Control. enable counting Timer IE1, Interrupt Edge Detect. external interrupt configured edge sensitive (IT1=1), hardware when negative edge detected /INT1 automatically cleared when vectors corresponding interrupt service routine. this case, also cleared software. external interrupt configured level-sensitive (IT1=0), when /INT1 cleared when /INT1 level-sensitive mode, software write IE1. IT1, Interrupt Type Selector, /INT1 detected falling edge when IT1=1; /INT1 detected level when IT1=0. IE0, Interrupt Edge Detect. external interrupt configured edge sensitive (IT0=1), hardware when negative edge detected /INT0 automatically cleared when vectors corresponding interrupt service routine. this case, also cleared software. external interrupt configured level-sensitive (IT0=0), when /INT0 cleared when /INT0 level-sensitive mode, software write IE0. IT0, Interrupt Type Selector, /INT0 detected falling edge when IT0=1; /INT0 detected level when IT0=0.
TMOD Register Description GATE. Timer Gate Control, when GATE=1, Timer will clock when /INT1 (TCON.6)= When GATE=0, Timer will clock only when TR1=1, regardless state /INT1 C/T, Counter/Timer Selector, when C/T=0, Timer clocked clk/12, depending state (CKCON.4). When C/T=1, Timer clocked pin. M1-0, Timer mode select bits Mode Mode counter Mode counter Mode counter with auto-reload Mode GATE. Timer Gate Control, when GATE=1, Timer will clock when /INT0 (TCON.4)= When GATE=0, Timer will clock only when TR0=1, regardless state /INT0. C/T, Counter/Timer Selector, when C/T=0, Timer clocked clk/12, depending state (CKCON.3). When C/T=1, Timer clocked pin. M1-0, Timer mode select bits Mode Mode counter Mode counter Mode counter with auto-reload Mode counter
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M6759: Micro-controller
Description TF2, Timer Overflow Flag. Hardware will when Timer overflow from FFFFH, must cleared software. will only RCLK TCLK both cleared Writing forces Timer interrupt enabled. EXF2, Timer External Flag. Hardware will EXF2 when reload capture caused high-to-low transition T2EX pin, EXEN2 set. EXF2 must cleared software. Writing EXF2 forces Timer interrupt enable. RCLK, Receive Clock Flag. Determine whether Timer Timer used Serial Port timing receive data serial mode RCLK=1 selects Timer overflow receive clock. RCLK=0 selects Timer overflow receive clock. TCLK, Transmit Clock Flag. Determine whether Timer Timer used Serial Port timing transmit data serial mode RCLK=1 selects Timer overflow transmit clock. RCLK=0 selects Timer overflow transmit clock. EXEN2, Timer External Enable. EXEN2=1 enables capture reload occur result high-to-low transition T2EX, Timer generating baud rates serial port. EXEN2=0 causes Timer ignore external events T2EX. TR2, Timer Control Flag. TR2=1 starts Timer TR2=0 stops Timer C/T2 Counter/Timer Selector. C/T2=0 selects timer function Timer C/T2=1 selects counter falling transitions pin. When used timer, Timer clocks tick clocks tick programmed CKCON.5, modes except baud rate generator mode. When used baud rate generator mode, Timer runs clocks tick, independent state CKCON.5 CP/RL2, Capture/Reload Flag. When CP/RL2=1, Timer captures occur high-to-low transitions T2EX, EXEN2=1. When CP/RL2=0, auto-reloads occur when Timer2 overflows when high-to-low transitions occur T2EX, EXEN2=1. either RCLK TCLK CP/RL2 will function Timer will operate auto-reload mode following each overflow.
SCON Register Description SM1,SM0, Serial Port Mode Select bits Mode SM2, Multiprocessor Communication Enable. modes this enables multiprocessor communication feature. SM2=1 mode will activated received SM2=1 mode then will only activated valid stop received. mode establishes baud rate: when SM2=0, baud rate clk/12; when SM2=1, baud rate clk/4. REN, Receive Enable. When REN=1, reception enabled. TB8, Defined state data transmitted modes RB8, modes indicates state received. mode indicates state received stop bit. mode used. Transmit Interrupt Flag. Indicates that transmit data word been shifted out. mode data bit. other modes, when stop placed pin, must cleared software. Receive Interrupt Flag. Indicates that serial data word been received. mode data bit. mode after last sample incoming stop bit, subject state SM2. modes last sample RB8, must cleared software.
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Section Peripheral Device
M6759 three 16-bit timer/counter registers, three configured operate either timers event counters.
oscillator periods. Thus, view register counter with count rate 1/12 oscillator frequency. When operating counter function, register increases according 1-to-0 transition corresponding external input
this function, external input sampled every machine cycle. When samples show high cycle next cycle, counter increases Since takes machine cycles determine transition, count machine cycle ensure given level sampled. addition timer/counter selection, Timer Timer have four operating modes, Timer three operating
Timer0/Timer1 Mode Control Operating Mode Timer/Counter, "THx" with "TLx" prescaler Timer/Counter, "THx" "TLx" cascadent auto-reload timer/counter, each time "TLx" overflows, store value "THx" into "TLx". Timer indicate 8-bit counters controlled Timer Timer2 Mode Control CP/RL2
16-bit auto-reload 16-bit capture Non-active
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Timer/Counter Mode Counter C/T=0 T0/T1 GATE INT0/INT1 Timer/Counter Mode 8-bit Auto-Reload C/T=0 C/T=1 T0/T1 GATE INT0/INT1 Timer Capture Mode C/T2=0 C/T2=1 Transition Detector T2EX CONTROL EXEN2 CONTROL Timer INTERRUPT RCAP2L RCAP2H EXF2 CONTROL OVERFLOW INTERRUPT CONTROL INTERRUPT
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Timer Auto-reload Mode
C/T2=0 C/T2=1 Transition Detector T2EX CONTROL EXEN2 CONTROL Timer INTERRUPT RCAP2L RCAP2H EXF2
Timer Baud Rate Generator Mode
C/T2=0 C/T2=1 Transition Detector T2EX CONTROL EXEN2 EXF2 CONTROL
RCLK
Timer OVERFLOW
SMOD
RCAP2L RCAP2H Timer INTERRUPT
TCLK
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Timer 16-bit Timer/Counter. selected timer event counter register T2CON. three operating modes: "Capture", "Auto-reload" "Baud rate generator". capture mode, there options which selected EXEN2 T2CON. EXEN2 then Timer2 16-bit timer/counter which sets (timer overflow flag) upon overflowing, generate interrupt when Timer interrupt enabled. EXEN2 above operation still activated, with added feature that 1-to0 transition external input T2EX cause content captured into RCAP2L RCAP2H. addition, transition T2EX EXF2 (which T2CON register), EXF2 generate interrupt. Auto-reload mode, there options that selected EXEN2 T2CON. EXEN2 when Timer overflows sets Timer load bits values stored RCAP2L RCAP2H. EXEN2 Timer2 still does above, with added feature that 1-to-0 transition external input T2EX will also trigger 16-bit reload EXF2. Serial Interface serial port full duplex, which means transmit receive data simultaneously. There receive buffer commence reception second byte before previously received byte been read from receive register. first byte been completely read time reception second byte, bytes will still lost). serial port receive transmit data both accessed SBUF. Writing SBUF loads transmit register. Read SBUF accesses physically separate receive register.
Baud Rates Mode Baud rate fixed:
Mode0 Baud Rate
Oscillator Frequency
Baud rate Mode depends SMOD Special Function Register PCON. SMOD baud rate 1/64 oscillator frequency; SMOD baud rate 1/32 oscillator frequency.
Mode2 Baud Rate
SMOD (Oscillator Frequency)
Baud rate Mode Mode determined overflow rate Timer Timer both (one transmit other receive). When Timer used generate Baud rate, determined following equation:
Baud Rate
SMOD (Timer1 Overflow Rate)
Timer interrupt should disabled this application. Timer itself configured either timer counter three running modes. Auto-reload mode (high nibble TMOD 0010B), baud rate given
Mode(1,3) Baud Rate
SMOD Oscillator Frequency (256
When Timer used generate Baud rate, TCLK and/or RCLK T2CON, baud rate transmit receive different.
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baud rate generator mode similar auto reload mode. rollover cause Timer reload with value which stored RCAP2H RCAP2L.
Mode(1,3) Baud Rate
Oscillator Frequency [65536 (RCAP RCAP2
Mode(1,3) Baud Rate
Timer Overflow Rate
where (RCAP2H, RCAP2L) content RCAP2H PCAP2L taken unsigned integer which preset software. Timer baud rate generator mode valid only RCLK TCLK T2CON rollover does TF2, will generate interrupt Also note that EXEN2 set, 1-to-0 transition T2EX will EXF2 will cause reload from (RCAP2H, RCAP2L). this case, T2EX used extra external interrupt desire.
Timer configured either "timer" "counter" operation. Normally, timer increments every machine cycle oscillator cycles), baud rate generator increments every state time oscillator cycles). that case baud rate give following formula:
Timer Reload Values Common Serial Port Mode Baud Rates Desired Baud SMOD Timer Value Value Value Rate Mode clock clock 11.0592 clock 57.6 Kb/s 19.2 Kb/s Kb/s Kb/s Kb/s Kb/s Timer Reload Values Common Serial Port Mode Baud Rates clock clock Desired Baud C/T2 Rate RCAP2H RCAP2L RCAP2H RCAP2L 57.6 Kb/s 19.2 Kb/s Kb/s Kb/s Kb/s Kb/s
11.0592 clock RCAP2H RCAP2L
Ver. 1.01, Document Number 6759DS02.doc Acer Labs: 11F, Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage www.ali.com.tw
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M6759: Micro-controller
Section Electrical Specifications
Absolute Maximum Ratings Absolute maximum ratings those values beyond which damage device occur. Continuous operation these limits intended should limited those conditions specified under electrical characteristics. Unless otherwise specified, voltages reference ground. Table Absolute Maximum Ratings Item Supply voltage Operating supply voltage (VCC) Operating supply voltage (VDD) input output voltages Storage temperature range (TSTG) Operating temperature (TA) D.C. Characteristics SYMBOL PARAMETERS Input Voltage Input High Voltage Output Voltage Output High Voltage Power Supply Current (Active mode) -0.5 VCC+0.5 Unit Test Conditions
Ratings -0.5V 4.5V 5.5V 3.0V 3.6V -0.5V VCC+0.5V
IOL=4.0 IOH= -4.0mA VDD=5V, Frequency=10MHz
Characteristics
SYMBOL tCLCL tCLCL tLHLL tHAVL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tRLRH tWLWH tRLDV tRHDX tLLDV tAVDV tLLWL tAVWL tQVWX tQVWH tWHQX tWHLH
PARAMETERS Oscillator Clock Cycle Period Oscillator Frequency Pulse Width High bytes Address Valid Address Valid Address Hold After Address Valid Instruction /PSEN PSEN Pulse Width /PSEN Valid Instruction Input Instruction Hold After /PSEN /PSEN Address Valid Address Valid Instruction Pulse Width Pulse Width Valid Data Data Hold After Data Valid Address Valid Data Address Data Valid Transition Data Valid High Data Hold After high High
2tCLCL 2tCLCL tCLCL tCLCL tCLCL 3tCLCL 6tCLCL 6tCLCL 3tCLCL 4tCLCL tCLCL 7tCLCL tCLCL
4tCLCL 3tCLCL tCLCL 5tCLCL 5tCLCL 8tCLCL 9tCLCL 3tCLCL tCLCL
Unit
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Ver.1.01, Doc. No.: 6759DS02.doc Acer Labs: 11F, no.45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage: www.ali.com.tw
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External Program Memory Read Cycle
tLHLL
tLLPL
tPLPH tAVLL /PSEN tHAVL tLLAX PORT0 A0-A7 tAVIV PORT2 A8-A15 tPXIX INSTR tLLIV tPLIV
tPXAIZV
A0-A7
External Data Memory Read Cycle tLHLL tWHLH /PSEN tLLWL tRLRH tAVLL PORT0 tLLAX A0-A7 tAVWL tAVDV tHAVL PORT2 P2.0 P2.7 A8-A15 tRLDV DATA tRHDX A0-A7 tLLDV
Ver. 1.01, Document Number 6759DS02.doc Acer Labs: 11F, Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage www.ali.com.tw
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External Data Memory Write Cycle
tLHLL tWHLH /PSEN tLLWL tWLWH tQVWX tAVLL PORT0 tLLAX A0-A7 tAVWL tRLDV tQVWH DATA tWHQX
A0-A7
PORT2
P2.0 P2.7 A8-A15
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Serial Port Timing Shift Register Mode Test Conditions SYMBOL PARAMETER tXLXL Serial Port Clock Cycle Time tCLCL tQVXH Output Data Setup Clock Rising Edge 9tCLCL tXHQX Output Data Hold After Clock Rising Edge 3tCLCL tXHDX Input Data Hold After Clock Rising Edge tXHDV Clock Rising Edge Input Data Valid Shift Register Mode Timing Diagram
10tCLCL
Unit
INSTRUCTION tXLXL CLOCK tQVXH
tXHQX tXHDX tXHDV
WRITE SBUF
Output Data
CLEAR Input Data
Ver. 1.01, Document Number 6759DS02.doc Acer Labs: 11F, Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage www.ali.com.tw
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Section Flash Programming Guide
Features
Kbytes electrically erasable internal program memory Encrypted verifiable 3-level program memory lock program/erase cycles Fully synchronous operation High performance CMOS 100ns read access time external programming voltage
Description flash module completely synchronous. operations synchronized rising edge clock (XTAL1 pin). rising edge XTAL1, pins' status sampled latched. writing internal registers operations, latched information decoded during XTAL1 high period, execution carried falling XTAL1 edge. flash module executes commands using eight Instruction Register (IR), that defines operation executed. Using enables reading, programming erasing main array OTPR. command defined following table.
Table 7-1. Command Definition
Command Read Array Read OTPR (Key bytes lock bits) Erase Array Erase OTPR (Key bytes lock bits) Program Array Program OTPR (Key bytes lock bits) Code
There modules flash main array OTPR. Main Array module' main array contains bytes memory that serve code storage space program code. array occupies address space from 0000H FFFFH. Rows These non-volatile cells contain bytes memory that serve special storage space protection data (i.e. bytes lock bits).
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Ver.1.01, Doc. No.: 6759DS02.doc Acer Labs: 11F, no.45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage: www.ali.com.tw
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Note assignments shown below listed based 44-pin PLCC package. package, number assignment should shifted accordingly, comparatively shown Section Pinout Diagram.
(PLCC) Name RST, ALE, P3.6 P3.1, P3.2, /PSEN P2.7 P2.0 P1.7 P1.0 P0.7 P0.0 P3.0 P3.3 P3.4 P3.5 P3.7 Signal Name Type Description Power supply internal operation, input Ground Always hold during erase, programming read flash module Always hold high during erase, programming read flash module Always hold during erase, programming read flash module Input high-order address bits
High /RESET IR_EN RD/WRb
Input low-order address bits IN/OUT Command/Data Flash reset Instruction register access enable Ready signal Output enable Read/write selection encryption function available only when programmed. Status Bits There status bits constrain protection function M6759. After whole chip erased (include array OTPR), must programmed After bytes lock bits programmed, must programmed status bits bit1 OTPR address 0004. Status bits Program Condition needs programmed after erased. needs programmed after protection function bytes (lock bits, bytes) programmed
Program Lock Bits M6759 programmable lock bits that when programmed according Table will provide different levels protection on-chip code data. lock bits OTPR address 0004. Refer Figure OTPR arrangement. Table 7-2. Program Lock Bits Features Program Lock Bits Protection Type Program Lock features enabled. (Code verify will encrypted Encryption Array programmed.) MOVC instructions executed from external program memory disabled from fetching code bytes from internal memory, sampled latched Reset, further programming flash disabled. Same also verify disabled. Same also external execution disabled. Encryption Array (key bytes) There bytes encryption array that initially unprogrammed (all Every time that byte addressed during verify, address lines used select byte encryption array. This byte then exclusive-NOR' (XNOR) with code byte, creating encryption verify byte. bytes address 0000, 0001, 0002 0003 OTPR space.
Ver. 1.01, Document Number 6759DS02.doc Acer Labs: 11F, Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage www.ali.com.tw
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0000 0001 0002 0003 0004
Key0 Key1 Key2 Key3
started. signal becomes remains until programming over. During period which signal low, module logic inputs sampled. clock signal must kept during period ensure synchronized with clock signal. Verify operation should done following each byte programming. read operation with built margins performed using (RD/WRb high). verify fails, additional programming cycle must applied same address. Programming failure specific address defined consecutive attempts program same address without successful verify. Erasing This mode enables user erase array OTPR. cells erased defined command. command executed upon rising edge XTAL1, following writing erase command into During erase, signal must high avoid contention. signal becomes remains until erase operation over. During period which signal low, module logic inputs sampled. clock signal must kept during period ensure synchronized with clock signal. Verify procedure read operation with built margins, required confirm that word were successfully erased. perform verify user must revert RD/WRb state high, apply address address bus. Verify carried following rising edge XTAL1 signal. addresses have applied sequentially order verify entire array. During verify, must enable reading erased cells. erased cell value thus erased byte contains FFh.
Reserved
Figure 7-1. OTPR Arrangement Programming This mode enables user program main memory verify contents. also allows programming OTPR. cells programmed defined command. order program, required address applied address bus, required data byte applied data program/verify instruction executed. signal must high order avoid contention. This mode operated through Instruction Register, requires loaded prior execution. Several programming pulses required program cell. Note that order succeed programming, byte must fully erased prior programming Erased byte holds value FFh. written holds value zero. When programming
High High /RESET IR_EN High RD/WRb XTAL1
/PSEN P3.0 P3.1 P3.2 P3.3 P3.5 P3.6 P3.7 XTAL1 P2.7 P2.0, P1.7 P1.0
P0.7 P0.0 P3.4
M6759
Fig.7-2. Flash Programming Configuration
Page Ver.1.01, Doc. No.: 6759DS02.doc Acer Labs: 11F, no.45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage: www.ali.com.tw
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Section Packaging Information
44-pin PLCC Package
SYMBOL
Dimension Inches 0.685 0.690 0.650 0.653 0.685 0.690 0.650 0.653 0.168 0.174 0.102 0.105 0.010
SYMBOL 0.695 0.656 0.695 0.656 0.180 0.108
Dimension Inches 0.595 0.610 0.026 0.013 0.02 0.045 0.05
0.625 0.032 0.021 0.04 0.055
Ver. 1.01, Document Number 6759DS02.doc Acer Labs: 11F, Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage www.ali.com.tw
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44-pin Package
0.10
SEATING PLANE
CONTROL DIMENSIONS MILLIMETERS Millimeter Inch Symbol Min. Nom. Max. Min. Nom. Max. 2.55 0.100 0.15 0.25 0.35 0.006 0.010 0.014 1.90 2.05 2.20 0.075 0.081 0.087 -HCAGE 13.20 BASIC 0.520 BASIC PLANE 0.25mm 10.00 BASIC 0.394 BASIC 13.20 BASIC 0.520 BASIC 10.00 BASIC 0.394 BASIC 0.13 0.30 0.005 0.012 0.13 0.005 Symbol Millimeter Inch Min. Nom. Max. Min. Nom. Max. 0.30 0.35 0.45 0.012 0.014 0.018 0.80 0.031 0.10 0.15 0.23 0.004 0.006 0.009 0.315 0.73 0.88 1.03 0.029 0.035 0.041 0.315 1.80 0.063 0.25 0.010 0.10 0.15 0.23 0.004 0.006 0.009 0.20 0.008 0.73 0.88 1.03 0.029 0.035 0.041 0.20 0.008 1.80 0.063 0.20 0.008 NOTES DIMENSION INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25mm SIDE DIMENSIONS INCLUDE MOLD MISMATCH DETERMINED DATUM PLANE (-H-). DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08mm TOTAL. EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT LOCATED LOWER RADIUS LEAD FOOT. Page Ver.1.01, Doc. No.: 6759DS02.doc Acer Labs: 11F, no.45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage: www.ali.com.tw
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Worldwide Distributors Sales Offices: Taiwan Acer Laboratories Inc. (www.ali.com.tw) 11F, Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 8768 -2800 Fax: 8768 -3030 Acer Sertek no.88, Sec. Hsin Road, HsiChih, Taipei Hsien 221,Taiwan, R.O.C. Tel: 2696-3232 Fax: 2696- 3535 Arrow Ally, Inc. 16F, 100, Sec. Hsin Road, HsiChih, Taipei Hsien, Taiwan, R.O.C. Tel: 2696 7388 Fax: 2696 7399 Asec International Inc. Chung Yang Road, Kang, Taipei, Taiwan, R.O.C. Tel: 2786-6677 Fax: 2786 5257 Hong Kong Lestina International Ltd. 14/F, Park Tower Austin Road, Tsimshatsui, Hong Kong Tel: 852-2735 -1736 Fax: 852-2730 5260 Texny Glorytact (HK) Ltd. Unit 6/F, Kaiser Estate Phase Yuen Street, Hunghom, Kowloon, Hong Kong Tel: 2765 0118 Fax: 2765 0557 Singapore Electronic Resources Ltd. Kallang Bahru, 04-00, Singapore 339341 Tel: 0888 Fax: 1111 Japan Unidux Inc. Shin-Ohsaki Kangyo Bldg., 6-4, Ohsaki 1-Chome, Shinagawa-Ku, Tokyo, Japan Tel: 3779 7828 Fax: 3779 7898 Macnica Inc. Hakusan High-Tech Park, 1-22-2 Hakusan, Midori-Ku, Yokohama City, Japan Tel: (45) 6106 Fax: (45) 6107 Teksel Ltd. 2-27-10, Higashi, Shibuya-Ku, 150-0011 Japan Tel: 5467-9000 Fax: 5467-9346 Korea Microsystems Co., Ltd. 801, 8/F, Bethel Bldg., 324-1, Yangjae-Dong, Seocho-Ku, Seoul, Korea Tel: 9131 Fax: 9130 Acetronix Namhan Bldg., 76-42, Hannam-Dong, Yongsan-Ku, Seoul, Korea Tel. 796-4561 Fax. 796-4563 Italy EL.CO.MI. Cassanese, 20090 Segrate (MI), Italy Tel: 39-2-26927430 Fax: 39-2-26927410 U.S.A. Office/European Operations East Brokaw Road Jose, 95131 Tel: (408) 3100 Fax: (408) 3135
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This material recyclable. Pentium trademark Intel Corp. Windows trademark Microsoft Corp. Other brands names property their respective owners. Acer Labs products licensed medical applications, including, limited life support devices without proper authorization from medical officers. Buyers requested inform sales office when planning products medical applications. Product names used this publication identification purposes only trademarks their respective companies. Acer Laboratories Inc. makes warranty products assumes responsibility errors which appear this document does make commitment update information contained herein. Acer Laboratories Inc. retains right make changes these specifications time, without notice. Contact your local sales office obtain latest specifications before placing your order. registered trademark Acer Laboratories Incorporated only used identify ALi' products. ACER LABORATORIES INCORPORATED 1993
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