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LPC1766 Rev. 00.02 August 2008 32-bit Cortex-M3 microcontrol


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LPC1766
Rev. 00.02 August 2008
32-bit Cortex-M3 microcontroller; flash SRAM with Ethernet, Host/Device/OTG, CAN, 12-bit ADC, 10-bit
Objective data sheet
General description
LPC1766 Cortex-M3 based microcontroller embedded applications featuring high level integration power consumption. Cortex-M3 next generation core that offers system enhancements such enhanced debug features higher level support block integration. LPC1766 operates frequencies MHz. Cortex-M3 incorporates 3-stage pipeline uses Harvard architecture with separate local instruction data buses well third peripherals. Cortex-M3 also includes internal prefetch unit that supports speculative branching. peripheral complement LPC1766 includes flash memory, data memory, Ethernet MAC, Device/Host/OTG interface, 8-channel general purpose controller, UARTs, channels, controllers, interface, interfaces, 2-input plus 2-output interface, channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, general purpose timers, 6-output general purpose PWM, ultra-low power with separate battery supply, general purpose pins. LPC1766 pin-compatible LPC2366 ARM7-based microcontroller.
Features
Cortex-M3 processor, running frequencies MHz. Memory Protection Unit (MPU) supporting eight regions included. Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). on-chip flash programmimg memory. Enhanced flash memory accelerator enables high-speed operation with zero wait states. In-System Programming (ISP) In-Application Programming (IAP) on-chip boot loader software. on-chip SRAM includes: SRAM with local code/data high-performance access. SRAM blocks with separate access paths higher throughput. These SRAM blocks used Ethernet, USB, memory, well general purpose instruction data storage.
Semiconductors
LPC1766
Fast communication chip
Eight channel General Purpose controller (GPDMA) multilayer matrix that used with SSP, I2S, UART, Analog-to-Digital Digital-to-Analog converter peripherals, timer match signals, memory-to-memory transfers. Multilayer matrix interconnect provides separate each master. masters include CPU, General Purpose controller, Ethernet MAC, interface. This interconnect provides communication with arbitration delays. Split allows high throughput with stalls between DMA. Serial interfaces: Ethernet with RMII interface dedicated controller. full-speed device/Host/OTG controller with dedicated controller on-chip device, Host, functions. Four UARTs with fractional baud rate generation, internal FIFO, support, RS-485 support. UART modem control I/O, UART IrDA support. 2.0B controller with channels. controller with synchronous, serial, full duplex communication programmable data length. controllers with FIFO multi-protocol capabilities. interfaces used with GPDMA controller. I2C-bus interfaces supporting fast mode with data rate kbits/s with multiple address recognition monitor mode. I2C-bus interface supporting full I2C-bus specification fast mode plus with data rate Mbit/s with multiple address recognition monitor mode. (Inter-IC Sound) interface digital audio input output, with fractional rate control. interface used with GPDMA. interface supports 3-wire 4-wire data transmit receive well master clock input/output. Other peripherals: General Purpose (GPIO) pins with configurable pull-up/down resistors new, configurable open-drain operating mode. 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates MHz, multiple result registers. 12-bit used with GPDMA controller. 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer support. Four general purpose timers/counters, with total eight capture inputs compare outputs. Each timer block external count input support. motor control with support three-phase motor control. Quadrature encoder interface that monitor external quadrature encoder. standard PWM/timer block with external count input. Real-Time Clock (RTC) with separate power domain dedicated oscillator. block includes bytes battery-powered backup registers. Watchdog Timer (WDT) resets microcontroller within reasonable amount time enters erroneous state. System tick timer, including external clock input option. Repetitive interrupt timer provides programmable repeating timed interrupts.
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Each peripheral clock divider further power savings. Standard JTAG test/debug interface compatibility with existing tools. Serial Wire Debug Serial Wire Trace Port options. Emulation trace module enables non-intrusive, high-speed real-time tracing instruction execution. Integrated (Power Management Unit) automatically adjusts internal regulators minimize power consumption during Sleep, Deep sleep, Power-down, Deep power-down modes. Four reduced power modes: Sleep, Deep-sleep, Power-down, Deep power-down. Single power supply (2.4 Four external interrupt inputs configurable edge/level sensitive. pins PORT0 PORT2 used edge sensitive interrupt sources. Non-maskable Interrupt (NMI) input. Clock output function that reflect main oscillator clock, clock, clock, clock, clock. Wakeup Interrupt Controller (WIC) allows automatically wake from priority interrupt that occur while clocks stopped deep sleep, power-down, deep power-down modes. Processor wake-up from Power-down mode interrupts from various peripherals. Brownout detect with separate threshold interrupt forced reset. Power-On Reset (POR). Crystal oscillator with operating range MHz. internal oscillator trimmed accuracy that optionally used system clock. allows operation maximum rate without need high-frequency crystal. from main oscillator, internal oscillator, oscillator. added flexibility. Code Read Protection (CRP) with different security levels. Available 100-pin LQFP package mm).
Applications
eMetering Lighting Industrial networking Alarm systems White goods Motor control
Ordering information
Table Ordering information Package Name LPC1766FBD100
LPC1766_0.02
Type number
Description plastic profile quad flat package; leads; body
Version SOT407-1
LQFP100
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Ordering options
Table Ordering options LPC1766 related LPC17xx parts Flash Total SRAM Ethernet Device/ Host/OTG Device/ Host/OTG Device/ Host/OTG Device/ Host/OTG Device Device Package pins pins pins pins pins pins pins Type number LPC1766FBD100 LPC1765FBD100 LPC1764FBD100 LPC1754FBD80 LPC1753FBD80 LPC1752FBD80 LPC1751FBD80
Sampling 2008 2008 2008 2008 2008 2008 2008
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Block diagram
debug port JTAG interface
XTAL1 XTAL2 RESET
RMII pins
pins
EMULATION TRACE MODULE
TEST/DEBUG INTERFACE
LPC1766
CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS clocks controls CLKOUT
CORTEX-M3
I-code D-code
CONTROLLER master
ETHERNET CONTROLLER WITH master
HOST/ DEVICE/OTG CONTROLLER WITH master slave
system
slave Multilayer Matrix slave SRAM FLASH ACCELERATOR FLASH
HIGH-SPEED GPIO
slave
slave BRIDGE
slave BRIDGE
SCK1 SSEL1 MISO1 MOSI1 RXD0/TXD0 UART1 RD1/2 TD1/2 SCL0/1 SDA0/1 SCK/SSEL MOSI/MISO MAT0/1 CAP0/1
slave group SSP1
slave group SSP0
SCK0 SSEL0 MISO0 MOSI0 RXD2/3 TXD2/3 I2SRX I2STX TX_MCLK RX_MCLK SCL2 SDA2 MAT2 MAT3 CAP2 CAP3 EINT[3:0]
UART0/1 CAN1/2
UART2/3
I2C0/1 SPI0 TIMER I2C2 TIMER TIMER2/3 EXTERNAL INTERRUPTS SYSTEM CONTROL CONNECT MOTOR CONTROL GPIO INTERRUPT CONTROL
PWM1[7:0] AD0[7:0]
PWM1 12-bit
MC0A/B MC1A/B MC2A/B MCFB1/2 MCABORT AOUT PHA, INDEX
RTCX1 RTCX2 VBAT
OSCILLATOR
QUADRATURE ENCODER
BACKUP REGISTERS POWER DOMAIN
002aad944
Grey-shaded blocks represent peripherals with connection GPDMA.
LPC1766_0.02
Block diagram
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Pinning information
Pinning
LPC176xFBD100
002aad945
configuration LQFP100 package
description
Table Symbol P0[0] P0[31] description Type Description Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins this port available. P0[0] General purpose digital input/output pin. CAN1 receiver input. TXD3 Transmitter output UART3. SDA1 I2C1 data input/output (this I2C-bus compliant open-drain pin). P0[1] General purpose digital input/output pin. CAN1 transmitter output. RXD3 Receiver input UART3. SCL1 I2C1 clock input/output (this I2C-bus compliant open-drain pin). P0[2] General purpose digital input/output pin. TXD0 Transmitter output UART0. AD0[7] converter input P0[3] General purpose digital input/output pin. RXD0 Receiver input UART0. AD0[6] converter input P0[4] General purpose digital input/output pin. I2SRX_CLK Receive Clock. driven master received slave. Corresponds signal I2S-bus specification. CAN2 receiver input. CAP2[0] Capture input Timer channel
P0[0]/RD1/TXD3/ SDA1
46[1]
P0[1]/TD1/RXD3/ SCL1
47[1]
P0[2]/TXD0/AD0[7] 98[2]
P0[3]/RXD0/AD0[6]
99[2]
P0[4]/ I2SRX_CLK/ RD2/CAP2[0]
81[1]
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Table Symbol
description .continued 80[1] Type Description P0[5] General purpose digital input/output pin.
P0[5]/ I2SRX_WS/ TD2/CAP2[1]
I2SRX_WS Receive Word Select. driven master received slave. Corresponds signal I2S-bus specification. CAN2 transmitter output. CAP2[1] Capture input Timer channel P0[6] General purpose digital input/output pin. I2SRX_SDA Receive data. driven transmitter read receiver. Corresponds signal I2S-bus specification. SSEL1 Slave Select SSP1. MAT2[0] Match output Timer channel P0[7] General purpose digital input/output pin. I2STX_CLK Transmit Clock. driven master received slave. Corresponds signal I2S-bus specification. SCK1 Serial Clock SSP1. MAT2[1] Match output Timer channel P0[8] General purpose digital input/output pin.
P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0]
79[1]
P0[7]/ I2STX_CLK/ SCK1/MAT2[1]
78[1]
P0[8]/ I2STX_WS/ MISO1/MAT2[2]
77[1]
I2STX_WS Transmit Word Select. driven master received slave. Corresponds signal I2S-bus specification. MISO1 Master Slave SSP1. MAT2[2] Match output Timer channel P0[9] General purpose digital input/output pin. I2STX_SDA Transmit data. driven transmitter read receiver. Corresponds signal I2S-bus specification. MOSI1 Master Slave SSP1. MAT2[3] Match output Timer channel P0[10] General purpose digital input/output pin. TXD2 Transmitter output UART2. SDA2 I2C2 data input/output (this open-drain pin). MAT3[0] Match output Timer channel P0[11] General purpose digital input/output pin. RXD2 Receiver input UART2. SCL2 I2C2 clock input/output (this open-drain pin). MAT3[1] Match output Timer channel P0[15] General purpose digital input/output pin. TXD1 Transmitter output UART1. SCK0 Serial clock SSP0. Serial clock SPI. P0[16] General purpose digital input/output pin. RXD1 Receiver input UART1. SSEL0 Slave Select SSP0. SSEL Slave Select SPI.
P0[9]/ I2STX_SDA/ MOSI1/MAT2[3]
76[1]
P0[10]/TXD2/ SDA2/MAT3[0]
48[1]
P0[11]/RXD2/ SCL2/MAT3[1]
49[1]
P0[15]/TXD1/ SCK0/SCK
62[1]
P0[16]/RXD1/ SSEL0/SSEL
63[1]
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Table Symbol
description .continued 61[1] Type Description P0[17] General purpose digital input/output pin. CTS1 Clear Send input UART1. MISO0 Master Slave SSP0. MISO Master Slave SPI. P0[18] General purpose digital input/output pin. DCD1 Data Carrier Detect input UART1. MOSI0 Master Slave SSP0. MOSI Master Slave SPI. P0[19] General purpose digital input/output pin. DSR1 Data Ready input UART1.
P0[17]/CTS1/ MISO0/MISO
P0[18]/DCD1/ MOSI0/MOSI
60[1]
P0[19]/DSR1/ SDA1
59[1]
SDA1 I2C1 data input/output (this I2C-bus compliant open-drain pin). P0[20] General purpose digital input/output pin. DTR1 Data Terminal Ready output UART1. SCL1 I2C1 clock input/output (this I2C-bus compliant open-drain pin). P0[21] General purpose digital input/output pin. Ring Indicator input UART1. CAN1 receiver input. P0[22] General purpose digital input/output pin. RTS1 Request Send output UART1. CAN1 transmitter output. P0[23] General purpose digital input/output pin. AD0[0] converter input I2SRX_CLK Receive Clock. driven master received slave. Corresponds signal I2S-bus specification. CAP3[0] Capture input Timer channel P0[24] General purpose digital input/output pin. AD0[1] converter input I2SRX_WS Receive Word Select. driven master received slave. Corresponds signal I2S-bus specification. CAP3[1] Capture input Timer channel P0[25] General purpose digital input/output pin. AD0[2] converter input I2SRX_SDA Receive data. driven transmitter read receiver. Corresponds signal I2S-bus specification. TXD3 Transmitter output UART3. P0[26] General purpose digital input/output pin. AD0[3] converter input AOUT converter output. RXD3 Receiver input UART3. P0[27] General purpose digital input/output pin. Output open-drain. SDA0 I2C0 data input/output. Open-drain output (for I2C-bus compliance). USB_SDA port serial data (OTG transceiver).
B.V. 2008. rights reserved.
P0[20]/DTR1/SCL1 58[1]
P0[21]/RI1/RD1
57[1]
P0[22]/RTS1/TD1
56[1]
P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0]
9[2]
P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1]
8[2]
P0[25]/AD0[2]/ I2SRX_SDA/ TXD3
7[2]
P0[26]/AD0[3]/ AOUT/RXD3
6[3]
P0[27]/SDA0/ USB_SDA
25[4]
LPC1766_0.02
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Table Symbol
description .continued 24[4] Type 29[5] 30[5] Description
P0[28]/SCL0/ USB_SCL
P0[28] General purpose digital input/output pin. Output open-drain. USB_SCL port serial clock (OTG transceiver). P0[29] General purpose digital input/output pin. USB_D+ bidirectional line. P0[30] General purpose digital input/output pin. USB_D- bidirectional line.
SCL0 I2C0 clock input/output. Open-drain output (for I2C-bus compliance).
P0[29]/USB_D+ P0[30]/USB_D- P1[0] P1[31]
Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins this port available. P1[0] General purpose digital input/output pin. ENET_TXD0 Ethernet transmit data P1[1] General purpose digital input/output pin. ENET_TXD1 Ethernet transmit data P1[4] General purpose digital input/output pin. ENET_TX_EN Ethernet transmit data enable. P1[8] General purpose digital input/output pin. ENET_CRS Ethernet carrier sense. P1[9] General purpose digital input/output pin. ENET_RXD0 Ethernet receive data. P1[10] General purpose digital input/output pin. ENET_RXD1 Ethernet receive data. P1[14] General purpose digital input/output pin. ENET_RX_ER Ethernet receive error. P1[15] General purpose digital input/output pin. ENET_REF_CLK Ethernet reference clock. P1[16] General purpose digital input/output pin. ENET_MDC Ethernet MIIM clock. P1[17] General purpose digital input/output pin. ENET_MDIO Ethernet MIIM data input output. P1[18] General purpose digital input/output pin. USB_UP_LED GoodLink indicator. when device configured (non-control endpoints enabled). HIGH when device configured during global suspend. PWM1[1] Pulse Width Modulator channel output. CAP1[0] Capture input Timer channel P1[19] General purpose digital input/output pin. MC0A Motor control channel output USB_PPWR Port Power enable signal port. CAP1[1] Capture input Timer channel
P1[0]/ ENET_TXD0 P1[1]/ ENET_TXD1 P1[4]/ ENET_TX_EN P1[8]/ ENET_CRS P1[9]/ ENET_RXD0 P1[10]/ ENET_RXD1 P1[14]/ ENET_RX_ER P1[15]/ ENET_REF_CLK P1[16]/ ENET_MDC P1[17]/ ENET_MDIO P1[18]/ USB_UP_LED/ PWM1[1]/ CAP1[0]
95[1] 94[1] 93[1] 92[1] 91[1] 90[1] 89[1] 88[1] 87[1] 86[1] 32[1]
P1[19]/MC0A/ USB_PPWR CAP1[1] 33[1]
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Table Symbol
description .continued 34[1] Type Description P1[20] General purpose digital input/output pin.
P1[20]/MCFB0/ PWM1[2]/SCK0
MCFB0 Motor control channel feedback input. Also Quadrature Encoder Interface input. PWM1[2] Pulse Width Modulator channel output. SCK0 Serial clock SSP0. P1[21] General purpose digital input/output pin. MCABORT Motor control PWM, emergency abort. PWM1[3] Pulse Width Modulator channel output. SSEL0 Slave Select SSP0. P1[22] General purpose digital input/output pin. MC0B Motor control channel output USB_PWRD Power Status port (host power switch). MAT1[0] Match output Timer channel P1[23] General purpose digital input/output pin. MCFB1 Motor control channel feedback input. Also Quadrature Encoder Interface input. PWM1[4] Pulse Width Modulator channel output. MISO0 Master Slave SSP0. P1[24] General purpose digital input/output pin. MCFB2 Motor control channel feedback input. Also Quadrature Encoder Interface INDEX input. PWM1[5] Pulse Width Modulator channel output. MOSI0 Master Slave SSP0. P1[25] General purpose digital input/output pin. MC1A Motor control channel output MAT1[1] Match output Timer channel P1[26] General purpose digital input/output pin. MC1B Motor control channel output PWM1[6] Pulse Width Modulator channel output. CAP0[0] Capture input Timer channel P1[27] General purpose digital input/output pin. CLKOUT Clock output pin. USB_OVRCR port Over-Current status. CAP0[1] Capture input Timer channel P1[28] General purpose digital input/output pin. MC2A Motor control channel output PCAP1[0] Capture input PWM1, channel MAT0[0] Match output Timer channel P1[29] General purpose digital input/output pin. MC2B Motor control channel output PCAP1[1] Capture input PWM1, channel MAT0[1] Match output Timer channel
P1[21]/MCABORT/ PWM1[3]/ SSEL0
35[1]
P1[22]/MC0B/ USB_PWRD/ MAT1[0]
36[1]
P1[23]/MCFB1/ PWM1[4]/MISO0
37[1]
P1[24]/MCFB2/ PWM1[5]/MOSI0
38[1]
P1[25]/MC1A/ MAT1[1]
39[1]
P1[26]/MC1B/ PWM1[6]/CAP0[0]
40[1]
P1[27]/CLKOUT /USB_OVRCR/ CAP0[1]
43[1]
P1[28]/MC2A PCAP1[0]/ MAT0[0]
44[1]
P1[29]/MC2B/ PCAP1[1]/ MAT0[1]
45[1]
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Table Symbol
description .continued 21[2] Type Description P1[30] General purpose digital input/output pin. VBUS Monitors presence power. Note: This signal must HIGH reset occur. AD0[4] converter input P1[31] General purpose digital input/output pin. SCK1 Serial Clock SSP1. AD0[5] converter input
P1[30]/VBUS/ AD0[4]
P1[31]/SCK1/ AD0[5]
20[2]
P2[0] P2[31]
Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins through this port available. P2[0] General purpose digital input/output pin. PWM1[1] Pulse Width Modulator channel output. TXD1 Transmitter output UART1. P2[1] General purpose digital input/output pin. PWM1[2] Pulse Width Modulator channel output. RXD1 Receiver input UART1. P2[2] General purpose digital input/output pin. PWM1[3] Pulse Width Modulator channel output. CTS1 Clear Send input UART1. TRACEDATA[3] Trace data, P2[3] General purpose digital input/output pin. PWM1[4] Pulse Width Modulator channel output. DCD1 Data Carrier Detect input UART1. TRACEDATA[2] Trace data, P2[4] General purpose digital input/output pin. PWM1[5] Pulse Width Modulator channel output. DSR1 Data Ready input UART1. TRACEDATA[1] Trace data, P2[5] General purpose digital input/output pin. PWM1[6] Pulse Width Modulator channel output. DTR1 Data Terminal Ready output UART1. TRACEDATA[0] Trace data, P2[6] General purpose digital input/output pin. PCAP1[0] Capture input PWM1, channel Ring Indicator input UART1. TRACECLK Trace Clock. P2[7] General purpose digital input/output pin. CAN2 receiver input. RTS1 Request Send output UART1.
P2[0]/PWM1[1]/ TXD1
75[1]
P2[1]/PWM1[2]/ RXD1
74[1]
P2[2]/PWM1[3]/ CTS1/ TRACEDATA[3]
73[1]
P2[3]/PWM1[4]/ DCD1/ TRACEDATA[2]
70[1]
P2[4]/PWM1[5]/ DSR1/ TRACEDATA[1]
69[1]
P2[5]/PWM1[6]/ DTR1/ TRACEDATA[0]
68[1]
P2[6]/PCAP1[0]/ RI1/TRACECLK
67[1]
P2[7]/RD2/ RTS1
66[1]
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Table Symbol P2[8]/TD2/ TXD2
description .continued 65[1] Type 64[1] Description P2[8] General purpose digital input/output pin. CAN2 transmitter output. TXD2 Transmitter output UART2. P2[9] General purpose digital input/output pin.
P2[9]/ USB_CONNECT/ RXD2
USB_CONNECT Signal used switch external resistor under software control. Used with SoftConnect feature. RXD2 Receiver input UART2. P2[10] General purpose digital input/output pin. Note: this while RESET forces on-chip bootloader take over control part after reset.
P2[10]/EINT0/NMI
53[6]
P2[11]/EINT1/ I2STX_CLK 52[6] P2[12]/EINT2/ I2STX_WS 51[6] P2[13]/EINT3/ I2STX_SDA 50[6] P3[0] P3[31]
EINT0 External interrupt input. Non-maskable interrupt input. P2[11] General purpose digital input/output pin. EINT1 External interrupt input. I2STX_CLK Transmit Clock. driven master received slave. Corresponds signal I2S-bus specification. P2[12] General purpose digital input/output pin. EINT2 External interrupt input. I2STX_WS Transmit Word Select. driven master received slave. Corresponds signal I2S-bus specification. P2[13] General purpose digital input/output pin. EINT3 External interrupt input. I2STX_SDA Transmit data. driven transmitter read receiver. Corresponds signal I2S-bus specification. Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins through through this port available. P3[25] General purpose digital input/output pin. MAT0[0] Match output Timer channel PWM1[2] Pulse Width Modulator output P3[26] General purpose digital input/output pin. STCLK System tick timer clock input. MAT0[1] Match output Timer channel PWM1[3] Pulse Width Modulator output Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins through this port available. P4[28] General purpose digital input/output pin. RX_MCLK receive master clock. MAT2[0] Match output Timer channel TXD3 Transmitter output UART3.
P3[25]/MAT0[0]/ PWM1[2]
27[1]
P3[26]/STCLK/ MAT0[1]/PWM1[3]
26[1]
P4[0] P4[31]
P4[28]/RX_MCLK/ MAT2[0]/TXD3
82[1]
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Table Symbol
description .continued 85[1] Type Description P4[29] General purpose digital input/output pin. TX_MCLK transmit master clock. MAT2[1] Match output Timer channel RXD3 Receiver input UART3. Test Data JTAG interface. Serial wire trace output. Test Data JTAG interface. Test Mode Select JTAG interface. SWDIO Serial wire debug data input/output. TRST Test Reset JTAG interface. Test Clock JTAG interface. SWDCLK Serial wire clock. RTCK JTAG interface control signal.
P4[29]/TX_MCLK/ MAT2[1]/RXD3
TDO/SWO TMS/SWDIO TRST TCK/SWDCLK RTCK RSTOUT RESET
1[1] 2[1] 3[1] 4[1] 5[1] 100[1] 17[7]
RSTOUT This pin. this indicates LPC1766 being Reset state. External reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. Input oscillator circuit internal clock generator circuits. Output from oscillator amplifier. Input oscillator circuit. Output from oscillator circuit. ground: reference.
XTAL1 XTAL2 RTCX1 RTCX2
22[8] 23[8] 16[8] 18[8] 83[8] 11[8] 96[8] 84[8] 10[8]
VSSA VDD(3V3) VREG(3V3) VDDA
analog ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. supply voltage: This power supply voltage ports. voltage regulator supply voltage: This supply voltage on-chip voltage regulator only. analog supply voltage: This should nominally same voltage VDD(3V3) should isolated minimize noise error. This voltage used power DAC. positive reference voltage: This should nominally same voltage VDDA should isolated minimize noise error. Level this used reference DAC. negative reference voltage: This should nominally same voltage should isolated minimize noise error. Level this used reference DAC. power supply: this supplies power peripheral. connected
VREFP
12[8]
VREFN
VBAT n.c.
19[8]
tolerant providing digital functions with levels hysteresis.
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
tolerant providing digital functions (with levels hysteresis) analog input. When configured input, digital section disabled.
tolerant providing digital with levels hysteresis analog output function. When configured output, digital section disabled.
Open-drain tolerant digital pad, compatible with I2C-bus specification. This requires external pull-up provide output functionality. When power switched off, this connected I2C-bus floating does disturb lines. Open-drain configuration applies functions this pin.
provides digital functions. designed accordance with specification, revision (Full-speed Low-speed mode only). tolerant with glitch filter providing digital functions with levels hysteresis. tolerant with glitch filter providing digital function with levels hysteresis. provides special analog functionality.
Functional description
Architectural overview
Cortex-M3 includes three AHB-Lite buses: system bus, I-code bus, D-code (see Figure I-code D-code core buses faster than system used similarly interfaces: dedicated instruction fetch (I-code) data access (D-code). core buses allows simultaneous operations concurrent operations target different devices. LPC1766 uses multi-layer matrix connect Cortex-M3 buses other masters peripherals flexible manner that optimizes performance allowing peripherals that different slaves ports matrix accessed simultaneously different masters.
Cortex-M3 processor
Cortex-M3 general purpose, 32-bit microprocessor, which offers high performance very power consumption. Cortex-M3 offers many features, including Thumb-2 instruction set, interrupt latency, hardware divide, interruptable/continuable multiple load store instructions, automatic state save restore interrupts, tightly integrated interrupt controller with wakeup interrupt controller, multiple core buses capable simultaneous accesses. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. Cortex-M3 processor described detail Cortex-M3 Technical Reference Manual that found official website.
On-chip flash program memory
LPC1766 contains on-chip flash memory. two-port flash accelerator maximizes performance with fast AHB-Lite buses.
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On-chip SRAM
LPC1766 contains total on-chip static memory. This includes main SRAM, accessible controller higher-speed bus, additional each SRAM blocks situated separate slave port multilayer matrix. This architecture allows accesses spread over three separate RAMs that accessed simultaneously.
Memory Protection Unit (MPU)
LPC1766 Memory Protection Unit (MPU) which used improve reliability embedded system protecting critical data within user application. allows separating processing tasks disallowing access each other's data, disabling access memory regions, allowing memory regions defined read-only detecting unexpected memory accesses that could potentially break system. separates memory into distinct regions implements protection preventing disallowed accesses. supports regions each which divided into subregions. Accesses memory locations that defined regions, permitted region setting, will cause Memory Management Fault exception take place.
Memory
LPC17xx incorporates several distinct memory regions, shown following figures. Figure shows overall entire address space from user program viewpoint following reset. interrupt vector area supports address remapping. peripheral area megabyte size, divided allow upto peripherals. peripheral area megabyte size divided allow peripherals. Each peripheral either type allocated kilobytes space. This allows simplifying address decoding each peripheral.
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0x4010 0000 0x400F C000 0x400C 0000 0x400B C000 0x400B 8000 0x400B 4000 0x400B 0000 0x400A C000 0x400A 8000 0x400A 4000 0x400A 0000 0x4009 C000 0x4009 8000 0x4009 4000 0x4009 0000 0x4008 C000 0x4008 8000 0x4008 0000
APB1 peripherals system control used motor control used used used I2C2 UART3 UART2 Timer Timer SSP0 reserved
LPC1766 memory space 0xFFFF FFFF reserved 0xE010 0000 private peripheral reserved 0x5020 0000 peripherals reserved 0x4400 0000 peripheral band alias addressing reserved APB1 peripherals 0x4200 0000 0x4010 0000 0x4008 0000 0x4000 0000 0x2400 0000 SRAM band alias addressing 0x2200 0000 reserved 0x2000 8000 0x1000 0000 0x0004 0000 0x5000 0000 0xE000 0000
peripherals 127- used GPIO reserved controller reserved GPDMA controller Ethernet controller
0x5020 0000 0x5001 8000 0x5001 4000 0x5001 0000 0x5000 C000 0x5000 8000 0x5000 4000 0x5000 0000
repetitive interrupt timer
APB0 peripherals used I2C1 used CAN2 CAN1 common registers SSP1 connect GPIO interrupts backup registers I2C0 PWM1 used UART1 UART0 TIMER1 TIMER0
0x4008 0000 0x4006 0000 0x4005 C000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 0x4003 4000 0x4003 0000 0x4002 C000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000
APB0 peripherals reserved
SRAM blocks reserved boot reserved
0x2000 0000 0x1FFF 2000 0x1FFF 0000 0x1000 8000
I-code/D-code memory space
local static
reserved 0x0000 0200 0x0000 0000 active interrupt vectors on-chip flash byte 0x0000 0000
FastFcommunication Tchip
0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000
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Nested Vectored Interrupt Controller (NVIC)
Nested Vectored Interrupt Controller (NVIC) integral part Cortex-M3. tight coupling allows interrupt latency efficient processing late arriving interrupts.
7.7.1 Features
Controls system exceptions peripheral interrupts LPC1766, NVIC supports vectored interrupts programmable interrupt priority levels, with hardware priority level masking Relocatable vector table Non-Maskable Interrupt (NMI) Software interrupt generation
7.7.2 Interrupt sources
Each peripheral device interrupt line connected NVIC have several interrupt flags. Individual interrupt flags also represent more than interrupt source. PORT0 PORT2 (total pins) regardless selected function, programmed generate interrupt rising edge, falling edge, both.
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between on-chip peripherals. Peripherals should connected appropriate pins prior being activated prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined. Most pins also configured open-drain outputs have pull-up, pull-down, resistor enabled.
General purpose controller
GPDMA AMBA compliant peripheral allowing selected LPC1766 peripherals have support. GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, memory-to-memory transactions. source destination areas each either memory region peripheral, accessed through master. GPDMA controller allows data transfers between Ethernet controllers various on-chip SRAM areas. supported peripherals SSP0/1, UARTs, interface, ADC, DAC. match signals each timer used trigger transfers.
7.9.1 Features
Eight channels. Each channel support unidirectional transfer.
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request lines. Single burst request signals. Each peripheral connected
Controller assert either burst request single request. burst size programming Controller.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory,
peripheral-to-peripheral transfers supported.
Scatter gather supported through linked lists. This means that
source destination areas have occupy contiguous areas memory.
Hardware channel priority. slave programming interface. Controller programmed
writing control registers over slave interface.
master transferring data. interface transfers data when
request goes active.
32-bit master width. Incrementing non-incrementing addressing source destination. Programmable burst size. burst size programmed more
efficiently transfer data.
Internal four-word FIFO channel. Supports 32-bit wide transactions. Big-endian little-endian support. Controller defaults little-endian
mode reset.
interrupt processor generated completion when
error occurred.
interrupt status. error count interrupt status read
prior masking.
7.10 Fast general purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back well current state port pins. LPC1766 uses accelerated GPIO functions:
GPIO registers dedicated peripheral accessed through
multilayer that fastest possible timing achieved.
Mask registers allow treating sets port bits group, leaving other bits
unchanged.
GPIO registers byte half-word addressable. Entire port value written instruction.
Additionally, PORT0 PORT2 (total pins) providing digital function programmed generate interrupt rising edge, falling edge, both. edge detection asynchronous, operate when clocks present such during Power-down mode. Each enabled interrupt used wake chip from Power-down mode.
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7.10.1 Features
bits port.
level clear registers allow single instruction clear number
Direction control individual bits. default inputs after reset. Pull-up/pull-down resistor configuration open-drain configuration
programmed through connect block each GPIO pin.
7.11 Ethernet
Ethernet block contains full featured Mbit/s Mbit/s Ethernet designed provide optimized performance through hardware acceleration. Features include generous suite control registers, half full duplex operation, flow control, control frames, hardware acceleration transmit retry, receive packet filtering wake-up activity. Automatic frame transmission reception with scatter-gather off-loads many operations from CPU. Ethernet block share Cortex-M3 D-code system through AHB-multilayer matrix access various on-chip SRAM blocks Ethernet data, control, status information. Ethernet block interfaces between off-chip Ethernet using Reduced (RMII) protocol on-chip Media Independent Interface Management (MIIM) serial bus. Ethernet block supports clock rates MHz.
7.11.1 Features
Ethernet standards support:
Supports Mbit/s Mbit/s devices including Base-T, Base-TX, Base-FX, Base-T4. Fully compliant with IEEE standard 802.3. Fully compliant with 802.3x full duplex flow control half duplex back pressure. Flexible transmit receive frame options. Virtual Local Area Network (VLAN) frame support.
Memory management:
Independent transmit receive buffers memory mapped shared SRAM. managers with scatter/gather arrays frame descriptors. Memory traffic optimized buffering pre-fetching.
Enhanced Ethernet features:
Receive filtering. Multicast broadcast frame support both transmit receive. Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) transmit. Selectable automatic transmit frame padding.
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Over-length frame support both transmit receive allows length frames.
Promiscuous receive mode. Automatic collision back-off frame retransmission. Includes power management clock switching.
Wake-on-LAN power management support allows system wake-up: using receive filters magic frame detection filter.
Physical interface:
Attachment external chip through standard RMII interface. register access available MIIM interface.
7.12 interface
Universal Serial (USB) 4-wire that supports communication between host more 127) peripherals. host controller allocates bandwidth attached devices through token-based protocol. supports plugging dynamic configuration devices. transactions initiated host controller. LPC1766 interface includes device, Host, controller with on-chip device Host functions. switching protocol supported through external controller. Details typical interfacing solutions found Section 14.1.
7.12.1 device controller
device controller enables Mbit/s data exchange with Host controller. consists register interface, serial interface engine, endpoint buffer memory, controller. serial interface engine decodes data stream writes data appropriate endpoint buffer. status completed transfer error condition indicated status registers. interrupt also generated enabled. When enabled, controller transfers data between endpoint buffer on-chip SRAM (see Figure 7.12.1.1 Features
Fully compliant with specification (full speed). Supports physical logical) endpoints with endpoint buffer RAM. Supports Control, Bulk, Interrupt Isochronous endpoints. Scalable realization endpoints time. Endpoint Maximum packet size selection maximum specification) software time.
Supports SoftConnect GoodLink features. While Suspend mode, LPC1766 enter reduced power
modes wake activity.
Supports transfers with on-chip SRAM blocks
non-control endpoints.
Allows dynamic switching between CPU-controlled slave modes. Double buffer implementation Bulk Isochronous endpoints.
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7.12.2 host controller
host controller enables full- low-speed data exchange with devices attached bus. consists register interface, serial interface engine, controller. register interface complies with OHCI specification.
7.12.2.1
Features
OHCI compliant. downstream port. Supports port power switching.
7.12.3 controller
(On-The-Go) supplement specification that augments capability existing mobile devices peripherals adding host functionality connection peripherals. Controller integrates host controller, device controller, master-only interface implement dual-role device functionality. dedicated interface controls external transceiver. 7.12.3.1 Features
Fully compliant with On-The-Go supplement Specification, Revision
1.0a.
Hardware support Host Negotiation Protocol (HNP). Includes programmable timer required Session Request Protocol
(SRP).
Supports transceiver compliant with Transceiver Specification
(CEA-2011), Rev. 1.0.
7.13 controller acceptance filters
Controller Area Network (CAN) serial communications protocol which efficiently supports distributed real-time control with very high level security. domain application ranges from high-speed networks cost multiplex wiring. block intended support multiple buses simultaneously, allowing device used gateway, switch, router among number buses industrial automotive applications.
7.13.1 Features
controllers buses. Data rates Mbit/s each bus. 32-bit register access. Compatible with specification 2.0B, 11898-1. Global Acceptance Filter recognizes standard (11-bit) extended-frame (29-bit) receive identifiers buses. Standard Identifiers.
Acceptance Filter provide FullCAN-style automatic reception selected
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FullCAN messages generate interrupts. 7.14 12-bit
LPC1766 contains ADC. single 12-bit successive approximation with eight channels support.
7.14.1 Features
12-bit successive approximation ADC. Input multiplexing among pins. Power-down mode. Measurement range Vi(VREFN) Vi(VREFP). 12-bit conversion rate: MHz. Individual channels selected conversion. Burst conversion mode single multiple inputs. Optional conversion transition input Timer Match signal. Individual result registers each channel reduce interrupt overhead. support.
7.15 10-bit
allows LPC1766 generate variable analog output. maximum output value Vi(VREFP).
7.15.1 Features
10-bit Resistor string architecture Buffered output Power-down mode Selectable output drive Dedicated conversion timer support
7.16 UARTs
LPC1766 each contain four UARTs. addition standard transmit receive data lines, UART1 also provides full modem control handshake interface. Support RS-485/9-bit mode allows both software address detection automatic address detection using 9-bit mode. UARTs include fractional baud rate generator. Standard baud rates such 115200 achieved with crystal frequency above MHz.
7.16.1 Features
Receive Transmit FIFOs.
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Register locations conform 16C550 industry standard. Receiver FIFO trigger points Built-in fractional baud rate generator covering wide range baud rates without
need external crystals particular values.
Fractional divider baud rate control, auto baud capabilities FIFO control
mechanism that enables software flow control implementation.
UART1 equipped with standard modem interface signals. This module also provides
full support hardware flow control (auto-CTS/RTS).
Support RS-485/9-bit mode. UART3 includes IrDA mode support infrared communication. UARTs have support. 7.17 serial controller
LPC1766 contains controller. full duplex serial interface designed handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends bits bits data slave, slave always sends bits bits data master.
7.17.1 Features
Compliant with specification Synchronous, serial, full duplex communication Combined master slave Maximum data rate eighth input clock rate bits bits transfer
7.18 serial controller
LPC1766 contains controllers. controller capable operation SPI, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. Only single master single slave communicate during given data transfer. supports full duplex transfers, with frames bits bits data flowing from master slave from slave master. practice, often only these data flows carries meaningful data.
7.18.1 Features
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, National
Semiconductor Microwire buses
Synchronous serial communication Master slave operation 8-frame FIFOs both transmit receive 4-bit 16-bit frame transfers supported GPDMA
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7.19 I2C-bus serial controllers
LPC1766 each contain three I2C-bus controllers.
I2C-bus bidirectional, inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver) transmitter with capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. multi-master controlled more than master connected
7.19.1 Features
I2C0 standard compliant interface with open-drain pins. I2C0 also
supports Fast mode plus with rates Mbit/s.
I2C1 I2C2 standard pins with rates kbit/s (Fast I2C-bus). Easy configure master, slave, master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial data bus. serial bus.
Serial clock synchronization allows devices with different rates communicate Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes. I2C-bus controllers support multiple address recognition monitor mode. 7.20 I2S-bus serial controllers
I2S-bus provides standard communication interface digital audio applications. I2S-bus specification defines 3-wire serial using data line, clock line, word select signal. basic connection master, which always master, slave. interface LPC1766 provides separate transmit receive channel, each which operate either master slave.
7.20.1 Features
interface separate input/output channels each which operate master
slave mode.
Capable handling 8-bit, 16-bit, 32-bit word sizes. Mono stereo audio data supported. sampling frequency range from (16, 22.05, 44.1,
kHz.
Support audio master clock. Configurable word select period master mode (separately input output).
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8-word FIFO data buffers provided, transmit receive. Generates interrupt requests when buffer levels cross programmable boundary. requests, controlled programmable buffer levels. These connected
GPDMA block.
Controls include reset, stop mute options separately input output. 7.21 General purpose 32-bit timers/external event counters
LPC1766 include four 32-bit timer/counters. timer/counter designed count cycles system derived clock externally-supplied clock. optionally generate interrupts, generate timed requests, perform other actions specified timer values, based four match registers. Each timer/counter also includes capture inputs trap timer value when input signal transitions, optionally generating interrupt.
7.21.1 Features
32-bit timer/counter with programmable 32-bit prescaler. Counter timer operation. 32-bit capture channels timer, that take snapshot timer value
when input signal transitions. capture event also generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
four external outputs corresponding match registers, with following
capabilities: match. HIGH match. Toggle match. nothing match.
match registers used generate timed requests. 7.22 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC1766. Timer designed count cycles system derived clock optionally switch pins, generate interrupts perform other actions when specified timer values occur, based seven match registers. function addition these features, based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions.
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match registers used provide single edge controlled output. match register (PWMMR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when PWMMR0 match occurs.
Three match registers used provide output with both edges controlled. Again, PWMMR0 match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge).
7.22.1 Features
LPC1766 block with Counter Timer operation (may
peripheral clock capture inputs clock source).
Seven match registers allow single edge controlled double edge
controlled outputs, both types. match registers also allow: Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs. Single
edge controlled outputs high beginning each cycle unless output constant low. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive going
negative going pulses.
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard 32-bit timer/counter with programmable 32-bit prescaler
mode enabled.
7.23 Motor control
motor control specialized supporting 3-phase motors other combinations. Feedback inputs provided automatically sense rotor position that information ramp speed down. abort input also provided that causes
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immediately release motor drive outputs. same time, motor control highly configurable other generalized timing, counting, capture, compare applications.
7.24 Quadrature Encoder Interface (QEI)
quadrature encoder, also known 2-channel incremental encoder, converts angular displacement into pulse signals. monitoring both number pulses relative phase signals, user track position, direction rotation, velocity. addition, third channel, index signal, used reset position counter. quadrature encoder interface decodes digital pulses from quadrature encoder wheel integrate position over time determine direction rotation. addition, capture velocity encoder wheel.
7.24.1 Features
Tracks encoder position. Increments/decrements depending direction. Programmable position counting. Velocity capture using built-in timer. Velocity compare function with "less than" interrupt. Uses 32-bit registers position velocity. Three position compare registers with interrupts. Index counter revolution counting. Index compare register with interrupts. combine index position interrupts produce interrupt whole partial revolution displacement.
Digital filter with programmable delays encoder input signals. accept decoded signal inputs (clk direction). Connected APB. 7.25 Repetitive Interrupt (RI) timer
repetitive interrupt timer provides free-running 32-bit counter which compared selectable value, generating interrupt when match occurs. bits timer/compare masked such that they contribute match detection. repetitive interrupt timer used create interrupt that repeats predetermined intervals.
7.25.1 Features
32-bit counter running from PCLK. Counter free-running reset
generated interrupt.
32-bit compare value. 32-bit compare mask. interrupt generated when counter value equals
compare value, after masking. This allows combinations possible with simple compare.
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7.26 System tick timer
Cortex-M3 includes system tick timer (SYSTICK) that intended generate dedicated SYSTICK exception interval. LPC1766, this timer clocked from internal clock from device pin.
7.27 Watchdog timer
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
7.27.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) (Tcy(WDCLK) multiples Tcy(WDCLK) (IRC) peripheral clock. This gives wide range potential timing choices Watchdog operation under different power reduction conditions. also provides ability from entirely internal source that dependent external crystal associated components wiring increased reliability.
Watchdog Clock (WDCLK) source selected from Internal oscillator
Includes lock/safe feature. 7.28 backup registers
counters measuring time when system power optionally when off. LPC1766 designed have extremely power consumption, i.e. less than will typically from main chip power supply, conserving battery power while rest device powered When operating from battery, will continue working down Battery power provided from standard Lithium button cell. ultra-low power oscillator will provide clock time counting portion RTC, moving most power consumption time counting function. includes calibration mechanism allow fine-tuning count rate that will provide less than second error when operated constant voltage temperature. clock output function (see Section 7.29.4) makes measuring oscillator rate easy accurate. contains small backup registers bytes) holding data while main part LPC1766 powered off.
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includes alarm function that wake LPC1766 from reduced power modes with time resolution
7.28.1 Features
Measures passage time maintain calendar clock. Ultra power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
Dedicated power supply connected battery main Periodic interrupts generated from increments field time registers. Backup registers bytes) powered VBAT. power supply isolated from rest chip.
7.29 Clocking power control
7.29.1 Crystal oscillators
LPC1766 includes three independent oscillators. These Main Oscillator, Internal oscillator, oscillator. Each oscillator used more than purpose required particular application. three clock sources chosen software drive main ultimately CPU. Following reset, LPC1766 will operate from Internal oscillator until switched software. This allows systems operate without external crystal bootloader code operate known frequency. Figure overview LPC1766 clock generation.
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LPC17xx
MAIN OSCILLATOR
CLOCK DIVIDER pllclk system clock select (CLKSRCSEL)
usbclk MHz) BLOCK
MAIN
clock config enable (USBCLKCFG) CLOCK DIVIDER clock config (CCLKCFG)
cclk
main enable
CORTEX-M3
ETHERNET BLOCK GPIO NVIC
INTERNAL OSCILLATOR
WATCHDOG TIMER
CCLK/8 OSCILLATOR pclkWDT rtclk PERIPHERAL CLOCK GENERATOR REAL-TIME CLOCK CCLK/6 CCLK/4 CCLK/2 CCLK peripherals
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LPC1766 clocking generation block diagram
7.29.1.1
Internal oscillator used clock source WDT, and/or clock that drives subsequently CPU. nominal frequency MHz. trimmed accuracy over entire voltage temperature range. Upon power-up chip reset, LPC1766 uses clock source. Software later switch other available clock sources.
7.29.1.2
Main oscillator main oscillator used clock source CPU, with without using PLL. main oscillator also provides clock source dedicated PLL. main oscillator operates frequencies MHz. This frequency boosted higher frequency, maximum operating frequency, main PLL. clock selected input PLLCLKIN. processor clock frequency referred CCLK elsewhere this document. frequencies PLLCLKIN CCLK same value unless active connected. clock frequency each peripheral selected individually referred PCLK. Refer Section 7.29.2 additional information.
7.29.1.3
oscillator oscillator used clock source block, main PLL, and/or CPU.
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7.29.2 Main (PLL0)
PLL0 accepts input clock frequency range MHz. input frequency multiplied high frequency, then divided down provide actual clock used and/or block.
PLL0 input, range MHz, initially divided down value `N', which range 256. This input division provides wide range output frequencies from same input frequency.
Following PLL0 input divider PLL0 multiplier. This multiply input divider output through Current Controlled Oscillator (CCO) value `M', range through 32768. resulting frequency must range MHz. multiplier works dividing output value then using phase-frequency detector compare divided output multiplier input. error value used adjust frequency. PLL0 turned bypassed following chip Reset entering Power-down mode. PLL0 enabled software only. program must configure activate PLL0, wait PL0L lock, then connect PLL0 clock source.
7.29.3 (PLL1)
LPC1766 contains second, dedicated PLL1 provide clocking interface. PLL1 receives clock input from main oscillator only provides fixed clock block only. PLL1 disabled powered reset. PLL1 left disabled, clock will supplied clock from main PLL0. PLL1 accepts input clock frequency range only. input frequency multiplied range clock using Current Controlled Oscillators (CCO). insured that PLL1 output duty cycle.
7.29.4 clock output
LPC1766 features clock output function intended mainly during system development allow checking internal clocks CCLK, clock, main crystal, clock, clock outside world. clock output allows tuning frequency without probing pin, which would distort results.
7.29.5 Wake-up timer
LPC1766 begins operation power-up when awakened from Power-down mode using oscillator clock source. This allows chip operation resume quickly. main oscillator needed application, software will need enable these features wait them stabilize before they used clock source. When main oscillator initially activated, wake-up timer allows software ensure that main oscillator fully functional before processor uses clock source starts execute instructions. This important power types Reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes wake-up Timer.
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Wake-up Timer monitors crystal oscillator check whether safe begin code execution. When power applied chip, when some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate VDD(3V3) ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g., capacitors), characteristics oscillator itself under existing ambient conditions.
7.29.6 Power control
LPC1766 supports variety power control features. There four special modes processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, Deep power-down mode. clock rate also controlled needed changing clock sources, reconfiguring values, and/or altering clock divider value. This allows trade-off power versus processing speed based application requirements. addition, Peripheral Power Control allows shutting down clocks individual on-chip peripherals, allowing fine tuning power consumption eliminating dynamic power peripherals that required application. Each peripherals clock divider which provides even better power control. Integrated (Power Management Unit) automatically adjust internal regulators minimize power consumption during Sleep, Deep sleep, Power-down, Deep power-down modes. LPC1766 also implements separate power domain allow turning power bulk device while maintaining operation small registers storing data during power-down modes. 7.29.6.1 Sleep mode When Sleep mode entered, clock core stopped. Resumption from Sleep mode does need special sequence re-enabling clock core. Sleep mode, execution instructions suspended until either Reset interrupt occurs. Peripheral functions continue operation during Sleep mode generate interrupts cause processor resume execution. Sleep mode eliminates dynamic power used processor itself, memory systems related controllers, internal buses. 7.29.6.2 Deep-sleep mode Deep-sleep mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Deep-sleep mode logic levels chip pins remain static. output disabled powered down fast wake-up later. oscillator stopped because interrupts used wake-up source. automatically turned disconnected. CCLK clock dividers automatically reset zero. Deep-sleep mode terminated normal operation resumed either Reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Deep-sleep mode reduces chip power consumption very value. Power flash memory left Deep-sleep mode, allowing very quick wake-up.
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wake-up from Deep-sleep mode, code execution peripherals activities will resume after cycles expire used before entering Deep-sleep mode. main external oscillator used, code execution will resume when 4096 cycles expire. clock dividers need reconfigured accordingly.
7.29.6.3
Power-down mode Power-down mode does everything that Deep-sleep mode does, also turns power oscillator flash memory. This saves more power requires waiting resumption flash operation before execution code data access flash memory accomplished.
wake-up Power-down mode, used before entering Power-down mode, will take start-up. After this cycles will expire before code execution then resumed code running from SRAM. meantime, flash wake-up timer then counts clock cycles make flash start-up time. When times out, access flash will allowed. Users need reconfigure clock dividers accordingly. 7.29.6.4 Deep power-down mode Deep power-down mode only entered from block. Deep power-down mode, power shut entire chip with exception module RESET pin. LPC1766 wake from Deep power-down mode RESET alarm match event RTC. 7.29.6.5 Wakeup interrupt controller Wakeup Interrupt Controller (WIC) allows automatically wake from enabled priority interrupt that occur while clocks stopped Deep sleep, Power-down, Deep power-down modes. Wake-up controller (WIC) works connection with Nested Vectored Interrupt Controller (NVIC). When enters Deep sleep, Power-down, Deep power-down mode, NVIC sends mask current interrupt situation WIC.This mask includes interrupts that both enabled sufficient priority serviced immediately. With this information, simply notices when interrupts occurred then wakes CPU. Wake-up controller (WIC) eliminates need periodically wake poll interrupts resulting additional power savings.
7.29.7 Peripheral power control
Power Control Peripherals feature allows individual peripherals turned they needed application, resulting additional power savings.
7.29.8 Power domains
LPC1766 provides independent power domains that allow bulk device have power removed while maintaining operation backup Registers. LPC1766, pads powered (VDD(3V3)) pins, while VREG(3V3) powers on-chip voltage regulator which turn provides power most peripherals.
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Depending LPC1766 application, design power options manage power consumption.
first option assumes that power consumption concern design ties VDD(3V3) VREG(3V3) pins together. This approach requires only power supply both pads, CPU, peripherals. While this solution simple, does support powering down ring fly" while keeping peripherals alive.
second option uses power supplies; supply pads (VDD(3V3)) dedicated supply (VREG(3V3)). Having on-chip voltage regulator powered independently from ring enables shutting down power supply fly", while peripherals stay active. VBAT supplies power only domain. requires minimum power operate, which supplied external battery. Whenever device core power (VREG(3V3)) present, that power used operate RTC. Therefore, there power drain from battery when VREG(3V3) available.
LPC17xx
VDD(3V3) REGULATOR VREG(3V3) pads
core memories, peripherals, oscillators, PLLs
MAIN POWER DOMAIN
VBAT
POWER SELECTOR
ULTRA-LOW POWER REGULATOR BACKUP REGISTERS
RTCX1 RTCX2
OSCILLATOR
REAL-TIME CLOCK POWER DOMAIN
VDDA VREFP VREFN VSSA POWER DOMAIN
002aad978
Power distribution
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7.30 System control
7.30.1 Reset
Reset four sources LPC1766: RESET pin, Watchdog reset, power-on reset (POR), BrownOut Detection (BOD) circuit. RESET Schmitt trigger input pin. Assertion chip Reset source, once operating voltage attains usable level, starts Wake-up timer (see description Section 7.29.5), causing reset remain asserted until external Reset de-asserted, oscillator running, fixed number clocks have passed, flash controller completed initialization. When internal Reset removed, processor begins executing address which initially Reset vector mapped from Boot Block. that point, processor peripheral registers have been initialized predetermined values.
7.30.2 Brownout detection
LPC1766 includes 2-stage monitoring voltage VREG(3V3) pins. this voltage falls below 2.95 asserts interrupt signal Vectored Interrupt Controller. This signal enabled interrupt Interrupt Enable Register NVIC order cause interrupt; not, software monitor signal reading dedicated status register. second stage low-voltage detection asserts Reset inactivate LPC1766 when voltage VREG(3V3) pins falls below 2.65 This Reset prevents alteration flash operation various elements chip would otherwise become unreliable voltage. circuit maintains this reset down below which point power-on reset circuitry maintains overall Reset. Both 2.95 2.65 thresholds include some hysteresis. normal operation, this hysteresis allows 2.95 detection reliably interrupt, regularly executed event loop sense condition.
7.30.3 Code security (Code Read Protection CRP)
This feature LPC1766 allows user enable different levels security system that access on-chip flash JTAG restricted. When needed, invoked programming specific pattern into dedicated flash location. commands affected CRP. There three levels Code Read Protection. CRP1 disables access chip JTAG allows partial flash update (excluding flash sector using limited commands. This mode useful when required flash field updates needed sectors erased. CRP2 disables access chip JTAG only allows full flash erase update using reduced commands. Running application with level CRP3 selected fully disables access chip JTAG pins ISP. This mode effectively disables override using P2[10] pin, too. user's application provide needed) flash update mechanism using calls call reinvoke command enable flash update UART0.
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CAUTION
level three Code Read Protection (CRP3) selected, future factory testing performed device.
7.30.4 interface
peripherals split into separate buses order distribute bandwidth thereby reducing stalls caused contention between GPDMA controller.
7.30.5 multilayer matrix
LPC1766 uses multilayer matrix. This matrix connects instruction (I-code) data (D-code) buses Cortex-M3 flash memory, main (32KB) static RAM, Boot ROM. GPDMA also access these memories peripheral controllers (Ethernet USB). Additionally, matrix connects system controllers various peripheral functions.
7.30.6 External interrupt inputs
LPC1766 includes edge sensitive interrupt inputs combined with four level sensitive external interrupt inputs selectable functions. external interrupt inputs optionally used wake processor from Power-down mode.
7.30.7 Memory mapping control
Cortex-M3 incorporates mechanism that allows remapping interrupt vector table alternate locations memory map. This controlled Vector Table Offset Register contained NVIC. vector table located anywhere within bottom Cortex-M3 address space. vector table must located word (512 byte) boundary because NVIC LPC1766 configured total interrupts.
7.31 Emulation debugging
Debug trace functions integrated into Cortex-M3. Serial wire debug trace functions supported addition standard JTAG debug parallel trace functions. Cortex-M3 configured support eight breakpoints four watch points.
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Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(3V3) VREG(3V3) VDDA Vi(VBAT) Vi(VREFP) Parameter supply voltage (3.3 Voltage regulator supply voltage (3.3 analog supply voltage input voltage VBAT input voltage VREFP analog input voltage input voltage related pins tolerant pins; only valid when VDD(3V3) supply voltage present other pins Ilatch supply current ground current latch-up current supply ground -(0.5VDD(3V3)) (1.5VDD(3V3)); Tstg Ptot(pack) storage temperature total power dissipation (per package) based package heat transfer, device power consumption human body model; pins
Conditions core external rail
-0.5
+4.6 +4.6 +4.6 +5.1 +6.0
Unit
-0.5 -0.5 -0.5 -0.5
[2][3]
-0.5
VDD(3V3)
+150
Vesd
electrostatic discharge voltage
-2000
+2000
following applies limiting values: This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted.
Including voltage outputs 3-state mode. exceed peak current limited times corresponding maximum current. Dependent package type. Human body model: equivalent discharging capacitor through series resistor.
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Thermal characteristics
Thermal characteristics
average chip junction temperature, (°C), calculated using following equation:
ambient temperature (°C), package junction-to-ambient thermal resistance °C/W) internal power dissipation
internal power dissipation product VDD. power dissipation pins often small many times negligible. However significant some applications.
Table Thermal characteristics Tamb unless otherwise specified; Symbol TJ(MAX) Parameter thermal resistance maximum junction temperature Conditions LQFP100 package <tbd> Unit °C/W
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Static characteristics
Table Static characteristics Tamb industrial applications, unless otherwise specified. Symbol VDD(3V3) VREG(3V3) VDDA Vi(VBAT) Vi(VREFP) Parameter supply voltage (3.3 Voltage regulator supply voltage (3.3 analog supply voltage input voltage VBAT input voltage VREFP LOW-level input current on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current VDD(3V3)
Conditions core external rail
Typ[1]
VDDA
Unit
Standard port pins, RESET, RTCK
VDD(3V3); on-chip pull-down resistor disabled VDD(3V3); on-chip pull-up/down resistors disabled configured provide digital function output active
[3][4][5]
Vhys IOHS IOLS
VDD(3V3)
VDD(3V3)
HIGH-level short-circuit output current LOW-level short-circuit output current pull-down current pull-up current VDDA VDD(3V3)
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Table Static characteristics .continued Tamb industrial applications, unless otherwise specified. Symbol IREGact(3V3) Parameter Conditions Typ[1] active mode voltage VREG(3V3) regulator supply current Tamb code (3.3 while(1){} executed from flash; peripherals enabled; CCLK CCLK IREGsleep(3V3) sleep mode voltage VREG(3V3) regulator supply current Tamb (3.3 deep sleep mode VREG(3V3) voltage regulator supply Tamb current (3.3 power-down mode VREG(3V3) voltage regulator supply Tamb current (3.3 deep power-down mode voltage regulator supply current (3.3 active mode battery supply current; running pins (P0[27] P0[28]) HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS VDD(3V3) Oscillator pins Vi(XTAL1) Vo(XTAL2) Vi(RTCX1) Vo(RTCX2) input voltage XTAL1 output voltage XTAL2 input voltage RTCX1 output voltage RTCX2
Unit
<tbd> <tbd> <tbd>
IREGdsleep(3V3)
<tbd>
IREGpd(3V3)
<tbd>
IREGdpd(3V3)
VREG(3V3) Tamb VREG(3V3) present VREG(3V3) present
<tbd>
IBATact
I2C-bus Vhys
0.7VDD(3V3)
0.3VDD(3V3)
0.5VDD(3V3)
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Table Static characteristics .continued Tamb industrial applications, unless otherwise specified. Symbol pins VBUS Vth(rs)se OFF-state output current supply voltage differential input sensitivity voltage differential common mode voltage range single-ended receiver switching threshold voltage LOW-level output voltage low-/full-speed HIGH-level output voltage (driven) low-/full-speed |(D+) (D-)| includes range Parameter Conditions Typ[1]
5.25
Unit
0.18
Ctrans ZDRV
transceiver capacitance driver output with series resistor; impedance driver steady state drive which high-speed capable pull-up resistance SoftConnect
[10]
44.1
Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. typically fails when Vi(VBAT) drops below Including voltage outputs 3-state mode. VDD(3V3) supply voltages must present. 3-state outputs into 3-state mode when VDD(3V3) grounded. Accounts voltage drop supply lines. Allowed long current limit does exceed maximum current allowed device. VBAT. VSS.
[10] Includes external resistors
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10.1 Power consumption
IREGact (mA)
002aad951
core frequency (MHz)
Conditions: Tamb active mode entered executing code from flash; core voltage peripherals enabled configured run.
IREGact(3V3) different core frequencies (active mode)
IREGact (mA)
002aad950
core voltage
Conditions: Tamb active mode entered executing code from flash; peripherals enabled configured run.
IREGact(3V3) different core voltages VREG(3V3) (active mode)
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002aad952
IREGact (mA)
temperature (°C)
Conditions: active mode entered executing code from flash; core voltage peripherals enabled configured run.
IREGact(3V3) different temperatures (active mode)
IBATact
002aad953
VREG(3V3)
Conditions: active mode entered executing code from flash; Tamb running;
IBATact different core voltages (active mode)
Table Typical peripheral current consumption Core voltage Tamb measurements PCLK CCLK/8; peripherals enabled. Peripheral Timer0 Timer1 Timer2 Timer3
LPC1766_0.02
CCLK active mode <tbd> <tbd> <tbd> <tbd> sleep mode <tbd> <tbd> <tbd> <tbd>
CCLK active mode <tbd> <tbd> <tbd> <tbd> sleep mode <tbd> <tbd> <tbd> <tbd>
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Table Typical peripheral current consumption .continued Core voltage Tamb measurements PCLK CCLK/8; peripherals enabled.
Peripheral UART0 UART1 UART2 UART3 PWM1 Motor control Quadrature encoder I2C0-bus I2C1-bus I2C2-bus SSP0 SSP1 CAN1 CAN2 Ethernet
CCLK active mode <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> sleep mode <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd>
CCLK active mode <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd>
sleep mode
GPDMA controller <tbd>
Table Typical power consumption VBAT Tamb measurements clock VREG present. Power modes active IBAT <tbd> sleep <tbd> deep-sleep <tbd> power-down <tbd> deep power-down <tbd>
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10.2 Electrical characteristics
(mA)
002aad979
Measured pins Pn.m; VDD(3V3)
Typical LOW-level output IOLcurrent versus LOW-level output
(mA)
002aad980
Measured pins Pn.m; VDD(3V3)
Typical HIGH-level output current versus HIGH-level output voltage
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002aad981
-100
Measured pins Pn.m; VDD(3V3)
Typical pull-up current versus input voltage
002aad982
Measured pins Pn.m; VDD(3V3)
Typical pull-down current versus input voltage
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Dynamic characteristics
11.1 Flash memory
Table Flash characteristics Tamb commercial applications, unless otherwise specified. Symbol PECYC TRET TPROG TERASE Parameter number program/erase cycles data retention word program time page erase time global erase time Conditions <tbd> <tbd> <tbd> Typ[1] <tbd> <tbd> <tbd>
<tbd> <tbd> <tbd>
Unit years
11.2 External clock
Table Dynamic characteristic: external clock Tamb industrial applications; VDD(3V3) over specified ranges.[1] Symbol fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL
Parameter oscillator frequency clock cycle time clock HIGH time clock time clock rise time clock fall time
Conditions
Tcy(clk) Tcy(clk)
Typ[2]
1000
Unit
Parameters valid over operating temperature range unless otherwise specified. Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages.
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
External clock timing (with amplitude least Vi(RMS)
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11.3 Internal oscillator
Table Dynamic characteristic: internal oscillator Tamb industrial applications; VDD(3V3) over specified ranges.[1] Symbol fosc(IRC) fosc(RTC)
Parameter oscillator frequency oscillator frequency
Conditions
<tbd> <tbd>
Typ[2] <tbd> <tbd>
<tbd> <tbd>
Unit
Parameters valid over operating temperature range unless otherwise specified. Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages.
foscIRC (MHz)
002aad983
temperature (°C)
conditions: <tbd>
Internal oscillator frequency temperature
foscIRC (MHz)
002aad984
core coltage VREG(3V3)
conditions: <tbd>
Internal oscillator frequency core voltage
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11.4 JTAG interface
Table Dynamic characteristics JTAG clock source Tamb commercial applications; VDD(3V3) over specified ranges.[1] Symbol fTCK
Parameter input frequency
Conditions
CCLK/
Unit
Parameters valid over operating temperature range unless otherwise specified.
11.5 I2C-bus
Table Dynamic characteristic: I2C-bus pins Tamb industrial applications; VDD(3V3) over specified ranges.[1] Symbol I2C-bus tf(o) tBUF tLOW tHD;STA tHIGH tSU;DAT tSU;STA tSU;STO
Parameter pins (P0[27] P0[28]) output fall time rise time fall time free time between STOP START condition period clock hold time (repeated) START condition HIGH period clock data set-up time set-up time repeated START condition set-up time STOP condition
Conditions
Cb[3] <tbd> <tbd>
Typ[2] <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd>
<tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd>
Unit
<tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd>
Parameters valid over operating temperature range unless otherwise specified. Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. capacitance from
HD;STA
HD;STA HD;STA HIGH SU;DAT SU;STA SU;STO
002aad985
I2C-bus pins clock timing
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11.6 interface
Table Dynamic characteristic: interface Tamb industrial applications; VDD(3V3) over specified ranges.[1] Symbol interface tsu(SPI_MISO) SPI_MISO set-up time Tamb measured Master mode; Figure Parameter Conditions Typ[2]
Unit
Parameters valid over operating temperature range unless otherwise specified. Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages.
shifting edges
sampling edges
MOSI
MISO
tsu(SPI_MISO)
002aad326
MISO line set-up time Master mode
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11.7 interface
Table Dynamic characteristics: pins (full-speed) VDD(3V3), unless otherwise specified. Symbol tFRFM VCRS tFEOPT tFDEOP tJR1 tJR2 tEOPR1 Parameter rise time fall time differential rise fall time matching output signal crossover voltage source interval source jitter differential transition transition receiver jitter next transition receiver jitter paired transitions width receiver must reject EOP; Figure must accept EOP; Figure
Conditions
13.8 13.7 +18.5
Unit
Figure Figure
-18.5
tEOPR2
width receiver
Characterized implemented production test. Guaranteed design.
tPERIOD crossover point differential data lines
crossover point extended
source width: tFEOPT differential data SE0/EOP skew tPERIOD tFDEOP
receiver width: tEOPR1, tEOPR2
002aab561
Differential data-to-EOP transition skew width
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11.8
Table Dynamic characteristics pins Tamb industrial applications Symbol master TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPISEDV tSPIOH slave TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPISEDV tSPIOH cycle time SPICLK HIGH time SPICLK time data set-up time data hold time shifting edge output data valid time output data hold time <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> cycle time SPICLK HIGH time SPICLK time data set-up time data hold time shifting edge output data valid time output data hold time <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> Parameter
<tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd>
Unit
tSPICLK
tSPICLKH
tSPICLKL
(CPOL
(CPOL tSPISEDV MOSI DATA VALID DATA VALID tSPIDSU MISO DATA VALID tSPIDH tSPIOH
DATA VALID
002aad986
master timing (CPHA
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tSPICLK
tSPICLKH
tSPICLKL
(CPOL
(CPOL tSPISEDV MOSI DATA VALID DATA VALID tSPIDSU DATA VALID tSPIDH tSPIOH
MISO
DATA VALID
002aad987
master timing (CPHA
tSPICLK
tSPICLKH
tSPICLKL
(CPOL
(CPOL tSPIDSU MOSI DATA VALID tSPISEDV MISO DATA VALID DATA VALID tSPIDH
DATA VALID tSPIOH
002aad988
slave timing (CPHA
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tSPICLK
tSPICLKH
tSPICLKL
(CPOL
(CPOL tSPIDSU MOSI DATA VALID tSPISEDV MISO DATA VALID DATA VALID tSPIDH
DATA VALID tSPIOH
002aad989
slave timing (CPHA
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11.9 Ethernet
Table Dynamic characteristics: Ethernet pins Parameter cycle time MDIO write data valid time clock risetime high impedance (turn around) MDIO read data set-up time MDIO read data hold time receive data set-up time receive data hold time receive error set-up time receive error hold time carrier sense set-up time carrier sense hold time transmit enable valid delay time transmit enable hold time transmit data valid delay time transmit data hold time <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd>
Symbol tMDC td(MDIO) ttahz(MDIO) tsu(MDIO) th(MDIO) tsu(RXD) tih(RXD) tsu(RXER) tih(RXER) tsu(CRS) tih(CRS) td(TXEN) toh(TXEN) td(TXD) toh(TXD)
<tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd>
Unit
Ethernet signals MIIM
Ethernet signals RMII
tMDC
ENET_MDC
td(MDIO)
ENET_MDIO(O)
ttahz(MDIO) tsu(MDIO) th(MDIO)
ENET_MDIO
002aad990
Ethernet MIIM timing
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ENET_REF_CLK
td(x)
ENET_TX_EN ENET_TXD[1:0]
toh(x)
tsu(x)
ENET_CRS ENET_RXD[1:0] ENET_RX_ER
tih(x)
002aad991
Ethernet RMII timing
11.10 UART
Table Dynamic characteristics: UART pins Tamb industrial applications Symbol tUART td(UART) th(UART) tsu(D) th(D) Parameter serial port clock cycle time output data setup clock rising edge time output data hold after clock rising edge time data input set-up time data input hold time <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> Unit <tbd> <tbd> <tbd> <tbd> <tbd>
reference clock
td(XXX)
th(XXX)
output signal
tsu(D)
th(D)
input signal
002aad636
UART timing
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
11.11 I2S-interface
Table Dynamic characteristics: I2S-interface pins Tamb industrial applications Symbol Parameter cycle time rise time fall time pulse width HIGH pulse width <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd>
<tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd>
Unit <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd>
I2STX_SCK
I2STX_SDA
I2STX_WS
002aad992
I2S-bus timing (output)
I2SRX_SCK
I2SRX_SDA
tsu1
I2SRX_WS tsu2
002aad993
I2S-bus timing (input)
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
electrical characteristics
Table characteristics VDDA Tamb unless otherwise specified; frequency MHz. Symbol EL(adj) Rvsi SRin Tcy(ADC) tADC
Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error voltage source interface resistance input slew rate clock cycle conversion time
Conditions
[1][2][3] [1][4] [1][5] [1][6] [1][7]
<tbd> <tbd> <tbd>
VDDA <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd>
Unit V/ms
<tbd> <tbd> <tbd>
Conditions: VSSA VDDA monotonic, there missing codes. differential linearity error (ED) difference between actual step width ideal step width. Figure integral non-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure Figure
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
offset error 4095
gain error
4094
4093
4092
4091
4090
code
(ideal) 4090 4091 4092 4093 4094 4095 4096
offset error (LSBideal)
VDDA VSSA 4096
002aad948
Example actual transfer curve. ideal transfer curve. Differential linearity error (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
12-bit characteristics
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
LPC176X
AD0[y]SAMPLE
AD0[y]
Rvsi
VEXT
002aad949
Suggested interface LPC1766 AD0[y]
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
electrical characteristics
Table electrical characteristics VDDA Tamb unless otherwise specified; frequency <tbd> MHz. Symbol VDDA PSRR EL(adj) tS(FS) ts(SM) BW(3dB) settling time, full scale settling time, small change slew rate glitch energy, full scale 3-dB bandwidth Parameter analog supply voltage power supply rejection ratio output voltage differential linearity error integral non-linearity offset error gain error absolute error load capacitance output resistance VDDA 100mV count count <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> Conditions <tbd> <tbd> VDDA <tbd> <tbd>
<tbd> <tbd> VSSA ±0.5 <tbd> <tbd> <tbd> <tbd> <tbd> <tbd>
Unit V/ms nV.s
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Application information
14.1 Suggested interface solutions
VDD(3V3)
USB_UP_LED USB_CONNECT
LPC17xx
soft-connect switch
VBUS USB_D+ USB_D-
002aad939
USB-B connector
LPC1766 interface self-powered device
VDD(3V3)
LPC17xx
USB_UP_LED VBUS USB_D+ USB_D-
USB-B connector
002aad940
LPC1766 interface bus-powered device
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
RSTOUT
RESET_N ADR/PSW OE_N/INT_N SPEED SUSPEND
VBUS
Mini-AB connector
ISP1302
LPC17xx
USB_SCL USB_SDA EINTn USB_D+ USB_D-
INT_N
002aad941
LPC1766 port configuration
USB_UP_LED USB_D+ USB_D-
USB-A connector
LPC17xx
USB_PWRD USB_OVRCR USB_PPWR
VBUS
FLAGA
LM3526-L
OUTA
002aad942
LPC1766 host port configuration
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
USB_UP_LED
LPC17xx
USB_CONNECT
USB_D+ USB_D- VBUS
VBUS USB-B connector
002aad943
LPC1766 device port configuration
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Package outline
LQFP100: plastic profile quad flat package; leads; body
SOT407-1
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 14.1 13.9 0.75 0.45 0.08 0.08 1.15 0.85 1.15 0.85
16.25 16.25 15.75 15.75
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT407-1 REFERENCES 136E20 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-02-01 03-02-20
Package outline SOT407-1 (LQFP100)
LPC1766_0.02 B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Abbreviations
Table Acronym AMBA EGPIO IrDA JTAG MIIM RMII UART Abbreviations Description Analog-to-Digital Converter Advanced High-performance Advanced Microcontroller Architecture Advanced Peripheral BrownOut Detection Controller Area Network Digital-to-Analog Converter Debug Communication Channel Direct Memory Access Digital Signal Processing Packet Embedded Trace Macrocell General Purpose Input/Output Infrared Data Association Joint Test Action Group Media Independent Interface Management Physical Layer Phase-Locked Loop Pulse Width Modulator Reduced Media Independent Interface Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Revision history
Table Revision history Release date <tbd> Data sheet status Objective data sheet Change notice Document LPC1766_0.02 Modifications: LPC1766_0.01
Supersedes LPC1766_0.01
Updated Figure ISP1302. Removed Ethernet from block diagram (Figure Objective data sheet
20080727
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Legal information
18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
18.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
18.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected result personal injury, death severe property environmental
18.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark B.V. GoodLink trademark B.V. SoftConnect trademark B.V.
Contact information
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
LPC1766_0.02
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
Contents
General description Features Applications Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview Cortex-M3 processor On-chip flash program memory On-chip SRAM Memory Protection Unit (MPU). Memory map. Nested Vectored Interrupt Controller (NVIC) 7.7.1 Features 7.7.2 Interrupt sources. connect block General purpose controller 7.9.1 Features 7.10 Fast general purpose parallel 7.10.1 Features 7.11 Ethernet 7.11.1 Features 7.12 interface 7.12.1 device controller 7.12.1.1 Features 7.12.2 host controller. 7.12.2.1 Features 7.12.3 controller 7.12.3.1 Features 7.13 controller acceptance filters 7.13.1 Features 7.14 12-bit 7.14.1 Features 7.15 10-bit 7.15.1 Features 7.16 UARTs. 7.16.1 Features 7.17 serial controller. 7.17.1 Features 7.18 serial controller 7.18.1 Features 7.19 I2C-bus serial controllers. 7.19.1 Features 7.20 I2S-bus serial controllers. 7.20.1 Features 7.21 General purpose 32-bit timers/external event counters 7.21.1 Features 7.22 Pulse width modulator 7.22.1 Features
LPC1766_0.02
7.23 Motor control 7.24 Quadrature Encoder Interface (QEI) 7.24.1 Features. 7.25 Repetitive Interrupt (RI) timer. 7.25.1 Features. 7.26 System tick timer 7.27 Watchdog timer 7.27.1 Features. 7.28 backup registers 7.28.1 Features. 7.29 Clocking power control 7.29.1 Crystal oscillators 7.29.1.1 Internal oscillator 7.29.1.2 Main oscillator 7.29.1.3 oscillator 7.29.2 Main (PLL0) 7.29.3 (PLL1) 7.29.4 clock output 7.29.5 Wake-up timer 7.29.6 Power control 7.29.6.1 Sleep mode 7.29.6.2 Deep-sleep mode. 7.29.6.3 Power-down mode 7.29.6.4 Deep power-down mode 7.29.6.5 Wakeup interrupt controller 7.29.7 Peripheral power control 7.29.8 Power domains 7.30 System control 7.30.1 Reset 7.30.2 Brownout detection 7.30.3 Code security (Code Read Protection CRP) 7.30.4 interface 7.30.5 multilayer matrix 7.30.6 External interrupt inputs 7.30.7 Memory mapping control 7.31 Emulation debugging Limiting values Thermal characteristics Thermal characteristics Static characteristics 10.1 Power consumption 10.2 Electrical characteristics. Dynamic characteristics. 11.1 Flash memory 11.2 External clock. 11.3 Internal oscillator 11.4 JTAG interface 11.5 I2C-bus 11.6 interface 11.7 interface. 11.8 11.9 Ethernet 11.10 UART 11.11 I2S-interface electrical characteristics
B.V. 2008. rights reserved.
Objective data sheet
Rev. 00.02 August 2008
Semiconductors
LPC1766
Fast communication chip
14.1 18.1 18.2 18.3 18.4
electrical characteristics Application information. Suggested interface solutions Package outline Abbreviations Revision history Legal information. Data sheet status Definitions Disclaimers Trademarks. Contact information. Contents
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
B.V. 2008.
rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: August 2008 Document identifier: LPC1766_0.02

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