high performance Blackfin processor 16-bit MACs, 40-bit ALUs, four 8-b
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Blackfin® Embedded Processor
high performance Blackfin processor 16-bit MACs, 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register instruction model ease gramming compiler-friendly support Advanced debug, trace, performance monitoring 0.85 1.30 core with on-chip voltage regulation compliant 160-ball CSP_BGA, 169-ball PBGA, 176-lead LQFP packages External memory controller with glueless support SDRAM, SRAM, flash, Flexible memory booting options from SPI® external memory
PERIPHERALS
Parallel peripheral interface PPI/GPIO, supporting ITU-R video data formats dual-channel, full duplex synchronous serial ports, porting eight stereo channels Four memory-to-memory DMAs Eight peripheral DMAs SPI-compatible port Three 32-bit timer/counters with support Real-time clock watchdog timer 32-bit core timer general-purpose pins (GPIO) UART with support IrDA® Event handler Debug/JTAG interface On-chip capable frequency multiplication
MEMORY
148K bytes on-chip memory: bytes instruction SRAM/Cache bytes instruction SRAM to32K bytes data SRAM/Cache to32K bytes data SRAM bytes scratchpad SRAM Memory management unit providing memory protection
VOLTAGE REGULATOR
JTAG TEST EMULATION
INSTRUCTION MEMORY DATA MEMORY
INTERRUPT CONTROLLER
PERIPHERAL ACCESS
WATCHDOG TIMER
CONTROLLER
ACCESS
TIMER0-2 UART SPORT0-1
CORE EXTERNAL ACCESS
EXTERNAL
GPIO PORT
EXTERNAL PORT FLASH, SDRAM CONTROL BOOT
Figure Functional Block Diagram
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TABLE CONTENTS
General Description
Portable Power Architecture
System Integration
Processor
Peripherals
Blackfin Processor Core
Memory Architecture
Controllers
Real-Time Clock
Watchdog Timer
Timers
Serial Ports (SPORTs)
Serial Peripheral Interface (SPI) Port
UART Port
General-Purpose Port
Parallel Peripheral Interface
Dynamic Power Management
Voltage Regulation
Clock Signals
Booting Modes
Instruction Description
Development Tools
Designing Emulator-Compatible Processor Board
Related Documents
Descriptions
Specifications
Operating Conditions
Electrical Characteristics
Absolute Maximum Ratings
Package Information
Sensitivity
Timing Specifications
Clock Reset Timing
Asynchronous Memory Read Cycle Timing
Asynchronous Memory Write Cycle Timing
SDRAM Interface Timing
External Port Request Grant Cycle Timing
Parallel Peripheral Interface Timing
Serial Ports
Serial Peripheral Interface (SPI) Port
-Master Timing
Serial Peripheral Interface (SPI) Port
-Slave Timing
Universal Asynchronous Receiver-Transmitter
(UART) Port-Receive Transmit Timing
General-Purpose Port Cycle Timing
Timer Cycle Timing
JTAG Test Emulation Port Timing
Output Drive Currents
Power Dissipation
Test Conditions
Environmental Conditions
160-Ball Ball Assignment
169-Ball PBGA ball assignment
176-Lead LQFP Pinout
Outline Dimensions
Surface Mount Design
Ordering Guide
REVISION HISTORY
7/07-Revision Changed from Rev. Rev. Combined ADSP-BF531/532 ADSP-BF533
Data sheets into this Revision
Changed Features
Reformatted Processor Comparison
Rewrote General-Purpose Port
Rewrote Parallel Peripheral Interface
Rewrote Dynamic Power Management
Rewrote Voltage Regulation
Rewrote Clock Signals
Rewrote Booting Modes
Rewrote EZ-KIT Lite Evaluation Board
Reformatted Descriptions
Changed Operating Conditions
Changed Electrical Characteristics
Reformatted Timing Specifications
Added Figures Parallel Peripheral Interface Timing
Changed Serial Ports
Changed Ordering Guide
8/06-Revision Changed from Rev. Rev.
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GENERAL DESCRIPTION
processors members Blackfin family products, incorporating Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine dual-MAC state-of-the-art signal processing engine, advantages clean, orthogonal RISClike microprocessor instruction set, single instruction, tiple data (SIMD) multimedia capabilities into single instruction architecture. processors completely code pin-compatible, differing only with respect their performance on-chip memory. Specific perfor mance memory configurations shown Table Table Processor Comparison
ADSP-BF531 ADSP-BF532 ADSP-BF533
power consumption. Varying voltage frequency result substantial reduction power consumption, pared with just varying frequency operation. This translates into longer battery life portable appliances.
SYSTEM INTEGRATION
processors highly integrated system-on-a-chip solutions next gener ation digital communication consumer multimedia applications. combining industry-standard interfaces with high performance signal processing core, users develop cost-effective solutions quickly without need costly external components. system peripherals include UART port, port, serial ports (SPORTs), four general-pur pose timers (three with capability), real-time clock, watchdog timer, parallel peripheral interface.
Features SPORTs UART Timers Watchdog Timers Parallel Peripheral Interface GPIOs Instruction SRAM/Cache Instruction SRAM Data SRAM/Cache Data SRAM Scratchpad Boot Memory Configuration Maximum Speed Grade Package Options: CSP_BGA Plastic LQFP
PROCESSOR PERIPHERALS
processors tain rich peripherals connected core several high bandwidth buses, providing flexibility system configura tion well excellent overall system performance (see functional block diagram Figure Page generalpurpose peripherals include functions such UART, timers with (pulse-width modulation) pulse measurement capability, general-purpose pins, real-time clock, watchdog timer. This functions satisfies wide variety typical system support needs augmented system expansion capabilities part. addition these generalpurpose peripherals, ADSP-BF531/ADSP-BF532/ ADSP-BF533 processors contain high speed serial parallel ports interfacing variety audio, video, modem codec functions; interrupt controller flexible manage ment interrupts from on-chip peripherals external sources; power management control functions tailor performance power characteristics processor many application scenarios. peripherals, except general-purpose I/O, real-time clock, timers, supported flexible structure. There also separate memory channel dedicated data transfers between processor's various memory spaces, including external SDRAM asynchronous memory. Multi on-chip buses running provide enough bandwidth keep processor core running along with activ on-chip external peripherals. processors include on-chip voltage regulator support proces sor's dynamic power management capability. voltage regulator provides range core voltage levels from single 2.25 input. voltage regulator bypassed user's discretion.
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160-Ball 160-Ball 160-Ball 169-Ball 169-Ball 169-Ball 176-Lead 176-Lead 176-Lead
integrating rich industry-leading system peripherals memory, Blackfin processors platform choice next generation applications that require RISC-like program mability, multimedia support, leading-edge signal processing integrated package.
PORTABLE POWER ARCHITECTURE
Blackfin processors provide world-class power management performance. Blackfin processors designed power voltage design methodology feature dynamic power management-the ability vary both volt frequency operation significantly lower overall
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BLACKFIN PROCESSOR CORE
shown Figure Page Blackfin processor core contains 16-bit multipliers, 40-bit accumulators, 40-bit ALUs, four video ALUs, 40-bit shifter. compu tation units process 8-bit, 16-bit, 32-bit data from register file. compute register file contains eight 32-bit registers. When performing compute operations 16-bit operand data, register file operates independent 16-bit registers. operands compute operations come from multiported register file instruction constant fields. Each perform 16-bit 16-bit multiply each cycle, accumulating results into 40-bit accumulators. Signed unsigned formats, rounding, saturation supported. ALUs perform traditional arithmetic logical operations 16-bit 32-bit data. addition, many special instructions included accelerate various signal processing tasks. These include operations such field extract population count, modulo multiply, divide primitives, satu ration rounding, sign/exponent detection. video instructions includes byte alignment packing opera tions, 16-bit 8-bit adds with clipping, 8-bit average operations, 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided compare/select vector search instructions. certain instructions, 16-bit operations formed simultaneously register pairs 16-bit high half 16-bit half compute register). Quad 16-bit operations possible using second ALU. 40-bit shifter perform shifts rotates used support normalization, field extract, field deposit instructions. program sequencer controls flow instruction execu tion, including instruction alignment decoding. program flow control, sequencer supports relative indirect conditional jumps (with static branch prediction), subroutine calls. Hardware provided support zero-over head looping. architecture fully interlocked, meaning that programmer need manage pipeline when executing instructions with data dependencies. address arithmetic unit provides addresses simulta neous dual fetches from memory. contains multiported register file consisting four sets 32-bit index, modify, length, base registers (for circular buffering), eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support modified Harvard architecture combination with hierarchical memory structure. Level (L1) memories those that typically operate full processor speed with little latency. level, instruction memory holds instructions only. data memories hold data, dedicated scratchpad data memory stores stack local variable information. addition, multiple memory blocks provided, offering configurable SRAM cache. memory manage ment unit (MMU) provides memory protection individual tasks that operating core protect system registers from unintended access. architecture provides three modes operation: user mode, supervisor mode, emulation mode. User mode restricted access certain system resources, thus providing protected software environment, while supervisor mode unrestricted access system core resources. Blackfin processor instruction been optimized that 16-bit opcodes represent most frequently used instruc tions, resulting excellent compiled code density. Complex instructions encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support limited multi-issue capability, where 32-bit instruc tion issued parallel with 16-bit instructions, allowing programmer many core resources single instruction cycle. Blackfin processor assembly language uses algebraic ease coding readability. architecture been optimized conjunction with C/C++ compiler, resulting fast efficient software implementations.
MEMORY ARCHITECTURE
processors view memory single unified byte address space, using 32-bit addresses. resources, including internal memory, external memory, control registers, occupy separate sections this common address space. memory portions this address space arranged hierarchical structure provide good cost/performance balance some very fast, latency on-chip memory cache SRAM, larger, lower cost performance off-chip memory systems. Figure Page Figure Page Figure Page memory system primary highest performance memory available Blackfin processor. off-chip system, accessed through external interface unit (EBIU), provides expansion with SDRAM, flash memory, SRAM, optionally accessing 132M bytes physical memory. memory controller provides high bandwidth datamovement capability. perform block transfers code data between internal memory external memory spaces.
Internal (On-Chip) Memory
processor three blocks on-chip memory providing high bandwidth access core. first instruction memory, consisting bytes SRAM, which bytes configured four set-associative cache. This memory accessed full processor speed.
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ADDRESS ARITHMETIC UNIT
MEMORY
DAG1 DAG0
PREG
ASTAT
SEQUENCER R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L BARREL SHIFTER DECODE ALIGN
LOOP BUFFER
CONTROL UNIT
DATA ARITHMETIC UNIT
Figure Blackfin Processor Core
second on-chip memory block data memory, sisting banks bytes. memory banks configurable, offering both cache SRAM func tionality. This memory block accessed full processor speed. third memory block byte scratchpad SRAM which runs same speed memories, only accessible data SRAM cannot configured cache memory.
byte segment regardless size devices used, that these banks will only contiguous each fully popu lated with byte memory.
Memory Space
Blackfin processors define separate space. resources mapped through flat 32-bit address space. On-chip devices have their control registers mapped into memory mapped registers (MMRs) addresses near byte address space. These separated into smaller blocks, containing control MMRs core functions, other containing registers needed setup trol on-chip peripherals outside core. MMRs accessible only supervisor mode appear reserved space on-chip peripherals.
External (Off-Chip) Memory
External memory accessed external interface unit (EBIU). This 16-bit interface provides glueless connection bank synchronous DRAM (SDRAM) well four banks asynchronous memory devices including flash, EPROM, ROM, SRAM, memory mapped devices. PC133-compliant SDRAM controller programmed interface 128M bytes SDRAM. SDRAM troller allows open each internal SDRAM bank, four internal SDRAM banks, improving overall system performance. asynchronous memory controller programmed control four banks devices with very flexible timing parameters wide variety devices. Each bank occupies
Booting
processor tains small boot kernel, which configures appropriate peripheral booting. ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor configured boot from boot memory space, processor starts executing from on-chip boot ROM. more information, Booting Modes Page
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0xFFFF FFFF CORE REGISTERS BYTE) 0xFFE0 0000 SYSTEM REGISTERS BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM BYTE) 0xFFB0 0000 RESERVED
INTERNAL MEMORY
0xFFFF FFFF CORE REGISTERS BYTE) 0xFFE0 0000 SYSTEM REGISTERS BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM BYTE) RESERVED 0xFFA1 4000 INSTRUCTION SRAM/CACHE (16K BYTE) 0xFFA1 0000 INSTRUCTION SRAM (64K BYTE) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK SRAM/CACHE (16K BYTE) 0xFF90 4000 DATA BANK SRAM (16K BYTE) 0xFF90 0000 RESERVED 0xFF80 8000 RESERVED DATA BANK SRAM/CACHE (16K BYTE) 0xFF80 4000 DATA BANK SRAM/CACHE (16K BYTE) DATA BANK SRAM (16K BYTE) 0xFF80 0000 RESERVED RESERVED 0xEF00 0000
EXTERNAL MEMORY INTERNAL MEMORY EXTERNAL MEMORY
0xFFB0 0000
0xFFA1 4000 INSTRUCTION SRAM/CACHE (16K BYTE) 0xFFA1 0000 RESERVED 0xFFA0 C000 INSTRUCTION SRAM (16K BYTE) 0xFFA0 8000 RESERVED 0xFFA0 0000 RESERVED 0xFF90 8000 RESERVED 0xFF90 4000 0xFF80 8000 0xFF80 4000 0xEF00 0000 RESERVED 0x2040 0000 ASYNC MEMORY BANK BYTE) 0x2030 0000 ASYNC MEMORY BANK BYTE) 0x2020 0000 ASYNC MEMORY BANK BYTE) 0x2010 0000 ASYNC MEMORY BANK BYTE) 0x2000 0000 RESERVED 0x0800 0000 SDRAM MEMORY (16M BYTE 128M BYTE) 0x0000 0000
RESERVED 0x2040 0000 ASYNC MEMORY BANK BYTE) 0x2030 0000 ASYNC MEMORY BANK BYTE) 0x2020 0000 ASYNC MEMORY BANK BYTE) 0x2010 0000 ASYNC MEMORY BANK BYTE) 0x2000 0000 RESERVED 0x0800 0000 SDRAM MEMORY (16M BYTE 128M BYTE) 0x0000 0000
Figure ADSP-BF531 Internal/External Memory
0xFFFF FFFF CORE REGISTERS BYTE) 0xFFE0 0000 SYSTEM REGISTERS BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM BYTE) RESERVED 0xFFA1 4000 INSTRUCTION SRAM/CACHE (16K BYTE) 0xFFA1 0000 INSTRUCTION SRAM (32K BYTE) 0xFFA0 8000 RESERVED 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK SRAM/CACHE (16K BYTE) 0xFF90 4000 RESERVED 0xFF80 8000 DATA BANK SRAM/CACHE (16K BYTE) 0xFF80 4000 RESERVED 0xEF00 0000 0x2040 0000 ASYNC MEMORY BANK BYTE) 0x2030 0000 ASYNC MEMORY BANK BYTE) 0x2020 0000 ASYNC MEMORY BANK BYTE) 0x2010 0000 ASYNC MEMORY BANK BYTE) 0x2000 0000 RESERVED 0x0800 0000 SDRAM MEMORY (16M BYTE 128M BYTE) 0x0000 0000
EXTERNAL MEMORY INTERNAL MEMORY
Figure ADSP-BF533 Internal/External Memory
Event Handling
event controller ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor handles asynchronous synchro nous events processor. ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor provides event handling that supports both nesting prioritization. Nesting allows multiple event service routines active simultaneously. Prioritization ensures that servicing higher priority event takes prece dence over servicing lower priority event. controller provides support five different types events: Emulation emulation event causes processor enter emulation mode, allowing command control processor JTAG interface. Reset This event resets processor. Nonmaskable Interrupt (NMI) event generated software watchdog timer input signal processor. event frequently used power-down indicator initiate orderly shut down system. Exceptions Events that occur synchronously program flow (i.e., exception will taken before instruction allowed complete). Conditions such data alignment violations undefined instructions cause exceptions. Interrupts Events that occur asynchronously program flow. They caused input pins, timers, other peripherals, well explicit software instruction.
0xFFB0 0000
RESERVED
Figure ADSP-BF532 Internal/External Memory
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Each event type associated register hold return address associated return-from-event instruction. When event triggered, state processor saved supervisor stack. processor event controller consists stages, core event controller (CEC) system interrupt controller (SIC). core event troller works with system interrupt controller prioritize control system events. Conceptually, interrupts from peripherals enter into SIC, then routed directly into general-purpose interrupts CEC. Table System Interrupt Controller (SIC)
Peripheral Interrupt Event Wakeup Error Error SPORT Error SPORT Error Error UART Error Real-Time Clock Channel (PPI) Channel (SPORT Receive) Channel (SPORT Transmit) Channel (SPORT Receive) Channel (SPORT Transmit) Channel (SPI) Channel (UART Receive) Channel (UART Transmit) Timer Timer Timer Port GPIO Interrupt Port GPIO Interrupt Memory Stream Memory Stream Software Watchdog Timer Default Mapping IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG11 IVG11 IVG11 IVG12 IVG12 IVG13 IVG13 IVG13
Core Event Controller (CEC)
supports nine general-purpose interrupts (IVG15-7), addition dedicated interrupt exception events. these general-purpose interrupts, lowest priority inter rupts (IVG15-14) recommended reserved software interrupt handlers, leaving seven prioritized interrupt inputs support peripherals processor. Table describes inputs CEC, identifies their names event vector table (EVT), lists their priorities. Table Core Event Controller (CEC)
Priority Highest) Event Class Emulation/Test Control Reset Nonmaskable Interrupt Exception Reserved Hardware Error Core Timer General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt Entry IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
Event Control
processor vides user with very flexible mechanism control processing events. CEC, three registers used coordinate control events. Each register bits wide: interrupt latch register (ILAT) ILAT register indicates when events have been latched. appropriate when processor latched event cleared when event been accepted into system. This register updated automatically controller, also written clear (cancel) latched events. This register read while supervisor mode only written while supervisor mode when corre sponding IMASK cleared. interrupt mask register (IMASK) IMASK regis controls masking unmasking individual events. When IMASK register, that event unmasked will processed when asserted. cleared IMASK register masks event, preventing processor from servicing event even though event latched ILAT register. This register read written while supervisor mode.
System Interrupt Controller (SIC)
system interrupt controller provides mapping rout events from many peripheral interrupt sources prioritized general-purpose interrupt inputs CEC. Although proces provides default mapping, user alter mappings priorities interrupt events writing appropriate into interrupt assignment registers (SIC_IARx). Table describes inputs into default mappings into CEC.
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Note that general-purpose interrupts globally enabled disabled with instructions, respectively. interrupt pending register (IPEND) IPEND register keeps track nested events. IPEND register indicates event currently active nested some level. This register updated automatically controller read while supervisor mode. allows further control event processing providing three 32-bit interrupt control status registers. Each register contains corresponding each peripheral interrupt events shown Table interrupt mask register (SIC_IMASK) This register controls masking unmasking each peripheral interrupt event. When this register, that peripheral event unmasked will processed system when asserted. cleared this register masks peripheral event, preventing processor from servic event. interrupt status register (SIC_ISR) multiple peripherals mapped single event, this register allows software determine which peripheral event source triggered interrupt. indicates peripheral asserting interrupt, cleared indi cates peripheral asserting event. interrupt wakeup enable register (SIC_IWR) enabling corresponding this register, peripheral configured wake processor, should core idled when event generated. Dynamic Power Management Page Because multiple interrupt sources single generalpurpose interrupt, multiple pulse assertions occur simulta neously, before during interrupt processing interrupt event already detected this interrupt input. IPEND ister contents monitored interrupt acknowledgement. appropriate ILAT register when interrupt rising edge detected (detection requires core clock cycles). cleared when respective IPEND register set. IPEND indicates that event entered into proces pipeline. this point will recognize queue next rising edge event corresponding event input. minimum latency from rising edge transition generalpurpose interrupt IPEND output asserted three core clock cycles; however, latency much higher, depend activity within state processor. asynchronous memory controller. DMA-capable peripherals include SPORTs, port, UART, PPI. Each individual DMA-capable peripheral least dedicated channel. processor controller supports both 1-dimensional (1-D) 2-dimen sional (2-D) transfers. transfer initialization implemented from registers from sets parameters called descriptor blocks. capability supports arbitrary column sizes elements elements, arbitrary column step sizes ±32K elements. Furthermore, column step size less than step size, allowing implementation interleaved data streams. This feature especially useful video applications where data de-interleaved fly. Examples types supported ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor controller include: single, linear buffer that stops upon completion circular, autorefreshing buffer that interrupts each full fractionally full buffer using linked list descriptors using array descriptors, specifying only base address within common page addition dedicated peripheral channels, there pairs memory channels provided transfers between various memories ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor system. This enables transfers blocks data between memories- including external SDRAM, ROM, SRAM, flash memory- with minimal processor intervention. Memory transfers controlled very flexible descriptor-based methodol standard register-based autobuffer mechanism.
REAL-TIME CLOCK
processor real-time clock (RTC) provides robust digital watch features, including current time, stopwatch, alarm. clocked 32.768 crystal external processor. peripheral dedicated power supply pins that remain powered clocked even when rest cessor power state. provides several programmable interrupt options, including interrupt ond, minute, hour, clock ticks, interrupt programmable stopwatch countdown, interrupt grammed alarm time. 32.768 input clock frequency divided down signal prescaler. counter function timer consists four counters: second counter, minute counter, hour counter, 32,768 counter. When enabled, alarm function generates interrupt when output timer matches programmed value alarm control register. There alarms: first alarm time day. second alarm time that day.
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CONTROLLERS
processor multiple, independent channels that support automated data transfers with minimal overhead processor core. transfers occur between processor's internal memories DMA-capable peripherals. Addition ally, transfers accomplished between DMA-capable peripherals external devices connected external memory interfaces, including SDRAM controller
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stopwatch function counts down from programmed value, with second resolution. When stopwatch enabled counter underflows, interrupt generated. Like other peripherals, wake processor from sleep mode upon generation wakeup event. Additionally, wakeup event wake processor from deep sleep mode, wake on-chip internal voltage regulator from powered-down state. Connect pins RTXI RTXO with external components shown Figure
RTXI RTXO
clock timer, mechanism measuring pulse widths periods external events. These timers synchro nized external clock input (TACLK), external clock input PPI_CLK (TMRCLK), internal SCLK. timer units used conjunction with UART measure width pulses data stream provide autobaud detect function serial channel. timers generate interrupts processor core provid periodic events synchronization, either system clock count external signals. addition three general-purpose programmable timers, fourth timer also provided. This extra timer clocked internal processor clock typically used system tick clock generation operating system periodic interrupts.
SERIAL PORTS (SPORTs)
processor incor porates dual-channel synchronous serial ports (SPORT0 SPORT1) serial multiprocessor communications. SPORTs support following features: capable operation. Bidirectional operation Each SPORT sets inde pendent transmit receive pins, enabling eight channels stereo audio. Buffered (8-deep) transmit receive ports Each port data register transferring data words from other processor components shift registers shifting data data registers. Clocking Each transmit receive port either external serial clock generate own, frequencies ranging from (fSCLK/131,070) (fSCLK/2) Word length Each SPORT supports serial data words from bits bits length, transferred most-signifi cant-bit first least-significant-bit first. Framing Each transmit receive port with without frame sync signals each data word. Frame sync signals generated internally externally, active high low, with either pulse widths early late frame sync. Companding hardware Each SPORT perform A-law -law companding according recommen dation G.711. Companding selected transmit and/or receive channel SPORT without additional latencies. operations with single-cycle overhead Each SPORT automatically receive transmit multiple buffers memory data. processor link chain sequences transfers between SPORT memory.
SUGGESTED COMPONENTS: IPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 LOAD (SURFACE-MOUNT PACKAGE) 22pF 22pF NOTE: SPECIFIC CRYSTAL SPECIFIED CONTACT CRYSTAL MANUFACTURER DETAILS. SPECI FICATIO ASSUME BOARD TRACE CAPACITANCE 3pF.
Figure External Components
WATCHDOG TIMER
processor includes 32-bit timer that used implement software watchdog function. software watchdog improve system availability forcing processor known state through generation hardware reset, nonmaskable interrupt (NMI), general-purpose interrupt, timer expires before being reset software. programmer initializes count value timer, enables appropriate interrupt, then enables timer. Thereafter, software must reload counter before counts zero from programmed value. This protects system from remaining unknown state where software, which would normally reset timer, stopped running external noise condition software error. configured generate hardware reset, watchdog timer resets both core processor peripherals. After reset, software determine watchdog source hardware reset interrogating status watchdog timer control register. timer clocked system clock (SCLK), maximum frequency fSCLK.
TIMERS
There four general-purpose programmable timer units processor. Three timers have external that configured either pulse-width modulator (PWM) timer output, input
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Interrupts Each transmit receive port generates interrupt upon completing transfer data-word after transferring entire data buffer buffers through DMA. Multichannel capability Each SPORT supports chan nels 1,024-channel window compatible with H.100, H.110, MVIP-90, HMVIP standards. additional SPORT input hysteresis enabled setting PLL_CTL register. When this set, SPORT input pins have increased hysteresis. data from memory. UART dedicated channels, transmit receive. These channels have lower default priority than most channels because their relatively service rates. baud rate, serial data format, error code generation tus, interrupts UART port programmable. UART programmable features include: Supporting rates ranging from (fSCLK/1,048,576) bits second (fSCLK/16) bits second. Supporting data formats from seven bits bits
frame.
Both transmit receive operations configured generate maskable interrupts processor. UART port's clock rate calculated SCLK UART Clock Rate UART_Divisor Where 16-bit UART_Divisor comes from UART_DLH register (most significant bits) UART_DLL register (least significant bits). conjunction with general-purpose timer functions, autobaud detection supported. capabilities UART further extended with support Infrared Data Association (IrDA) serial infrared physical layer link specification (SIR) protocol.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
processor SPI-compatible port that enables processor communicate with multiple SPI-compatible devices. interface uses three pins transferring data: data pins (master output-slave input, MOSI, master input-slave output, MISO) clock (serial clock, SCK). chip select input (SPISS) lets other devices select proces sor, seven chip select output pins (SPISEL7-1) processor select other devices. select pins reconfigured general-purpose pins. Using these pins, port provides full-duplex, synchronous serial interface which ports both master/slave modes multimaster environments. baud rate clock phase/polarities port programmable, integrated controller, figurable support transmit receive data streams. controller only service unidirectional accesses given time. port clock rate calculated SCLK Clock Rate SPI_BAUD Where 16-bit SPI_BAUD register contains value 65,535. During transfers, port simultaneously transmits receives serially shifting data serial data lines. serial clock line synchronizes shifting pling data serial data lines.
GENERAL-PURPOSE PORT
processor bidirectional, general-purpose pins Port (PF15-0). Each general-purpose individually controlled manipulation GPIO control, status interrupt registers: GPIO direction control register Specifies direction each individual input output. GPIO control status registers ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor employs "write modify" mechanism that allows combination individual GPIO pins modified single instruction, without affecting level other GPIO pins. Four control registers provided. register written order GPIO values, register written order clear GPIO values, register written order toggle GPIO values, register written order specify GPIO values. Reading GPIO register allows software interrogate sense GPIO pin. GPIO interrupt mask registers GPIO interrupt mask registers allow each individual function interrupt processor. Similar GPIO trol registers that used clear individual GPIO values, GPIO interrupt mask register sets bits enable interrupt function, other GPIO interrupt mask register clears bits disable interrupt function.
UART PORT
processor vides full-duplex universal asynchronous receiver/transmitter (UART) port, which fully compatible with PC-standard UARTs. UART port provides simplified UART interface other peripherals hosts, supporting full-duplex, DMA-sup ported, asynchronous transfers serial data. UART port includes support data bits data bits, stop stop bits, none, even, parity. UART port supports modes operation: (programmed I/O) processor sends receives data writing reading I/O-mapped UART registers. data double-buffered both transmit receive. (direct memory access) controller trans fers both transmit receive data. This reduces number frequency interrupts required transfer
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pins defined inputs configured generate hard ware interrupts, while output pins triggered software interrupts. GPIO interrupt sensitivity registers GPIO inter rupt sensitivity registers specify whether individual pins level- edge-sensitive specify-if edge-sensi tive-whether just rising edge both rising falling edges signal significant. register selects type sensitivity, register selects which edges significant edge-sensitivity.
Frame Capture Mode
Frame capture mode allows video source(s) slave (e.g., frame capture). ADSP-BF531/ADSP-BF532/ ADSP-BF533 processors control when read from video source(s). PPI_FS1 HSYNC output PPI_FS2 VSYNC output.
Output Mode
Output mode used transmitting video other data with three output frame syncs. Typically, single frame sync appropriate data converter applications, whereas three frame syncs could used sending video with hard ware signaling.
PARALLEL PERIPHERAL INTERFACE
processor provides parallel peripheral interface (PPI) that connect directly parallel converters, video encoders decoders, other general-purpose peripherals. consists dedicated input clock pin, three frame synchronization pins, data pins. input clock supports parallel data rates half system clock rate synchronization signals configured either inputs outputs. supports variety general-purpose ITU-R modes operation. general-purpose mode, provides half-duplex, bi-directional data transfer with bits data. three frame synchronization signals also vided. ITU-R mode, provides half-duplex directional transfer 10-bit video data. Additionally, onchip decode embedded start-of-line (SOL) start-of-field (SOF) preamble packets supported.
ITU-R Mode Descriptions
ITU-R modes intended suit wide variety video capture, processing, transmission applica tions. Three distinct submodes supported: Active video only mode Vertical blanking only mode Entire field mode
Active Video Only Mode
Active video only mode used when only active video tion field interest blanking intervals. does read data between active video (EAV) start active video (SAV) preamble symbols, data present during vertical blanking intervals. this mode, control byte sequences stored memory; they filtered PPI. After synchronizing start Field ignores incoming samples until sees code. user specifies number active video lines frame PPI_COUNT register).
General-Purpose Mode Descriptions
general-purpose modes intended suit wide variety data capture transmission applications. Three distinct submodes supported: Input mode Frame syncs data inputs into PPI. Frame capture mode Frame syncs outputs from PPI, data inputs. Output mode Frame syncs data outputs from PPI.
Vertical Blanking Interval Mode
this mode, only transfers vertical blanking interval (VBI) data.
Entire Field Mode
this mode, entire incoming stream read through PPI. This includes active video, control preamble sequences, ancillary data that embedded horizontal tical blanking intervals. Data transfer starts immediately after synchronization Field Data transferred from synchronous channels through eight engines that work autonomously from processor core.
Input Mode
Input mode intended applications, well video communication with hardware signaling. simplest form, PPI_FS1 external frame sync input that controls when read data. PPI_DELAY allows delay PPI_CLK cycles) between reception this frame sync initiation data reads. number input data samples user programmable defined contents PPI_COUNT register. supports 8-bit 10-bit through 16-bit data, programmable PPI_CONTROL register.
DYNAMIC POWER MANAGEMENT
processor vides four operating modes, each with different performance/ power profile. addition, dynamic power management vides control functions dynamically alter processor core supply voltage, further reducing power dissipation. Control clocking each processor peripherals also reduces power consumption. Table summary power settings each mode.
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Full-On Operating Mode-Maximum Performance
full-on mode, enabled bypassed, providing capability maximum operational frequency. This power-up default execution state which maximum formance achieved. processor core enabled peripherals full speed. interrupt causes processor transition active mode. Assertion RESET while deep sleep mode causes proces transition full-on mode.
Hibernate State-Maximum Static Power Savings
hibernate state maximizes static power savings disabling voltage clocks processor core (CCLK) synchronous peripherals (SCLK). internal voltage regu lator processor shut writing b#00 FREQ bits VR_CTL register. addition disabling clocks, this sets internal power supply voltage (VDDINT) provide lowest static power dissipation. critical information stored internally (memory contents, register tents, etc.) must written nonvolatile storage device prior removing power processor state preserved. Since VDDEXT still supplied this mode, external pins three-state, unless otherwise specified. This allows other devices that connected processor still have power applied without drawing unwanted current. internal supply regulator woken either real-time clock wakeup asserting RESET pin.
Active Operating Mode-Moderate Power Savings
active mode, enabled bypassed. Because bypassed, processor's core clock (CCLK) system clock (SCLK) input clock (CLKIN) frequency. this mode, CLKIN CCLK multiplier ratio changed, although changes realized until full-on mode entered. access available appropriately configured memories. active mode, possible disable through control register (PLL_CTL). disabled, must re-enabled before transitioning full-on sleep modes. Table Power Settings
Mode Bypassed Full-On Enabled Active Enabled/ Disabled Sleep Enabled Deep Sleep Disabled Hibernate Disabled Core Clock (CCLK) Enabled Enabled System Clock Core (SCLK) Power Enabled Enabled
Power Savings
shown Table ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor supports three different power domains. multiple power domains maximizes flexi bility, while maintaining compliance with industry standards conventions. isolating internal logic processor into power domain, separate from other I/O, processor take advantage dynamic power agement without affecting other devices. There sequencing requirements various power domains. Table Power Domains
Power Domain internal logic, except internal logic crystal other Range VDDINT VDDRTC VDDEXT
Disabled Enabled Disabled Disabled Disabled Disabled
Sleep Operating Mode-High Dynamic Power Savings
sleep mode reduces dynamic power dissipation disabling clock processor core (CCLK). system clock (SCLK), however, continue operate this mode. Typi cally external event activity will wake processor. When sleep mode, assertion wakeup will cause processor sense value BYPASS control register (PLL_CTL). BYPASS disabled, cessor will transition full-on mode. BYPASS enabled, processor will transition active mode. When sleep mode, system access memory supported.
Deep Sleep Operating Mode-Maximum Dynamic Power Savings
deep sleep mode maximizes dynamic power savings abling clocks processor core (CCLK) synchronous peripherals (SCLK). Asynchronous peripherals, such RTC, still running will able access internal resources external memory. This powereddown mode only exited assertion reset interrupt (RESET) asynchronous interrupt generated RTC. When deep sleep mode, asynchronous
power dissipated processor largely function clock frequency processor square operating voltage. example, reducing clock frequency results reduction dynamic power dissipation, while reducing voltage reduces dynamic power dissipation more than 40%. Further, these power savings additive, that clock frequency supply voltage both reduced, power savings dramatic. dynamic power management feature ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor allows both proces sor's input voltage (VDDINT) clock frequency (fCCLK) dynamically controlled. savings power dissipation modeled using power savings factor power savings calculations.
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power savings factor calculated power savings factor CCLKRED DDINTRED CCLKNOM DDINTNOM where variables equation are: fCCLKNOM nominal core clock frequency fCCLKRED reduced core clock frequency VDDINTNOM nominal internal supply voltage VDDINTRED reduced internal supply voltage tNOM duration running fCCLKNOM tRED duration running fCCLKRED percent power savings calculated power savings power savings factor) 100%
Voltage Regulator Layout Guidelines
Regulator external component placement, board routing, bypass capacitors have significant effect noise injected into other analog circuits on-chip. VROUT1-0 traces voltage regulator external components should consid ered noise sources when doing board layout should routed placed near sensitive circuits components board. internal power supplies should well bypassed with bypass capacitors placed close processors possible. further details on-chip voltage regulator related board design guidelines, Switching Regulator Design Considerations ADSP-BF533 Blackfin Processors (EE-228) applications note Analog Devices site (www.ana log.com)-use site search "EE-228".
VOLTAGE REGULATION
Blackfin processor provides on-chip voltage regulator that generate appropriate VDDINT voltage levels from VDDEXT supply. Operating Conditions Page regula tolerances acceptable VDDEXT ranges specific models. Figure shows typical external components required complete power management system. regulator trols internal logic voltage levels programmable with voltage regulator control register (VR_CTL) increments reduce standby power consumption, internal voltage regulator programmed remove power processor core while keeping power (VDDEXT) supplied. While hibernate state, power still being applied, eliminat need external buffers. voltage regulator activated from this power-down state either through wakeup asserting RESET, both which will then initiate boot sequence. regulator also disabled bypassed user's discretion.
CLOCK SIGNALS
processor clocked external crystal, sine wave input, buffered, shaped clock derived from external clock oscillator. external clock used, should compatible signal must halted, changed, operated below speci fied frequency during normal operation. This signal connected processor's CLKIN pin. When external clock used, XTAL must left unconnected. Alternatively, because ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor includes on-chip oscillator circuit, external crystal used. fundamental frequency operation, circuit shown Figure
Blackfin CLKOUT CIRCUITRY
2.25V 3.6V INPUT VOLTAGE
RANGE
VDDEXT (LOW-INDUCTANCE)
DECOUPLING
CAPACITORS
100µF 100nF 100µF FDS9431A 10µF
100µF ZHCS1000 10µH
VDDEXT
CLKIN
XTAL OVERTONE OPERATION ONLY:
VDDINT
18pF*
18pF*
NOTE: VALUES MARKED WITH MUST CUSTOMIZED
DEPENDING CRYSTAL LAYOUT. PLEASE
ANALYZE CAREFULLY.
VROUT
Figure External Crystal Connections
SHORT LOWINDUCTANCE WIRE NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH FDS9431A.
VROUT
Figure Voltage Regulator Circuit
parallel-resonant, fundamental frequency, microprocessorgrade crystal connected across CLKIN XTAL pins. on-chip resistance between CLKIN XTAL range. Further parallel resistors typically ommended. capacitors series resistor shown Figure fine tune phase amplitude sine
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frequency. capacitor resistor values shown Figure typical values only. capacitor values dependent upon crystal manufacturer's load capacitance recommendations physical layout. resistor value depends drive level specified crystal manufacturer. System designs should verify customized values based careful investiga tion multiple devices over allowed temperature range. third-overtone crystal used frequencies above MHz. circuit then modified ensure crystal operation only third overtone, adding tuned inductor circuit shown Figure shown Figure core clock (CCLK) system peripheral clock (SCLK) derived from input clock (CLKIN) signal. on-chip capable multiplying CLKIN signal user programmable multiplica tion factor (bounded specified minimum maximum frequencies). default multiplier modified software instruction sequence. On-the-fly frequency changes effected simply writing PLL_DIV register.
ADJUSTMENT REQUI UENCING ARSE" ADJUSTMENT ON-THE-FLY
divisor register (PLL_DIV). When SSEL value changed, will affect peripherals that derive their clock signals from SCLK signal. core clock (CCLK) frequency also dynamically changed means CSEL1-0 bits PLL_DIV register. Supported CCLK divider ratios shown Table This programmable core clock capability useful fast core frequency modifications. Table Core Clock Ratios
Example Frequency Ratios (MHz) CCLK
Signal Name CSEL1-0
Divider Ratio VCO/CCLK
BOOTING MODES
processor mechanisms (listed Table automatically loading internal instruction memory after reset. third mode provided execute from external memory, bypassing boot sequence. Table Booting Modes
CLKIN
CCLK
SCLK
BMODE1-0
SCLK CCLK SCLK
Figure Frequency Modification Methods
on-chip peripherals clocked system clock (SCLK). system clock frequency programmable means SSEL3-0 bits PLL_DIV register. values programmed into SSEL fields define divide ratio between output (VCO) system clock. SCLK divider values through Table illustrates typical system clock ratios. Table Example System Clock Ratios
Example Frequency Ratios Divider Ratio (MHz) VCO/SCLK SCLK 10:1
Description Execute from 16-bit external memory (bypass boot ROM) Boot from 8-bit 16-bit FLASH Boot from serial master connected Boot from serial slave EEPROM /flash (8-,16-, 24-bit address range, Atmel AT45DB041, AT45DB081, AT45DB161serial flash)
BMODE pins reset configuration register, sampled during power-on resets software-initiated resets, imple ment following modes: Execute from 16-bit external memory Execution starts from address 0x2000 0000 with 16-bit packing. boot bypassed this mode. configuration settings slowest device possible (3-cycle hold time; 15-cycle access times; 4-cycle setup). Boot from 8-bit 16-bit external flash memory flash boot routine located boot memory space using asynchronous Memory Bank configuration tings slowest device possible (3-cycle hold time; 15-cycle access times; 4-cycle setup). Boot from serial EEPROM/flash (8-, 16-, 24-bit addressable, Atmel AT45DB041, AT45DB081, AT45DB161) uses output select single EEPROM/flash device, submits read command successive address bytes (0x00) until valid 16-,
Signal Name SSEL3-0 0001 0011 1010
maximum frequency system clock fSCLK. divisor ratio must chosen limit system clock frequency maximum fSCLK. SSEL value changed dynamically without lock latencies writing appropriate values
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24-bit addressable EEPROM/flash device detected, begins clocking data into processor beginning instruction memory. Boot from serial master Blackfin processor oper ates slave mode configured receive bytes file from host (master) agent. hold host device from transmitting while boot busy, Blackfin processor asserts GPIO pin, called host wait (HWAIT), signal host device send more bytes until flag deasserted. GPIO chosen user this information transferred Blackfin processor bits[10:5] FLAG header image. each boot modes, 10-byte header first read from external memory device. header specifies number bytes transferred memory destination address. Multiple memory blocks loaded boot sequence. Once blocks loaded, program execution commences from start instruction SRAM. addition, reset configuration register application code bypass normal boot sequence during software reset. this case, processor jumps directly beginning instruction memory. Microcontroller features, such arbitrary bit-field manipulation, insertion, extraction; integer operations 16-, 32-bit data types; separate user supervisor stack pointers. Code density enhancements, which include intermixing 16-bit 32-bit instructions mode switching, code segregation). Frequently used instructions encoded bits.
DEVELOPMENT TOOLS
processor ported complete CROSSCORE® software hardware development tools, including Analog Devices emula tors VisualDSP++® development environment. same emulator hardware that supports other Blackfin processors also fully emulates processor. VisualDSP++ project management environment lets grammers develop debug application. This environment includes easy assembler (which based alge braic syntax), archiver (librarian/library builder), linker, loader, cycle-accurate instruction level simulator, C/C++ compiler, C/C++ runtime library that includes mathematical functions. point these tools C/C++ code efficiency. compiler been developed efficient translation C/C++ code processor assembly. processor architectural features that improve efficiency piled C/C++ code. VisualDSP++ debugger number important tures. Data visualization enhanced plotting package that offers significant level flexibility. This graphical representa tion user data enables programmer quickly determine performance algorithm. algorithms grow plexity, this capability have increasing significance designer's development schedule, increasing productivity. Statistical profiling enables programmer nonintrusively poll processor running program. This feature, unique VisualDSP++, enables software developer sively gather important code execution metrics without interrupting real-time characteristics program. Essen tially, developer identify bottlenecks software quickly efficiently. using profiler, programmer focus those areas program that impact performance take corrective action. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information). Insert breakpoints. conditional breakpoints registers, memory,
stacks.
INSTRUCTION DESCRIPTION
Blackfin processor family assembly language instruction employs algebraic syntax designed ease coding readability. instructions have been specifically tuned vide flexible, densely encoded instruction that compiles very small final memory size. instruction also provides fully featured multifunction instructions that allow grammer many processor core resources single instruction. Coupled with many features more often seen microcontrollers, this instruction very efficient when piling source code. addition, architecture supports both user (algorithm/application code) supervisor (O/S kernel, device drivers, debuggers, ISRs) modes opera tion, allowing multiple levels access core processor resources. assembly language, which takes advantage proces sor's unique architecture, offers following advantages: Seamlessly integrated DSP/CPU features optimized both 8-bit 16-bit operations. multi-issue load/store modified Harvard architecture, which supports 16-bit four 8-bit load/store pointer updates cycle. registers, I/O, memory mapped into unified byte memory space, providing simplified program ming model.
CROSSCORE registered trademark Analog Devices, Inc. VisualDSP++ registered trademark Analog Devices, Inc.
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Trace instruction execution. Perform linear statistical profiling program execution. Fill, dump, graphically plot contents memory. Perform source level debugging. Create custom debugger windows. VisualDSP++ IDDE lets programmers define manage software development. dialog boxes property pages programmers configure manage Blackfin develop ment tools, including color syntax highlighting VisualDSP++ editor. This capability permits programmers Control development tools process inputs generate outputs Maintain one-to-one correspondence with tool's
command line switches
VisualDSP++ Kernel (VDK) incorporates scheduling resource management tailored specifically address timing constraints programming. These capabilities enable engineers develop code more effectively, eliminating need start from very beginning, when developing application code. features include threads, critical unscheduled regions, semaphores, events, device flags. also supports priority-based, emptive, cooperative, time-sliced scheduling approaches. addition, designed scalable. application does specific feature, support code that feature excluded from target system. Because library, developer decide whether not. integrated into VisualDSP++ development environment, also used standard command line tools. When used, development environment assists developer with many error prone tasks assists managing system resources, automating eration various VDK-based objects, visualizing system state, when debugging application that uses VDK. expert linker visually manipulate placement code data embedded system. View memory utiliza tion color coded graphical form, easily move code data different areas processor external memory with drag mouse, examine runtime stack heap usage. expert linker fully compatible with existing linker defini tion file (LDF), allowing developer move between graphical textual environments. Analog Devices emulators IEEE 1149.1 JTAG test access port processor monitor control target board processor during lation. emulator provides full speed emulation, allowing inspection modification memory, registers, proces stacks. Nonintrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting Blackfin processor family. Hardware tools include Blackfin processor plug-in cards. Third party software tools include libraries, real-time oper ating systems, block diagram design tools.
EZ-KIT Lite Evaluation Board
Analog Devices offers range EZ-KIT Lite® evaluation plat forms cost effective method learn more about developing prototyping applications with Analog Devices processors, platforms, software tools. Each EZ-KIT Lite includes evaluation board along with evaluation suite VisualDSP++ development debugging environment with C/C++ compiler, assembler, linker. Also included sample application programs, power supply, cable. evaluation versions software tools limited only with EZ-KIT Lite product. controller EZ-KIT Lite board connects board port user's enabling Visu alDSP++ evaluation suite emulate on-board processor incircuit. This permits customer download, execute, debug programs EZ-KIT Lite system. also allows incircuit programming on-board flash device store userspecific boot code, enabling board standalone unit without being connected With full version VisualDSP++ installed (sold separately), engineers develop software EZ-KIT Lite defined system. Connecting Analog Devices JTAG emulators EZ-KIT Lite board enables high speed, nonintrusive emulation. evaluation processors, EZ-KIT Lite board available from Analog Devices. Order part number ADDS-BF533-EZLITE. board comes with on-chip emulation capabilities equipped enable software development. Multiple daughter cards available.
DESIGNING EMULATOR-COMPATIBLE PROCESSOR BOARD
Analog Devices family emulators tools that every developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG test access port (TAP) each JTAG processor. emulator uses access internal features processor, allow developer load code, breakpoints, observe variables, observe memory, examine registers. proces must halted send data commands, once operation been completed emulator, processor system running full speed with impact system timing. these emulators, target board must include header that connects processor's JTAG port emulator.
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details target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, Analog Devices JTAG Emulation Technical Refer ence (EE-68) Analog Devices website (www.analog.com)-use site search "EE-68." This document updated regularly keep pace with improvements emula support.
RELATED DOCUMENTS
following publications that describe ADSP-BF531/ ADSP-BF532/ADSP-BF533 processors (and related processors) ordered from Analog Devices sales office accessed electronically website: Getting Started With Blackfin Processors ADSP-BF533 Blackfin Processor Hardware Reference ADSP-BF53x/BF56x Blackfin Processor Programming
Reference
ADSP-BF531 Blackfin Processor Anomaly List ADSP-BF532 Blackfin Processor Anomaly List ADSP-BF533 Blackfin Processor Anomaly List
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DESCRIPTIONS
processor defini tions listed Table pins three-stated during immediately after reset, except memory interface, asynchronous memory control, synchronous memory control pins, which driven high. active, then memory pins also three-stated. unused pins have their input buffers disabled with exception pins that need pull-ups pull-downs noted table footnotes. order maintain maximum functionality reduce pack size count, some pins have dual, multiplexed functionality. cases where functionality reconfigurable, default state shown plain text, while alternate function ality shown italics.
Table Descriptions
Name Memory Interface ADDR19-1 DATA15-0 ABE1-0/SDQM1-0 Asynchronous Memory Control AMS3-0 ARDY Synchronous Memory Control SRAS SCAS SCKE CLKOUT SA10 Timers TMR0 TMR1/PPI_FS1 TMR2/PPI_FS2 Port PPI3-0 PPI_CLK/TMRCLK PPI3-0 Clock/External Timer Reference Timer Timer 1/PPI Frame Sync1 Timer 2/PPI Frame Sync2 Address Strobe Column Address Strobe Write Enable Clock Enable Clock Output Bank Select Bank Select Hardware Ready Control (This should pulled HIGH used.) Output Enable Read Enable Write Enable Address Async/Sync Access Data Async/Sync Access Byte Enables/Data Masks Async/Sync Access Request (This should pulled HIGH used.) Grant Grant Hang Type Function Driver Type1
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Table Descriptions (Continued)
Name Port GPIO/Parallel Peripheral Interface Port/SPI/Timers PF0/SPISS PF1/SPISEL1/TACLK PF2/SPISEL2 PF3/SPISEL3/PPI_FS3 PF4/SPISEL4/PPI15 PF5/SPISEL5/PPI14 PF6/SPISEL6/PPI13 PF7/SPISEL7/PPI12 PF8/PPI11 PF9/PPI10 PF10/PPI9 PF11/PPI8 PF12/PPI7 PF13/PPI6 PF14/PPI5 PF15/PPI4 JTAG Port TRST Port MOSI MISO Serial Ports RSCLK0 RFS0 DR0PRI DR0SEC TSCLK0 TFS0 DT0PRI DT0SEC RSCLK1 SPORT0 Receive Serial Clock SPORT0 Receive Frame Sync SPORT0 Receive Data Primary SPORT0 Receive Data Secondary SPORT0 Transmit Serial Clock SPORT0 Transmit Frame Sync SPORT0 Transmit Data Primary SPORT0 Transmit Data Secondary SPORT1 Receive Serial Clock Master Slave Master Slave (This should pulled HIGH through resistor booting port.) Clock JTAG Clock JTAG Serial Data JTAG Serial Data JTAG Mode Select JTAG Reset (This should pulled JTAG used.) Emulation Output GPIO/SPI Slave Select Input GPIO/SPI Slave Select Enable 1/Timer Alternate Clock Input GPIO/SPI Slave Select Enable GPIO/SPI Slave Select Enable 3/PPI Frame Sync GPIO/SPI Slave Select Enable 4/PPI GPIO/SPI Slave Select Enable 5/PPI GPIO/SPI Slave Select Enable 6/PPI GPIO/SPI Slave Select Enable 7/PPI GPIO/PPI GPIO/PPI GPIO/PPI GPIO/PPI GPIO/PPI GPIO/PPI GPIO/PPI GPIO/PPI Type Function Driver Type1
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Table Descriptions (Continued)
Name RFS1 DR1PRI DR1SEC TSCLK1 TFS1 DT1PRI DT1SEC UART Port Real-Time Clock RTXI RTXO Clock CLKIN XTAL Mode Controls RESET BMODE1-0 Voltage Regulator VROUT1-0 Supplies VDDEXT VDDINT VDDRTC
Type Function SPORT1 Receive Frame Sync SPORT1 Receive Data Primary SPORT1 Receive Data Secondary SPORT1 Transmit Serial Clock SPORT1 Transmit Frame Sync SPORT1 Transmit Data Primary SPORT1 Transmit Data Secondary UART Receive UART Transmit Crystal Input (This should pulled when used.) Crystal Output Clock/Crystal Input (This needs level clocking.) Crystal Output Reset (This always active during core power-on.) Nonmaskable Interrupt (This should pulled when used.) Boot Mode Strap (These pins must pulled state required desired boot mode.) External Drive Power Supply Core Power Supply Real-Time Clock Power Supply External Ground
Driver Type1
Refer Figure Page Figure Page
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SPECIFICATIONS
Component specifications subject change without notice.
OPERATING CONDITIONS
Parameter VDDINT Internal Supply Voltage VDDINT Internal Supply Voltage VDDINT Internal Supply Voltage
Conditions Nonautomotive speed grade models Nonautomotive speed grade models speed grade models Automotive grade models2 Nonautomotive grade models2 Automotive grade models
Nominal 1.25 1.30 0.95
Unit 1.32 1.45 1.32 1.375
VDDINT Internal Supply Voltage1 VDDEXT External Supply Voltage VDDEXT External Supply Voltage VDDRTC Real-Time Clock Power Supply Voltage VDDRTC Real-Time Clock Power Supply Voltage
1.75 1.8/2.5/3.3 1.75 1.8/2.5/3.3 -0.3 -0.3
Nonautomotive grade models Automotive grade models2 VDDEXT =1.85 VDDEXT =Maximum VDDEXT =Maximum VDDEXT =1.75 VDDEXT =2.25
High Level Input Voltage3, High Level Input Voltage3,
VIHCLKIN High Level Input Voltage Level Input Voltage Level Input Voltage Junction Temperature Junction Temperature Junction Temperature Junction Temperature Junction Temperature Junction Temperature
+0.3 +0.6 +105 +125 +125 +105 +100
160-Ball Chip Scale Ball Grid Array (CSP_BGA) TAMBIENT +70°C 160-Ball Chip Scale Ball Grid Array (CSP_BGA) TAMBIENT -40°C +85°C 169-Ball Plastic Ball Grid Array (PBGA) TAMBIENT -40°C +105°C 169-Ball Plastic Ball Grid Array (PBGA) TAMBIENT -40°C +85°C 176-Lead Quad Flatpack (LQFP) TAMBIENT -40°C +85°C
160-Ball Chip Scale Ball Grid Array (CSP_BGA) TAMBIENT -40°C +105°C
regulator generate VDDINT levels 0.85 with +10% tolerance, 1.25 with-4% +10% tolerance, with +10% tolerance. Ordering Guide Page Applies input bidirectional pins except CLKIN. processors tolerant (always accepts maximum VIH), voltage compliance outputs, VOH) depends input VDDEXT, because (maximum) approximately equals VDDEXT (maximum). This tolerance applies bidirectional pins (DATA15-0, TMR2-0, PF15-0, PPI3-0, RSCLK1-0, TSCLK1-0, RFS1-0, TFS1-0, MOSI, MISO, SCK) input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, BMODE1-0). Applies CLKIN only.
Applies input bidirectional pins.
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ELECTRICAL CHARACTERISTICS
Power1 Parameter IIHP
High Speed2 10.0 50.0 10.0 10.0 10.0
Test Conditions High Level Output Voltage3 High Level Output Voltage High Level Output Voltage Level Output Voltage Level Output Voltage High Level Input Current4 High Level Input Current JTAG5 Level Input Current
Typical Typical Unit
VDDEXT 1.75 -0.5 VDDEXT 2.25 -0.5 VDDEXT -0.5 VDDEXT 1.75 VDDEXT 2.25 V/3.0 VDDEXT Maximum, Maximum VDDEXT Maximum, Maximum VDDEXT Maximum, VDDEXT Maximum, Maximum VDDEXT Maximum, MHz, TAMBIENT 25°C, VDDEXT 3.65 with voltage regulator (VDDINT VDDRTC TJUNCTION 25°C VDDINT TJUNCTION 25°C, SCLK
10.0 50.0 10.0 10.0 10.0 37.5
IOZH IOZL6 IDDHIBERNATE IDDRTC IDDDEEPSLEEP IDDSLEEP IDD_TYP10, IDD_TYP IDD_TYP IDD_TYP
Three-State Leakage Current Input Capacitance8
Three-State Leakage Current7 VDDINT Current Hibernate State VDDRTC Current
VDDINT Current Deep Sleep Mode VDDINT TJUNCTION 25°C VDDINT Current Sleep Mode VDDINT Current Dissipation (Typical) VDDINT fCCLK MHz, TJUNCTION 25°C VDDINT Current Dissipation (Typical) VDDINT 1.14 fCCLK MHz, TJUNCTION 25°C VDDINT Current Dissipation (Typical) VDDINT fCCLK MHz, TJUNCTION 25°C VDDINT Current Dissipation (Typical) VDDINT fCCLK MHz, TJUNCTION 25°C VDDINT Current Dissipation (Typical) VDDINT fCCLK MHz, TJUNCTION 25°C
IDD_TYP10,
Applies speed grade models. Ordering Guide Page
Applies MHz, MHz, speed grade models. Ordering Guide Page
Applies output bidirectional pins.
Applies input pins except JTAG inputs.
Applies JTAG input pins (TCK, TDI, TMS, TRST).
Absolute value.
Applies three-statable pins.
Applies signal pins.
Guaranteed, tested.
Estimating Power ADSP-BF531/BF532/BF533 Blackfin Processors (EE-229) Analog Devices website (www.analog.com)-use site search "EE-229."
Processor executing dual MAC, with moderate data activity.
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ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed table cause perma nent damage device. These stress ratings only. Functional operation device these other condi tions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Parameter Internal (Core) Supply Voltage (VDDINT) External (I/O) Supply Voltage (VDDEXT) Input Voltage1 Output Voltage Swing Load Capacitance2 Storage Temperature Range Junction Temperature Under Bias
PACKAGE INFORMATION
information presented Figure Table provides details about package branding Blackfin processors. complete listing product availability, Ordering Guide Page
Rating -0.3 -0.5 +3.8 -0.5 +3.8 -0.5 VDDEXT +0.5 +150°C 125°C
ADSP-BF53x tppZ-cc vvvvvv.x
yyww country_of_origin
Figure Product Information Package
Table Package Brand Information
Brand Field Description
Applies 100% transient duty cycle. other duty cycles Table proper SDRAM controller operation, maximum load capacitance ADDR19-1, DATA15-0, ABE1-0/SDQM1-0, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, SMS.
ADSP-BF53x Either ADSP-BF531, ADSP-BF532, ADSP-BF533 vvvvvv.x yyww Temperature Range Package Type RoHS Compliant Part Ordering Guide Assembly Code Silicon Revision Date Code
Table Maximum Duty Cycle Input Transient Voltage1
-0.50 -0.70 -0.80 -0.90 -1.00
(V)2 +3.80 +4.00 +4.10 +4.20 +4.30
Maximum Duty Cycle 100%
Applies signal pins with exception CLKIN, XTAL, VROUT1-0. Only listed options apply particular design.
SENSITIVITY
(electrostatic discharge) sensitive device. Charged devices circuit boards discharge without detection. Although this product features patented proprietary circuitry, damage occur devices subjected high energy ESD. Therefore, proper precautions should take avoid performance degradation loss functionality.
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TIMING SPECIFICATIONS
Table through Table describe timing requirements processor clocks. Take care selecting MSEL, SSEL, CSEL ratios exceed maximum core clock system clock described Table Core Clock (CCLK) Requirements-400 Models1
TJUNCTION 125°C All2 Other TJUNCTION
Absolute Maximum Ratings Page voltage trolled oscillator (VCO) operating frequencies described Table Table describes phase-locked loop operating conditions.
Parameter fCCLK CCLK Frequency (VDDINT =1.14 Minimum) fCCLK CCLK Frequency (VDDINT =1.045 Minimum) fCCLK CCLK Frequency (VDDINT =0.95 Minimum) fCCLK CCLK Frequency (VDDINT =0.85 Minimum) fCCLK CCLK Frequency (VDDINT =0.8 Minimum)
Internal Regulator Setting 1.20 1.10 1.00 0.90 0.85
Unit
Ordering Guide Page Operating Conditions Page
Table Core Clock (CCLK) Requirements-500 MHz, MHz, Models
Parameter fCCLK CCLK Frequency (VDDINT =1.3 Minimum)1 fCCLK CCLK Frequency (VDDINT =1.2 Minimum)2 CCLK Frequency (VDDINT =1.14 Minimum)3 fCCLK fCCLK CCLK Frequency (VDDINT =1.045 Minimum) fCCLK CCLK Frequency (VDDINT =0.95 Minimum) fCCLK CCLK Frequency (VDDINT =0.85 Minimum) fCCLK CCLK Frequency (VDDINT =0.8 Minimum)
Internal Regulator Setting 1.30 1.25 1.20 1.10 1.00 0.90 0.85
Unit
Applies models only. Ordering Guide Page
Applies models only. Ordering Guide Page models cannot support internal regulator levels above 1.25
Applies MHz, MHz, models. Ordering Guide Page models cannot support internal regulator levels above 1.20
Table Phase-Locked Loop Operating Conditions
Parameter fVCO Voltage Controlled Oscillator (VCO) Frequency Maximum fCCLK Unit
Table System Clock (SCLK) Requirements
Parameter1 MBGA/PBGA fSCLK fSCLK LQFP fSCLK fSCLK
VDDEXT CLKOUT/SCLK Frequency (VDDINT 1.14 CLKOUT/SCLK Frequency (VDDINT 1.14 CLKOUT/SCLK Frequency (VDDINT 1.14 CLKOUT/SCLK Frequency (VDDINT 1.14
VDDEXT V/3.3
Unit
tSCLK 1/fSCLK) must greater than equal tCCLK.
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Clock Reset Timing
Table Figure describe clock reset operations. Absolute Maximum Ratings Page combinations CLKIN clock multipliers/divisors must result core/ Table Clock Reset Timing
Parameter Timing Requirements tCKIN CLKIN Period1, tCKINL CLKIN Pulse tCKINH CLKIN High Pulse tWRST RESET Asserted Pulse Width Low5
system clocks exceeding maximum limits allowed processor, including system clock restrictions related supply voltage.
25.0 10.0 10.0 tCKIN
100.0
Unit
Applies bypass mode nonbypass mode. CLKIN frequency must change fly. Combinations CLKIN frequency clock multiplier must exceed allowed fVCO, fCCLK, fSCLK settings discussed Table Page through Table Page Since default behavior multiply CLKIN frequency speed grade parts cannot full CLKIN period range. PLL_CTL register set, then maximum tCKIN period Applies after power-up sequence complete. power-up, processor's internal phase-locked loop requires more than 2,000 CLKIN cycles, while RESET asserted, assuming stable power supplies CLKIN (not including start-up time external clock oscillator).
tCKIN
CLKIN
tCKINL
RESET
tCKINH tWRST
Figure Clock Reset Timing
Rev.
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July 2007
Asynchronous Memory Read Cycle Timing
Table Asynchronous Memory Read Cycle Timing
VDDEXT VDDEXT V/3.3 Unit
Parameter Timing Requirements tSDAT DATA15-0 Setup Before CLKOUT tHDAT DATA15-0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics Output Delay After CLKOUT1 Output Hold After CLKOUT
Output pins include AMS3-0, ABE1-0, ADDR19-1, DATA15-0, AOE, ARE.
HOLD CYCLE
SETUP CYCLES
PROGRAMMED READ ACCESS CYCLES
ACCESS EXTENDED CYCLES
CLKOUT
AMSx
ABE1-0 ADDR19-1
ABE, ADDRESS
SARDY
ARDY
HARDY
tHARDY
SARDY
SDAT tHDAT
DATA15-0
READ
Figure Asynchronous Memory Read Cycle Timing
Rev.
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July 2007
Asynchronous Memory Write Cycle Timing
Table Asynchronous Memory Write Cycle Timing
VDDEXT VDDEXT V/3.3 Unit
Parameter Timing Requirements tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDDAT DATA15-0 Disable After CLKOUT tENDAT DATA15-0 Enable After CLKOUT Output Delay After CLKOUT1 Output Hold After CLKOUT
Output pins include AMS3-0, ABE1-0, ADDR19-1, DATA15-0, AOE, AWE.
ACCESS EXTENDED CYCLE
SETUP CYCLES
PROGRAMMED WRITE ACCESS CYCLES
HOLD CYCLE
CLKOUT
AMSx
ABE1-0 ADDR19-1
ABE, ADDRESS
SARDY
ARDY
HARDY
ENDAT
DATA15-0 WRITE DATA
tSARDY
Figure Asynchronous Memory Write Cycle Timing
Rev.
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July 2007
SDRAM Interface Timing
Table SDRAM Interface Timing1
VDDEXT 10.0 VDDEXT V/3.3 Unit
Parameter Timing Requirements tSSDAT DATA Setup Before CLKOUT tHSDAT DATA Hold After CLKOUT Switching Characteristics tSCLK CLKOUT Period2 tSCLKH CLKOUT Width High CLKOUT Width tSCLKL tDCAD Command, ADDR, Data Delay After CLKOUT3 tHCAD Command, ADDR, Data Hold After CLKOUT1 tDSDAT Data Disable After CLKOUT tENSDAT Data Enable After CLKOUT
SDRAM timing TJUNCTION 125°C limited MHz.
Refer Table Page maximum fSCLK various VDDINT.
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
tSCLK
CLKOUT
tSCLKH
tSSDAT SDAT
DATA(IN)
tSCLKL
tENSDAT
DATA(OUT)
tDSDAT tHCAD
tDCAD
CMND ADDR (OUT)
tHCAD
NOTE: COMMAND SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure SDRAM Interface Timing
Rev.
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External Port Request Grant Cycle Timing
Table Figure describe external port request grant operations. Table External Port Request Grant Cycle Timing
VDDEXT VDDEXT VDDEXT V/3.3 LQFP/PBGA Packages MBGA Package Packages Unit
Parameter Timing Requirements Asserted CLKOUT High Setup CLKOUT High Deasserted Hold Time Switching Characteristics CLKOUT AMSx, Address, ARE/AWE Disable CLKOUT AMSx, Address, ARE/AWE Enable tDBG CLKOUT High High Setup tEBG CLKOUT High Deasserted Hold Time tDBH CLKOUT High High Setup tEBH CLKOUT High Deasserted Hold Time
CLKOUT
AMSx
ADDR19-1 ABE1-0
tDBG
tEBG
tDBH
tEBH
Figure External Port Request Grant Cycle Timing
Rev.
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Parallel Peripheral Interface Timing
Table Figure through Figure Page describe parallel peripheral interface operations. Table Parallel Peripheral Interface Timing
VDDEXT LQFP/PBGA Packages 20.0 1.02 2.03 11.0 11.0 VDDEXT MBGA Package 20.0 1.02 2.03 VDDEXT V/3.3 Packages Unit 15.0 4.02 6.03 1.02 2.03
Parameter Timing Requirements tPCLKW PPI_CLK Width tPCLK PPI_CLK Period1 tSFSPE External Frame Sync Setup Before PPI_CLK Edge (Nonsampling Edge Sampling Edge tHFSPE External Frame Sync Hold After PPI_CLK
tSDRPE Receive Data Setup Before PPI_CLK tHDRPE Receive Data Hold After PPI_CLK Switching Characteristics-GP Output Frame Capture Modes tDFSPE Internal Frame Sync Delay After PPI_CLK tHOFSPE Internal Frame Sync Hold After PPI_CLK tDDTPE Transmit Data Delay After PPI_CLK tHDTPE Transmit Data Hold After PPI_CLK
PPI_CLK frequency cannot exceed fSCLK/2
Applies when PPI_CONTROL cleared. Figure Page Figure Page
Applies when PPI_CONTROL set. Figure Page Figure Page
FRAME SYNC DRIVEN POLC PPI_CLK
DATA0 SAMPLED
PPI_CLK POLC tDFSPE POLS PPI_FS1 POLS
HOFSPE
POLS PPI_FS2 POLS tSDRPE tHDRPE
PPI_DATA
Figure Mode with Internal Frame Sync Timing
Rev.
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FRAME SYNC SAMPLED DATA0
DATA0 SAMPLED PPI_CLK POLC PPI_CLK POLC
DATA1 SAMPLED
tSFSPE POLS PPI_FS1 POLS
HFSPE
POLS PPI_FS2 POLS
SDRPE
HDRPE
PPI_DATA
Figure Mode with External Frame Sync Timing
DATA SAMPLING/ FRAME SYNC SAMPLING EDGE PPI_CLK POLC PPI_CLK POLC
DATA SAMPLING/ FRAME SYNC SAMPLING EDGE
POLS PPI_FS1 POLS
SFSPE
HFSPE
POLS PPI_FS2 POLS PPI_DATA
SDRPE
HDRPE
Figure Mode with External Frame Sync Timing (Bit PPI_CONTROL Set)
Rev.
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FRAME SYNC DRIVEN
DATA0 DRIVEN
PPI_CLK POLC PPI_CLK POLC tHOFSPE POLS PPI_FS1 POLS
DFSPE
POLS PPI_FS2 POLS
DDTPE
HDTPE
PPI_DATA
DATA0
Figure Mode with Internal Frame Sync Timing
FRAME SYNC SAMPLED PPI_CLK POLC PPI_CLK POLC tHFSPE tSFSPE POLS PPI_FS1 POLS
DATA0
DRIVEN
POLS PPI_FS2 POLS tHDTPE
PPI_DATA
DATA0
DDTPE
Figure Mode with External Frame Sync Timing
Rev.
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DATA DRIVING/ FRAME SYNC SAMPLING EDGE PPI_CLK POLC PPI_CLK POLC POLS PPI_FS1 POLS
SFSPE HFSPE
DATA DRIVING/ FRAME SYNC SAMPLING EDGE
POLS PPI_FS2 POLS tDDTPE PPI_DATA
HDTPE
Figure Mode with External Frame Sync Timing (Bit PPI_CONTROL Set)
Rev.
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Serial Ports
Table through Table Page Figure Page through Figure Page describe Serial Port operations. Table Serial Ports-External Clock
VDDEXT 20.0 10.0 10.0 10.0 VDDEXT V/3.3 Unit 15.02 10.0
Parameter Timing Requirements tSFSE TFSx/RFSx Setup Before TSCLKx/RSCLKx1 tHFSE TFSx/RFSx Hold After TSCLKx/RSCLKx1 tSDRE Receive Data Setup Before RSCLKx1 tHDRE Receive Data Hold After RSCLKx1 tSCLKEW TSCLKx/RSCLKx Width tSCLKE TSCLKx/RSCLKx Period Switching Characteristics tDFSE TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)3 tHOFSE TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1 tDDTE Transmit Data Delay After TSCLKx1 tHDTE Transmit Data Hold After TSCLKx1
Referenced sample edge.
receive mode with external RSCLKx external RFSx only, maximum specification 11.11 MHz).
Referenced drive edge.
Table Serial Ports-Internal Clock
VDDEXT VDDEXT VDDEXT V/3.3 LQFP/PBGA MBGA Package Packages Packages Unit 11.0 -2.0 15.0 -1.0 -2.0 -2.0 -1.0 -2.0 15.0
Parameter Timing Requirements tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx1 11.0 tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx1 -2.0 tSDRI Receive Data Setup Before RSCLKx1 tHDRI Receive Data Hold After RSCLKx tSCLKEW TSCLKx/RSCLKx Width tSCLKE TSCLKx/RSCLKx Period 20.0 Switching Characteristics tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1 -1.0 tDDTI Transmit Data Delay After TSCLKx1 tHDTI Transmit Data Hold After TSCLKx1 -2.5 tSCLKIW TSCLKx/RSCLKx Width
Referenced sample edge. Referenced drive edge.
Rev.
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DATA RECEIVE-INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA RECEIVE-EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
RSCLKx RSCLKx
tSCLKEW
tDFSI tHOFSI
RFSx
tDFSE tSFSI tHFSI
RFSx
tHOFSE
tSFSE
tHFSE
tSDRI
tHDRI
tSDRE
tHDRE
NOTE: EITHER RISING EDGE FALLING EDGE RSCLKx TSCLKx USED ACTIVE SAMPLING EDGE. DATA TRANSMIT-INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA TRANSMIT-EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
TSCLKx TSCLKx
tSCLKEW
tDFSI tHOFSI
TFSx
tDFSE tSFSI tHFSI
TFSx
tHOFSE
tSFSE
tHFSE
tDDTI tHDTI
tDDTE tHDTE
NOTE: EITHER RISING EDGE FALLING EDGE RSCLKx TSCLKx USED ACTIVE SAMPLING EDGE.
Figure Serial Ports
Table Serial Ports-Enable Three-State
VDDEXT VDDEXT V/3.3 Unit 10.0 -2.0 -2.0 10.0
Parameter Switching Characteristics tDTENE Data Enable Delay from External TSCLKx1 tDDTTE Data Disable Delay from External TSCLKx1 tDTENI Data Enable Delay from Internal TSCLKx1 tDDTTI Data Disable Delay from Internal TSCLKx1
Referenced drive edge.
Table External Late Frame Sync
VDDEXT VDDEXT LQFP/PBGA Packages MBGA Package 10.5 10.0 VDDEXT V/3.3 Packages 10.0
Parameter Switching Characteristics tDDTLFSE Data Delay from Late External TFSx External RFSx with tDTENLFS Data Enable from Late
Unit
TFSx enable TFSx valid follow tDTENLFS tDDTLFSE.
external RFSx/TFSx setup RSCLKx/TSCLK tSCLKE/2, then tDDTTE/I tDTENE/I apply; otherwise tDDTLFSE tDTENLFS apply.
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EXTERNAL RFSx WITH DRIVE RSCLKx SAMPLE DRIVE
tSFSE/I
tHOFSE/I
RFSx
tDTENLFS
tDDTTE/I tDTENE/I
tDDTLFSE
LATE EXTERNAL TFSx DRIVE TSCLKx SAMPLE DRIVE
tSFSE/I
tHOFSE/I
TFSx
tDTENLFS
tDDTTE/I tDTENE/I
tDDTLFSE
Figure External Late Frame Sync
Rev.
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Serial Peripheral Interface (SPI) Port -Master Timing
Table Figure describe port master operations. Table Serial Peripheral Interface (SPI) Port-Master Timing
VDDEXT VDDEXT LQFP/PBGA Packages MBGA Package -1.5 2tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 4tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 -1.0 VDDEXT V/3.3 Packages -1.5 2tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 4tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 -1.0
Parameter Timing Requirements tSSPIDM Data Input Valid Edge (Data Input Setup) 10.5 tHSPIDM Sampling Edge Data Input Invalid -1.5 Switching Characteristics tSDSCIM SPISELx First Edge 2tSCLK -1.5 tSPICHM Serial Clock High Period 2tSCLK -1.5 tSPICLM Serial Clock Period 2tSCLK -1.5 tSPICLK Serial Clock Period 4tSCLK -1.5 tHDSM Last Edge SPISELx High 2tSCLK -1.5 tSPITDM Sequential Transfer Delay 2tSCLK -1.5 tDDSPIDM Edge Data Valid (Data Delay) tHDSPIDM Edge Data Invalid (Data Hold) -1.0
SPISELx (OUTPUT)
Unit
+4.0
+4.0
+4.0
tSDSCIM
(CPOL (OUTPUT)
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tSPICLM
(CPOL (OUTPUT)
tSPICHM
tDDSPIDM
MOSI (OUTPUT) CPHA MISO (INPUT)
tHDSPIDM
tSSPIDM
VALID
tHSPIDM
tSSPIDM
VALID
tHSPIDM
tDDSPIDM
MOSI (OUTPUT) CPHA
tHDSPIDM
tSSPIDM
MISO (INPUT) VALID
tHSPIDM
VALID
Figure Serial Peripheral Interface (SPI) Port-Master Timing
Rev.
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Serial Peripheral Interface (SPI) Port -Slave Timing
Table Figure describe port slave operations. Table Serial Peripheral Interface (SPI) Port-Slave Timing
VDDEXT VDDEXT LQFP/PBGA Packages MBGA Package 2tSCLK -1.5 2tSCLK -1.5 4tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 VDDEXT V/3.3 Packages 2tSCLK -1.5 2tSCLK -1.5 4tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5 2tSCLK -1.5
Parameter Timing Requirements tSPICHS Serial Clock High Period 2tSCLK -1.5 tSPICLS Serial Clock Period 2tSCLK -1.5 tSPICLK Serial Clock Period 4tSCLK -1.5 2tSCLK -1.5 tHDS Last Edge SPISS Asserted tSPITDS Sequential Transfer Delay 2tSCLK -1.5 tSDSCI SPISS Assertion First Edge 2tSCLK -1.5 tSSPID Data Input Valid Edge (Data Input Setup) tHSPID Sampling Edge Data Input Invalid Switching Characteristics tDSOE SPISS Assertion Data Active tDSDHI SPISS Deassertion Data High Impedance tDDSPID Edge Data Valid (Data Delay) tHDSPID Edge Data Invalid (Data Hold)
Unit
SPISS (INPUT)
tSPICHS
(CPOL (INPUT)
tSPICLS
tSPICLK
tHDS
tSPITDS
tSDSCI
(CPOL (INPUT)
tSPICLS
tSPICHS
tDSOE
tDDSPID tHDSPID tDDSPID tDSDHI
MISO (OUTPUT) CPHA MOSI (INPUT)
tSSPID
VALID
tHSPID
tSSPID
tHSPID
VALID
tDSOE
MISO (OUTPUT) CPHA MOSI (INPUT)
tDDSPID
tDSDHI
tHSPID tSSPID
VALID VALID
Figure Serial Peripheral Interface (SPI) Port-Slave Timing
Rev.
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Universal Asynchronous Receiver-Transmitter (UART) Port-Receive Transmit Timing
Figure describes UART port receive transmit operations. maximum baud rate SCLK/16. shown Figure there some latency between generation internal UART interrupts external data operations. These latencies negligible data transmission rates UART.
CLKOUT (SAMPLE CLOCK)
DATA[8:5] STOP
RECEIVE INTERNAL UART RECEIVE INTERRUPT
UART RECEIVE DATA STOP; CLEARED FIFO READ
START DATA[8:5] STOP[2:1]
TRANSMIT INTERNAL UART TRANSMIT INTERRUPT
UART TRANSMIT PROGRAM; CLEARED WRITE TRANSMIT
Figure UART Port-Receive Transmit Timing
Rev.
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General-Purpose Port Cycle Timing
Table Figure describe GPIO operations. Table General-Purpose Port Cycle Timing
VDDEXT tSCLK VDDEXT V/3.3 Unit tSCLK
Parameter Timing Requirement tWFI GPIO Input Pulse Width Switching Characteristic tDFO GPIO Output Delay from CLKOUT
CLKOUT
tDFO
(OUTPUT) GPIO OUTPUT
tWFI
(INPUT) GPIO INPUT
Figure GPIO Cycle Timing
Rev.
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Timer Cycle Timing
Table Figure describe timer expired operations. input signal asynchronous width capture mode exter clock mode absolute maximum input frequency fSCLK/2 MHz. Table Timer Cycle Timing
VDDEXT VDDEXT V/3.3 (232-1) (232-1)
Parameter Timing Characteristics Timer Pulse Width Input Low1 (Measured SCLK Cycles) Timer Pulse Width Input High1 (Measured SCLK Cycles) Switching Characteristic tHTO Timer Pulse Width Output2 (Measured SCLK Cycles)
Unit SCLK SCLK SCLK
minimum pulse widths apply TMRx input pins width capture external clock modes. They also apply PPI_CLK input pins output mode. minimum time tHTO cycle, maximum time tHTO equals (232-1) cycles.
CLKOUT
tHTO
TMRx (PWM OUTPUT MODE)
TMRx (WIDTH CAPTURE EXTERNAL CLOCK MODES)
Figure Timer PWM_OUT Cycle Timing
Rev.
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JTAG Test Emulation Port Timing
Table Figure describe JTAG port operations. Table JTAG Port Timing
VDDEXT VDDEXT V/3.3
Parameter Timing Requirements tTCK Period TDI, Setup Before High tSTAP tHTAP TDI, Hold After High tSSYS System Inputs Setup Before High1 tHSYS System Inputs Hold After High1 tTRSTW TRST Pulse Width2 (Measured Cycles) Switching Characteristics tDTDO Delay from tDSYS System Outputs Delay After Low3
Unit
System Inputs DATA15-0, ARDY, TMR2-0, PF15-0, PPI_CLK, RSCLK0-1, RFS0-1, DR0PRI, DR0SEC, TSCLK0-1, TFS0-1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RESET, NMI, BMODE1-0, PP3-0. maximum System Outputs DATA15-0, ADDR19-1, ABE1-0, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2-0, PF15-0, RSCLK0-1, RFS0-1, TSCLK0-1, TFS0-1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, BGH, PPI3-0.
tTCK
tSTAP
tHTAP
tDTDO
tSSYS
SYSTEM INPUTS
tHSYS
tDSYS
SYSTEM OUTPUT
Figure JTAG Port Timing
Rev.
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July 2007
OUTPUT DRIVE CURRENTS
Figure through Figure show typical current-voltage char acteristics output drivers ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor. curves represent current drive capability output drivers function output voltage.
VDDEXT 2.75V VDDEXT 2.50V VDDEXT 2.25V VDDEXT 3.65V VDDEXT 3.30V VDDEXT 2.95V
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
-100
-150
SOURCE VOLTAGE
Figure Drive Current (VDDEXT
VDDEXT 2.75V VDDEXT 2.50V VDDEXT 2.25V
-100
-150
SOURCE CURRENT (mA) SOURCE VOLTAGE
Figure Drive Current (VDDEXT
SOURCE CURRENT (mA)
VDDEXT 1.9V VDDEXT 1.8V VDDEXT 1.7V
-100
-150
SOURCE VOLTAGE
Figure Drive Current (VDDEXT
SOURCE VOLTAGE
SOURCE CURRENT (mA)
VDDEXT 1.9V VDDEXT 1.8V VDDEXT 1.7V
Figure Drive Current (VDDEXT
SOURCE VOLTAGE
Figure Drive Current (VDDEXT
Rev.
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VDDEXT 3.65V VDDEXT 3.30V VDDEXT 2.95V SOURCE CURRENT (mA) -150 SOURCE VOLTAGE -100 VDDEXT 3.65V VDDEXT 3.30V VDDEXT 2.95V
SOURCE CURRENT (mA)
-100
SOURCE VOLTAGE
Figure Drive Current (VDDEXT
VDDEXT 2.75V VDDEXT 2.50V VDDEXT 2.25V SOURCE CURRENT (mA) SOURCE CURRENT (mA) SOURCE VOLTAGE -100
Figure Drive Current (VDDEXT
VDDEXT 2.75V VDDEXT 2.50V VDDEXT 2.25V
Figure Drive Current (VDDEXT
SOURCE CURRENT (mA)
SOURCE VOLTAGE
Figure Drive Current (VDDEXT
VDDEXT 1.9V VDDEXT 1.8V VDDEXT 1.7V
SOURCE CURRENT (mA)
VDDEXT 1.9V VDDEXT 1.8V VDDEXT 1.7V
SOURCE VOLTAGE
SOURCE VOLTAGE
Figure Drive Current (VDDEXT
Figure Drive Current (VDDEXT
Rev.
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VDDEXT 3.65V VDDEXT 3.30V VDDEXT 2.95V
SOURCE CURRENT (mA)
VTRIP (high) VTRIP (low) Time tTRIP interval from when output starts driving when output reaches VTRIP (high) VTRIP (low) trip voltage. Time tENA calculated shown equation: ENA_MEASURED TRIP multiple pins (such data bus) enabled, measure ment value that first start driving.
-100
Output Disable Time Measurement
Output pins considered disabled when they stop driv ing, into high impedance state, start decay from their output high voltage. output disable time tDIS difference between tDIS_MEASURED tDECAY shown left side Figure
DIS_MEASURED DECAY
time voltage decay dependent capacitive load load current This decay time approximated equation: DECAY time tDECAY calculated with test loads with equal VDDEXT (nominal) VDDEXT (nominal) V/3.3 time tDIS_MEASURED interval from when reference signal switches, when output voltage decays from measured output high output voltage.
-150 SOURCE VOLTAGE
Figure Drive Current (VDDEXT
POWER DISSIPATION
Many operating conditions affect power dissipation. System designers should refer Estimating Power ADSP-BF531/ BF532/BF533 Blackfin Processors (EE-229) Analog Devices website (www.analog.com)-use site search "EE-229." This document provides detailed information optimizing your design lowest power. ADSP-BF533 Blackfin Processor Hardware Reference Manual definitions various operating modes instructions minimize system power.
TEST CONDITIONS
timing parameters appearing this data sheet were sured under conditions described this section. Figure shows measurement point measurements (except enable/disable). measurement point VMEAS 0.95 VDDEXT (nominal) VDDEXT (nominal)
INPUT OUTPUT
REFERENCE SIGNAL
tDIS_MEASURED tDIS
(MEASURED) (MEASURED)
tENA_MEASURED tENA
(MEASURED) (MEASURED)
VOH(MEASURED) VTRIP(HIGH) VTRIP(LOW) VOL(MEASURED)
VMEAS
VMEAS
tDECAY
tTRIP
Figure Voltage Reference Levels
Measurements (Except Output Enable/Disable)
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING HIGH IMPEDANCE STATE
Output Enable Time Measurement
Output pins considered enabled when they have made transition from high impedance state point when they start driving. output enable time tENA interval from point when
reference signal reaches high voltage level point when output starts driving shown right side Figure time tENA_MEASURED interval, from when reference signal switches, when output voltage reaches VTRIP(high) VTRIP (low). VDDEXT (nominal) V-VTRIP (high) VTRIP (low) VDDEXT (nominal) V/3.3
Rev.
Figure Output Enable/Disable
Example System Hold Time Calculation
determine data output hold time particular system, first calculate tDECAY using equation given above. Choose difference between ADSP-BF531/ADSP-BF532/
ADSP-BF533 processor's output voltage input threshold device requiring hold time. CLis total capacitance (per data line), total leakage three-state current (per data line). hold time will tDECAY
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RISE FALL TIME (10% 90%)
plus various output disable times specified Timing Specifications Page (for example tDSDAT SDRAM write cycle shown SDRAM Interface Timing Page 28).
RISE TIME FALL TIME
Capacitive Loading
Output delays holds based standard capacitive loads: pins (see Figure 44). VLOAD 0.95 VDDEXT (nominal) VDDEXT (nominal) V/3.3 Figure through Figure Page show output rise time varies with capacitance. delay hold specifications given should derated factor derived from these figures. graphs these figures linear side ranges shown.
OUTPUT 30pF VLOAD
LOAD CAPACITANCE (pF)
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT 2.25
RISE FALL TIME (10% 90%)
Figure Equivalent Device Loading Measurements (Includes Fixtures)
RISE FALL TIME (10% 90%) RISE TIME FALL TIME LOAD CAPACITANCE (pF)
RISE TIME FALL TIME
LOAD CAPACITANCE (pF)
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT 3.65
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT 1.75
RISE FALL TIME (10% 90%)
RISE TIME
FALL TIME
LOAD CAPACITANCE (pF)
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT 1.75
Rev.
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RISE FALL TIME (10% 90%) RISE FALL TIME (10% 90%)
RISE TIME FALL TIME
RISE TIME
FALL TIME
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT 2.25
RISE FALL TIME (10% 90%) RISE TIME FALL TIME
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT 2.25
RISE FALL TIME (10% 90%) RISE TIME FALL TIME
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT 3.65
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT 3.65
RISE FALL TIME (10% 90%) RISE TIME FALL TIME
RISE FALL TIME (10% 90%)
RISE TIME
FALL TIME
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT 1.75
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT 1.75
Rev.
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RISE FALL TIME (10% 90%) RISE TIME FALL TIME
where: ambient temperature (C). Table through Table airflow measurements comply with JEDEC standards JESD51-2 JESD51-6, junc tion-to-board measurement complies with JESD51-8. junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). measurements 2S2P JEDEC test board. Thermal resistance Table through Table figure merit relating performance package board convective environment. represents thermal resistance under conditions airflow. represents correlation between TCASE.
LOAD CAPACITANCE (pF)
Table Thermal Characteristics BC-160 Package
Parameter Condition Linear Airflow Linear Airflow Linear Airflow Applicable Linear Airflow Linear Airflow Linear Airflow Typical 27.1 23.85 22.7 7.26 0.14 0.26 0.35 Unit
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT 2.25
RISE FALL TIME (10% 90%)
RISE TIME
FALL TIME
Table Thermal Characteristics ST-176-1 Package
Parameter
LOAD CAPACITANCE (pF)
Condition Linear Airflow Linear Airflow Linear Airflow Linear Airflow Linear Airflow Linear Airflow
Typical 34.9 33.0 32.0 0.50 0.75 1.00
Unit
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT 3.65
ENVIRONMENTAL CONDITIONS
determine junction temperature application printed circuit board use: CASE where:
junction temperature (C).
TCASE case temperature measured customer
center package.
from Table through Table
power dissipation (see Power Dissipation Page
method calculate PD).
Values provided package comparison printed
circuit board design considerations. used first
order approximation equation:
Table Thermal Characteristics B-169 Package
Parameter Condition Linear Airflow Linear Airflow Linear Airflow Applicable Linear Airflow Linear Airflow Linear Airflow Typical 22.8 20.3 19.3 10.39 0.59 0.88 1.37 Unit
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160-BALL BALL ASSIGNMENT
Table lists ball assignment signal. Table Page lists ball assignment ball number. Table 160-Ball CSP_BGA Ball Assignment (Alphabetically Signal)
Signal ABE0 ABE1 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 AMS0 AMS1 AMS2 AMS3 ARDY BMODE0 BMODE1 CLKIN CLKOUT DATA0 DATA1 DATA2 DATA3 Ball Signal DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DR0PRI DR0SEC DR1PRI DR1SEC DT0PRI DT0SEC DT1PRI DT1SEC Ball Signal MISO MOSI PF10 PF11 PF12 PF13 PF14 PF15 PPI_CLK PPI0 PPI1 PPI2 PPI3 RESET RFS0 RFS1 RSCLK0 RSCLK1 RTXI RTXO SA10 SCAS Ball Signal SCKE SRAS TFS0 TFS1 TMR0 TMR1 TMR2 TRST TSCLK0 TSCLK1 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDRTC VROUT0 VROUT1 XTAL Ball
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Table 160-Ball CSP_BGA Ball Assignment (Numerically Ball Number)
Ball Signal VDDEXT PF10 PF11 PF14 PPI2 RTXO RTXI XTAL CLKIN VROUT0 PF12 PF13 PPI3 PPI1 VDDRTC VROUT1 SCKE CLKOUT PF15 VDDEXT PPI0 PPI_CLK RESET VDDEXT Ball Signal SCAS MOSI VDDEXT VDDINT VDDEXT SRAS TFS1 MISO DT1SEC VDDINT VDDINT SA10 ARDY AMS0 TSCLK1 DT1PRI DR1SEC VDDEXT AMS2 AMS1 RSCLK1 RFS1 DR1PRI VDDEXT AMS3 Ball Signal DT0PRI DT0SEC TFS0 ABE1 ABE0 TSCLK0 DR0SEC RFS0 VDDEXT VDDINT VDDEXT ADDR4 ADDR1 DR0PRI TMR2 ADDR7 ADDR5 ADDR2 RSCLK0 TMR0 VDDINT VDDEXT VDDINT VDDEXT ADDR8 ADDR6 ADDR3 TMR1 Ball Signal DATA12 DATA9 DATA6 DATA3 DATA0 ADDR15 ADDR9 ADDR10 ADDR11 TRST BMODE0 DATA13 DATA10 DATA7 DATA4 DATA1 ADDR16 ADDR14 ADDR13 ADDR12 VDDEXT BMODE1 DATA15 DATA14 DATA11 DATA8 DATA5 DATA2 ADDR19 ADDR18 ADDR17
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Figure lists view ball configuration. Figure lists bottom view ball configuration.
KEY: VDDINT VDDEXT VDDRTC VROUT
Figure 160-Ball CSP_BGA Ground Configuration (Top View)
KEY: VDDINT VDDEXT VDDRTC VROUT
Figure 160-Ball CSP_BGA Ground Configuration (Bottom View)
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169-BALL PBGA BALL ASSIGNMENT
Table lists PBGA ball assignment signal. Table Page lists PBGA ball assignment ball number. Table 169-Ball PBGA Ball Assignment (Alphabetically Signal)
Signal ABE0 ABE1 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 AMS0 AMS1 AMS2 AMS3 ARDY BMODE0 BMODE1 CLKIN CLKOUT DATA0 DATA1 DATA2 DATA3 Ball Signal DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DR0PRI DR0SEC DR1PRI DR1SEC DT0PRI DT0SEC DT1PRI DT1SEC Ball Signal MISO MOSI PF10 PF11 PF12 PF13 PF14 PF15 PPI_CLK PPI0 PPI1 PPI2 PPI3 RESET RFS0 RFS1 RSCLK0 RSCLK1 RTCVDD Ball Signal RTXI RTXO SA10 SCAS SCKE SRAS TFS0 TFS1 TMR0 TMR1 TMR2 TRST TSCLK0 TSCLK1 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Ball Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VROUT0 VROUT1 XTAL Ball
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Table 169-Ball PBGA Ball Assignment (Numerically Ball Number)
Ball Signal PF11 PF12 PF14 PPI3 PPI1 RTXI RTXO RESET XTAL CLKIN SRAS SCAS VDDEXT PF10 PF13 PF15 PPI2 PPI0 PPI_CLK VROUT0 VROUT1 SCKE SA10 ARDY Ball Signal CLKOUT AMS0 MOSI MISO AMS1 AMS2 DT1PRI DT1SEC VDDEXT VDDEXT VDDEXT VDDEXT RTCVDD AMS3 TSCLK1 TFS1 VDDEXT DR1PRI DR1SEC VDDEXT ABE0 ABE1 RFS1 Ball Signal RSCLK1 VDDEXT ADDR1 ADDR2 DT0SEC DT0PRI VDDEXT ADDR3 ADDR4 TFS0 TSCLK0 VDDEXT ADDR5 ADDR6 DR0SEC DR0PRI VDDEXT VDDEXT VDDEXT Ball Signal ADDR7 ADDR8 RFS0 RSCLK0 ADDR10 ADDR9 TMR2 TMR1 ADDR12 ADDR11 TMR0 ADDR14 ADDR13 VDDEXT BMODE1 DATA15 DATA13 DATA10 DATA8 DATA6 DATA3 DATA1 ADDR19 ADDR17 ADDR15 TRST BMODE0 DATA14 DATA12 DATA11 Ball Signal DATA9 DATA7 DATA5 DATA4 DATA2 DATA0 ADDR16 ADDR18
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BALL CORNER
DDINT DDEXT
ROUT
VIEW
Figure 169-Ball PBGA Ground Configuration (Top View)
BALL CORNER
DDEXT ROUT DDINT KEY:
BOTTOM VIEW
Figure 169-Ball PBGA Ground Configuration (Bottom View)
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176-LEAD LQFP PINOUT
Table lists LQFP pinout signal. Table Page lists LQFP pinout lead number. Table 176-Lead LQFP Assignment (Alphabetically Signal)
Signal ABE0 ABE1 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 AMS0 AMS1 AMS2 AMS3 ARDY BMODE0 BMODE1 CLKIN CLKOUT DATA0 DATA1 DATA10 Lead Signal DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DR0PRI DR0SEC DR1PRI DR1SEC DT0PRI DT0SEC DT1PRI DT1SEC Lead Signal MISO MOSI PF10 PF11 PF12 PF13 PF14 PF15 Lead Signal PPI_CLK PPI0 PPI1 PPI2 PPI3 RESET RFS0 RFS1 RSCLK0 RSCLK1 RTXI RTXO SA10 SCAS SCKE SRAS TFS0 TFS1 TMR0 TMR1 TMR2 TRST TSCLK0 TSCLK1 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Lead Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDRTC VROUT0 VROUT1 XTAL Lead
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Table 176-Lead LQFP Assignment (Numerically Lead Number)
Lead Signal VROUT1 VROUT0 VDDEXT CLKIN XTAL VDDEXT RESET RTXO RTXI VDDRTC VDDEXT PPI_CLK PPI0 PPI1 PPI2 VDDINT PPI3 PF15 PF14 PF13 VDDEXT PF12 PF11 PF10 Lead Signal VDDEXT VDDINT MISO MOSI VDDEXT DT1SEC DT1PRI TFS1 TSCLK1 DR1SEC DR1PRI RFS1 RSCLK1 VDDINT DT0SEC DT0PRI TFS0 VDDEXT TSCLK0 DR0SEC DR0PRI RFS0 RSCLK0 TMR2 TMR1 TMR0 VDDINT Lead Signal TRST VDDEXT BMODE1 BMODE0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 VDDEXT DATA7 DATA6 DATA5 VDDINT DATA4 DATA3 DATA2 DATA1 DATA0 VDDEXT Lead Signal ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 ADDR14 ADDR13 VDDEXT ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 VDDINT VDDEXT ADDR4 ADDR3 ADDR2 ADDR1 ABE1 ABE0 VDDEXT VDDINT AMS3 AMS2 AMS1 Lead Signal AMS0 ARDY SA10 SCAS SRAS VDDINT CLKOUT VDDEXT SCKE
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OUTLINE DIMENSIONS
Dimensions outline dimension figures shown millimeters.
0.75 0.60 0.45 0.27 0.22 0.17
26.00 24.00
SEATING PLANE 0.08 LEAD COPLANARITY 0.15 0.05
1.45 1.40 1.35 1.60 DETAIL
DETAIL 0.50 LEAD PITCH VIEW (PINS DOWN)
NOTES DIMENSIONS MILLIMETERS ACTUAL POSITION EACH LEAD WITHIN 0.08 IDEAL POSITION, WHEN MEASURED LATERAL DIRECTION. CENTER DIMENSIONS NOMINAL
Figure 176-Lead Profile Quad Flat Package (LQFP) ST-176-1
12.00
CORNER INDEX AREA
BALL INDICATOR 10.40
VIEW
0.80 BALL PITCH 1.31 1.21 1.11 BOTTOM VIEW
1.70
DETAIL
SEATING PLANE 0.40 (NOTE NOTES DIMENSIONS MILLIMETERS. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-205, VARIATION WITH EXCEPTION
BALL DIAMETER.
MINIMUM BALL HEIGHT 0.25.
0.12 0.50 0.45 COPLANARITY 0.40 BALL DIAMETER
DETAIL
Figure 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-2
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BALL CORNER 19.00 16.00 1.00 BALL PITCH VIEW BOTTOM VIEW
0.40
2.50 2.23 1.97
SIDE VIEW DETAIL 0.20 COPLANARITY
NOTES DIMENSIONS MILLIMETERS. COMPLIES WITH JEDEC REGISTERED OUTLINE MS-034, VARIATION AAG-2 MINIMUM BALL HEIGHT 0.40
0.70 BALL DIAMETER 0.60 0.50
SEATING PLANE DETAIL
Figure 169-Ball Plastic Ball Grid Array (B-169)
SURFACE MOUNT DESIGN
Table provided design. industrystandard design recommendations, refer IPC-7351, Generic Requirements Surface Mount Design Land tern Standard. Table Data with Surface Mount Design
Package Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-2 Plastic Ball Grid Array (PBGA) B-169 Ball Attach Type Solder Mask Defined Solder Mask Defined Solder Mask Opening 0.40 diameter 0.43 diameter Ball Size 0.55 diameter 0.56 diameter
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ORDERING GUIDE
Temperature Speed Grade Operating Voltage Range1 (Max) (Nom) Package Description -40°C +85°C internal, 169-Ball Plastic Ball Grid Array (PBGA) -40°C +85°C internal, 169-Ball Plastic Ball Grid Array (PBGA) -40°C +85°C internal, 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +85°C internal, 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +85°C internal, 176-Lead Quad Flatpack (LQFP) -40°C +85°C internal, 176-Lead Quad Flatpack (LQFP) -40°C +85°C internal, 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +85°C internal, 169-Ball Plastic Ball Grid Array (PBGA) -40°C +85°C internal, 176-Lead Quad Flatpack (LQFP) -40°C +105°C internal, 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +105°C internal, 169-Ball Plastic Ball Grid Array (PBGA) -40°C +85°C internal, 169-Ball Plastic Ball Grid Array (PBGA) -40°C +85°C internal, 169-Ball Plastic Ball Grid Array (PBGA) -40°C +85°C internal, 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +85°C internal, 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +85°C internal, 176-Lead Quad Flatpack (LQFP) -40°C +85°C internal, 176-Lead Quad Flatpack (LQFP) -40°C +85°C internal, 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +85°C internal, 169-Ball Plastic Ball Grid Array (PBGA) -40°C +85°C internal, 176-Lead Quad Flatpack (LQFP) -40°C +105°C internal, 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +105°C internal, 169-Ball Plastic Ball Grid Array (PBGA) Package Option B-169 B-169 BC-160-2 BC-160-2 ST-176-1 ST-176-1 BC-160-2 B-169 ST-176-1 BC-160-2 B-169 B-169 B-169 BC-160-2 BC-160-2 ST-176-1 ST-176-1 BC-160-2 B-169 ST-176-1 BC-160-2 B-169
Model ADSP-BF531SBB400 ADSP-BF531SBBZ400 ADSP-BF531SBBC400 ADSP-BF531SBBCZ4002 ADSP-BF531SBST400 ADSP-BF531SBSTZ4002 ADSP-BF531WBBCZ-4A2,3 ADSP-BF531WBBZ-4A2,3 ADSP-BF531WBSTZ-4A2,3 ADSP-BF531WYBCZ-4A2,3 ADSP-BF531WYBZ-4A2,3 ADSP-BF532SBB400 ADSP-BF532SBBZ4002 ADSP-BF532SBBC400 ADSP-BF532SBBCZ4002 ADSP-BF532SBST400 ADSP-BF532SBSTZ400 ADSP-BF532WBBCZ-4A2 ADSP-BF532WBBZ-4A2,3 ADSP-BF532WBSTZ-4A2,3 ADSP-BF532WYBCZ-4A2,3 ADSP-BF532WYBZ-4A2,3
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Model ADSP-BF533SBB500 ADSP-BF533SBBZ5002 ADSP-BF533SBBC500 ADSP-BF533SBBCZ5002 ADSP-BF533SBBC-5V ADSP-BF533SBBCZ-5V2 ADSP-BF533SBBCZ4002 ADSP-BF533SBST400 ADSP-BF533SBSTZ4002 ADSP-BF533SKBC-6V ADSP-BF533SKBCZ-6V2 ADSP-BF533WBBCZ-5A2,3 ADSP-BF533WBBZ-5A2,3 ADSP-BF533WYBCZ-4A2,3 ADSP-BF533WYBZ-4A2,3
Temperature Speed Grade Operating Voltage Range1 (Max) (Nom) Package Description -40°C +85°C Internal, 169-Ball Plastic Ball Grid Array (PBGA) -40°C +85°C Internal, 169-Ball Plastic Ball Grid Array (PBGA) -40°C +85°C Internal 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +85°C Internal 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +85°C 1.25 Internal 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +85°C Internal 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +85°C 1.25 internal, 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +85°C internal, 176-Lead Quad Flatpack (LQFP) -40°C +85°C internal, 176-Lead Quad Flatpack (LQFP) +70°C Internal 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) +70°C Internal 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +85°C Internal, 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +85°C Internal, 169-Ball Plastic Ball Grid Array (PBGA) -40°C +105°C internal, 160-Ball Chip Scale Package Ball Grid Array (CSP_BGA) -40°C +105°C internal, 169-Ball Plastic Ball Grid Array (PBGA)
Package Option B-169 B-169 BC-160-2 BC-160-2 BC-160-2 BC-160-2 BC-160-2 ST-176-1 ST-176-1 BC-160-2 BC-160-2 BC-160-2 B-169 BC-160-2 B-169
Referenced temperature ambient temperature.
RoHS Compliant Part.
Automotive grade part.
©2007 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D03728-0-7/07(E)
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