MONOLITHIC MANCHESTER ENCODER (SERIES 3D7521) All-silicon, low-po

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MONOLITHIC MANCHESTER ENCODER (SERIES 3D7521) All-silicon, low-po

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3D7521
MONOLITHIC MANCHESTER ENCODER (SERIES 3D7521)
All-silicon, low-power CMOS technology TTL/CMOS compatible inputs outputs Vapor phase, wave solderable ground bounce noise Maximum data rate: MBaud
data delay devices, inc.
PACKAGES
RESB 3D7521Z
RESB
SOIC (.150)
3D7521D SOIC (.150)
mechanical dimensions, click here. package marking details, click here.
FUNCTIONAL DESCRIPTION
3D7521 monolithic CMOS Manchester Encoder. clock data, present unit input, combined into single bi-phaselevel signal. this encoding mode, logic represented high-to-low transition within cell, while logic zero represented low-to-high transition. unit operating baud rate Mbaud) equal input clock frequency MHZ). pins marked must left unconnected.
DESCRIPTIONS
RESB Data Input Clock Input Reset Signal Output Inverted Signal Output Volts Ground
all-CMOS 3D7521 integrated circuit been designed reliable, economic alternative hybrid Manchester Encoder. TTL- CMOS-compatible, capable driving 74LS-type loads. offered space saving surface mount 8-pin 14-pin SOICs.
#06001
10/31/2007
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7521
APPLICATION NOTES
3D7521 Manchester Encoder samples data input rising edge input clock. sampled data used conjunction with clock rising falling edges generate byphase level Manchester code.
OUTPUT SIGNAL CHARACTERISTICS
3D7521 presents outputs true complimented encoded data. High-to-Low time skew selected data output should budgeted user, relates application, satisfactorily estimate distortion transmitted data stream. Such estimate very useful determining functionality margins data link, 3D7522 Manchester Decoder used decode received data.
INPUT SIGNAL CHARACTERISTICS
3D7521 Manchester Encoder inputs compatible. user should assure himself that volt threshold used when referring timing, especially input clock duty cycle.
CLOCK DUTY CYCLE ERRORS
3D7521 Manchester Encoder employs timing clock rising falling edges (duty cycle) implement required coding scheme. reduce difference between output data high time time, essential that deviation input clock duty cycle from 50/50 minimized.
POWER SUPPLY TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry strongly dependent power supply temperature. monolithic 3D7521 Manchester encoder utilizes novel innovative compensation circuitry minimize timing variations induced fluctuations power supply and/or temperature.
RESET (RESB)
Power-on reset (Left high normal operation)
1/fC
CLOCK (CIN)
DATA (DIN)
TRANSMIT (TXB) TRANSMIT (TX)
Figure Timing Diagram
#06001
10/31/2007
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7521
DEVICE SPECIFICATIONS
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Input Current Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
(-40C 85C, 4.75V 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current High Level Output Current Level Output Current Output Rise Fall Time SYMBOL -4.0 UNITS NOTES
4.75V 2.4V 4.75V 0.4V
*IDD(Dynamic) where: Average capacitance load/pin (pf) Input frequency (GHz)
Input Capacitance typical Output Load Capacitance (CLD)
TABLE ELECTRICAL CHARACTERISTICS
(-40C 85C, 4.75V 5.25V) PARAMETER Input Baud Rate Clock Frequency Data set-up clock rising Data hold from clock rising High-Low time skew High-Low time skew High/Low time skew
SYMBOL
-3.5 -2.0 -3.0
UNITS MBaud
NOTES
Notes: Assumes duty cycle clock input
#06001
10/31/2007
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7521
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High 3.0V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.4V Pulse Width: PWIN 1/(2*BAUD) Period: PERIN 1/BAUD OUTPUT: Rload: Cload: Threshold: 1.5V (Rising Falling)
Device Under Test
Digital Scope
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
WAVEFORM GENERATOR
TRIG
DEVICE UNDER TEST (DUT)
TRIG
DIGITAL SCOPE
Figure Test Setup
PERIN tRISE INPUT SIGNAL
2.4V 1.5V 0.6V
tFALL
2.4V 1.5V 0.6V
tPHL
tPLH OUTPUT SIGNAL
1.5V
1.5V
Figure Timing Diagram
#06001
10/31/2007
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

MONOLITHIC MANCHESTER ENCODER (SERIES 3D7521) All-silicon, low-po

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