CyFiTransceiver Battery Voltage Monitoring Circuitry Supports coi

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CyFiTransceiver Battery Voltage Monitoring Circuitry Supports coi

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CYRF7936
CyFiTransceiver
Battery Voltage Monitoring Circuitry Supports coin-cell operated applications Operating voltage from 1.8V 3.6V Operating temperature from 70°C Space saving 40-pin package
Direct Sequence Spread Spectrum (DSSS) radio transceiver Operates unlicensed worldwide Industrial, Scientific, Medical (ISM) band (2.400 2.483 GHz) operating current (Transmit dBm) Transmit power Receive sensitivity Sleep Current DSSS data rates kbps, GFSK data rate Mbps external component count Auto Transaction Sequencer (ATS) intervention Framing, Length, CRC16, Auto Power Management Unit (PMU) Fast Startup Fast Channel Changes Separate 16-byte Transmit Receive FIFOs Dynamic data rate reception Receive Signal Strength Indication (RSSI) Serial Peripheral Interface (SPI) control while sleep mode microcontroller interface
Applications
Wireless Sensor Networks Wireless Actuator Control Home Automation White Goods Commercial Building Automation Automatic Meter Readers Precision Agriculture Remote Controls Consumer Electronics Personal Health Fitness Toys
Applications Support
www.cypress.com development tools, reference designs, application notes.
Logic Block Diagram
VREG VBAT MISO MOSI PACTL
CyFi Radio Modem Data Interface Sequencer
GFSK Modulator
RFBIAS
DSSS Baseband Framer
RSSI Xtal Synthesizer
GFSK Demodulator
XTAL XOUT
Cypress Semiconductor Corporation Document 001-48013 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised September 2008
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CYRF7936
Functional Description
CYRF7936 CyFiTransceiver Radio designed low-power embedded wireless applications. Combined with Cypress's PSoC programmable system-on-chip CyFi network protocol stack, CYRF7936 used implement complete CyFi wireless system. Figure Diagram CYRF7936 40-Pin
VBAT0 VREG
Corner tabs
XTAL VBAT1 VBAT2
Bottom Side
PACTL GPIO XOUT GPIO MISO GPIO MOSI SDAT GPIO
CYRF7936 CyFi Transciever lead
RFBIAS RESV
Table Description CYRF7936 40-Pin Number Name RFBIAS PACTL XTAL XOUT MISO MOSI Type Default Description Differential signal from antenna. Differential signal from antenna. 1.8V reference voltage. Control signal external switch, GPIO. crystal. Buffered 0.75, 1.5, clock, PACTL, GPIO. Tri-states sleep mode (configure GPIO drive LOW). clock. data output (Master Slave Out), GPIO 3-pin mode). Tri-states when 3PIN deasserted. data input (Master Slave In), SDAT. enable, active assertion. Enables frames transfers. Interrupt output (configurable active HIGH LOW), GPIO. Device reset. Internal kohm pull down resistor. Active HIGH, typically connect through 0.47 capacitor VBAT. Must have event first time power applied radio. Otherwise state radio control registers unknown. inductor/diode connection, when used. used, connect GND. boosted output voltage feedback. Decoupling 1.8V logic regulator, connect through 0.47 capacitor GND. VBAT 1.8V 3.6V. Main supply. 2.4V 3.6V. Typically connected VREG. Page
VREG VBAT(0-2)
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Table Description CYRF7936 40-Pin (continued) Number Name RESV Type Default interface voltage, 1.8-3.6V. Must connected GND. Connect GND. Description
E-PAD Corner Tabs
Ground. Must soldered Ground. solder tabs keep other signal traces clear. tabs common lead frame paddle which grounded after grounded. While they visible user, they extend bottom.
Functional Overview
CYRF7936 designed implement wireless device links operating worldwide frequency band. intended systems compliant with worldwide regulations covered ETSI 489-1 V1.41, ETSI 328-1 V1.3.1 (Europe), Part (USA Industry Canada), TELEC ARIB_T66_March, 2003 (Japan). CYRF7936 contains CyFi radio modem which features Mbps GFSK radio front-end, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI). CYRF7936 features interface data transfer device configuration. CyFi radio modem supports discrete channels (regulations limit some these channels certain jurisdictions). baseband performs DSSS spreading/despreading, Start Packet (SOP), Packet (EOP) detection, CRC16 generation checking. baseband also configured automatically transmit Acknowledge (ACK) handshake packets whenever valid packet received. When receive mode, with packet framing enabled, device always ready receive data transmitted supported rates. This enables implementation mixed-rate systems which different devices different data rates. This also enables implementation dynamic data rate systems that high data rates shorter distances low-moderate interference environment both. changes lower data rates longer distances high interference environments both. addition, CYRF7936 Power Management Unit (PMU), which allows direct connection device battery voltage range 1.8V 3.6V. conditions battery voltage provide supply voltages required device, supply external devices.
Data Transmission Modes
CyFi radio transceiver supports different data transmission modes:
GFSK mode, data transmitted Mbps, without DSSS. mode, DSSS enabled eight bits encoded each derived code symbol transmitted.
Both chip chip Pseudo Noise (PN) codes supported mode. general, lower data rates reduce packet error rate given environment.
Packet Framing
CYRF7936 device supports following data packet framing features: Packets begin with two-symbol Start-of-Packet (SoP) marker. SOP_CODE_ADR code used different from that used "body" packet, desired different length. must configured same length both sides link. Length This first eight bits after symbol, transmitted payload data rate. condition inferred after reception number bytes defined length field, plus bytes CRC16. CRC16 device configured append CRC16 each packet. CRC16 uses polynomial with added programmability seed. enabled, receiver verifies calculated CRC16 payload data against received value CRC16 field. seed value CRC16 calculation configurable, CRC16 transmitted calculated using either loaded seed value zero seed; received data CRC16 checked against both configured zero CRC16 seeds.
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CRC16 detects following errors:
number bits error (irrespective location). error burst wide checksum itself.
error. bits error (irrespective apart, which column, on).
Figure shows example packet with SOP, CRC16, lengths fields enabled, Figure shows standard packet.
Figure Example Packet Format
16us
Packet
Figure Example Packet Format
16us
Packet Buffers
data transmission reception byte packet buffers transmission reception. transmit buffer allows loading complete packet bytes payload data burst transaction. This then transmitted with further intervention. Similarly, receive buffer allows receiving entire packet payload data bytes with firmware intervention required until packet reception complete. CYRF7936 supports packets bytes. However, actual maximum packet length depends accuracy clock each link data mode. Interrupts provided allow transmit receive buffers FIFOs. When transmitting packet longer than bytes, load bytes initially, further bytes transmit buffer transmission data creates space buffer. Similarly, when receiving packets longer than bytes, must fetch received data from FIFO periodically during packet reception prevent from overflowing.
Similarly, when receiving transaction mode, device automatically:
waits receive mode valid packet received transitions transmit mode, transmits packet transitions transaction state (receive mode await next packet, on.)
contents packet buffers affected transmission reception packets. each case, entire packet transaction takes place without need firmware action long packets bytes less used). transmit data, must load data packet transmitted, length, bit. Similarly, when receiving packets transaction mode, firmware must retrieve fully received packet response interrupt request indicating reception packet.
Data Rates
CYRF7936 supports following data rates combining code lengths data transmission modes described previous sections:
Auto Transaction Sequencer (ATS)
CYRF7936 provides automated support transmission reception acknowledged data packets. When transmitting transaction mode, device automatically:
1000 kbps (GFSK) kbps chip 8DR) kbps chip 8DR)
starts crystal synthesizer enters transmit mode transmits packet transmit buffer transitions receive mode waits packet transitions transaction state when packet received timeout period expires
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Functional Block Overview
CyFi Radio Modem
CyFi radio Modem dual conversion architecture optimized power, range, robustness. CyFi radio modem employs channel-matched filters achieve high performance presence interference. integrated Power Amplifier (PA) provides transmit power, with output power control range seven steps. supply current device reduced output power reduced. Table Internal Output Power Step Table Setting Typical Output Power (dBm)
communication described following:
Command Direction (bit enables write transaction. When equals `0', enables read transactions. Command Increment (bit enables auto address increment. When set, address field automatically increments each data byte burst access. Otherwise same address accessed. bits address Eight bits data
device receives from application pin. Data from application shifted MOSI pin. Data application shifted MISO pin. active Slave Select (SS#) must asserted initiate transfer. application initiate data transfers using multi-byte transaction. first byte Command/Address byte, following bytes data bytes shown Figure through Figure page communications interface burst mechanism, where first byte followed many data bytes required. burst transaction terminated deasserting slave select (SS# communications interface single read burst read sequences shown Figure Figure page respectively. communications interface single write burst write sequences shown Figure Figure page respectively. This interface optionally operated 3-pin mode with MISO MOSI functions combined single bidirectional data (SDAT). When using 3-pin mode, user firmware must ensure that MOSI high impedance state except when MOSI actively transmitting data. device registers written read from byte time, several sequential register locations written read single transaction using incrementing burst mode. addition single byte configuration registers, device includes register files. Register files FIFOs written read from using nonincrementing burst transactions. function optionally multiplexed onto MOSI pin. When this option enabled, function available while LOW. When using this configuration, user firmware must ensure that MOSI high impedance state whenever HIGH. interface dependent internal clock. Registers therefore read from written when device sleep mode, oscillator disabled. interface pins have separate voltage reference (VIO). This enables device interface directly MCUs operating voltages below CYRF7936 supply voltage.
Frequency Synthesizer
Before transmission reception begin, frequency synthesizer must settle. settling time varies depending channel; fast channels provided with maximum settling time `fast channels' (less than settling time) every third channel, starting including (for example, 72).
Baseband Framer
baseband framer blocks provide DSSS encoding decoding, generation reception, CRC16 generation checking, detection length field.
Packet Buffers Radio Configuration Registers
Packet data configuration registers accessed through interface. configuration registers directly addressed through address field packet. Configuration registers allow configuration DSSS codes, data rate, operating mode, interrupt masks, interrupt status,
Interface
CYRF7936 interface supporting communication between application more slave devices (including CYRF7936). interface supports single-byte multi-byte serial transfers using either 4-pin 3-pin interfacing. communications interface consists Slave Select (SS#), Serial Clock (SCK), Master Out-Slave (MOSI), Master In-Slave (MISO), Serial Data (SDAT).
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Figure Transaction Format
Byte Name [5:0] Address Byte [7:0] Data
Figure Single Read Sequence
addr
MOSI MISO
data
Figure Incrementing Burst Read Sequence
MOSI MISO
addr
data mcu1
data mcu1+N
Figure Single Write Sequence
addr
data from
MOSI MISO
Figure Incrementing Burst Write Sequence
addr
data from mcu1
data from mcu1+N
MOSI MISO
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Interrupts
device provides interrupt (IRQ) output, which configurable indicate occurrence various different events. programmed either active HIGH active LOW, either CMOS open drain output. available interrupts described section Register Descriptions page CYRF7936 features three sets interrupts: transmit, receive, system interrupts. These interrupts share single (IRQ), independently enabled disabled. contents enable registers preserved when switching between transmit receive modes. more than interrupt enabled time, necessary read relevant status register determine which event caused assert. Even when given interrupt source disabled, status condition that would otherwise cause interrupt determined reading appropriate status register. therefore possible devices without pin, polling status registers wait event, rather than using pin.
output voltage (VREG) Power Management Unit (PMU) configurable several minimum values between 2.4V 2.7V. VREG used provide (average load) external devices. possible disable provide externally regulated supply voltage device's main supply range 2.4V 3.6V. also provides regulated 1.8V supply logic. designed provide high boost efficiency (74-85% depending input voltage, output voltage, load) when using Schottky diode power inductor, eliminating need external boost converter many systems where other components require boosted voltage. However, reasonable efficiencies (69-82% depending input voltage, output voltage, load) achieved when using cost components such SOT23 diodes 0805 inductors. also provides configurable battery detection function, which read over interface. seven thresholds between 1.8V 2.7V selected. interrupt configured assert when voltage VBAT falls below configured threshold. latched event. Battery monitoring disabled when device sleep mode.
Clocks
crystal better) directly connected between XTAL without need external capacitors. digital clock function provided, with selectable output frequencies 0.75, 1.5, MHz. This output used clock external microcontroller (MCU) ASIC. This output enabled default, disabled. requirements directly connect crystal XTAL are:
Noise Amplifier Received Signal Strength Indication
gain receiver controlled directly clearing writing Noise Amplifier (LNA) RX_CFG_ADR register. Clearing reduces receiver gain approximately allowing accurate reception very strong received signals (for example, when operating receiver very close transmitter). Approximately receiver attenuation added setting Attenuation (ATT) bit. This limits data reception devices very short ranges. Disabling enabling recommended, unless receiving from device using external When device receive mode RSSI_ADR register returns relative signal strength on-channel signal power. When receiving, device automatically measures stores relative strength signal being received five value. RSSI reading taken automatically when detected. addition, RSSI reading taken every time previous reading read from RSSI_ADR register, allowing background energy level given channel easily measured when RSSI read while signal being received. reading occur fast once every
Nominal Frequency: Operating Mode: Fundamental Mode Resonance Mode: Parallel Resonant Frequency Initial Stability: Series Resistance: ohms Load Capacitance: Drive Level:
Power Management
operating voltage device 1.8V 3.6V which applied VBAT pin. device shut down fully static sleep mode writing STATE bits XACT_CFG_ADR register over interface. device enters sleep mode within after last positive edge this transaction. Alternatively, device configured automatically enter sleep mode after completing packet transmission reception. When sleep mode, on-chip oscillator stopped, interface remains functional. device wakes from sleep mode automatically when device commanded enter transmit receive mode. When resuming from sleep mode, there short delay while oscillator restarts. device configured assert when oscillator stabilized.
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Application Examples
Figure Recommended Circuit Systems where VBAT 2.4V
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Table Recommended Systems where VBAT 2.4V Item 730-10012 730-11955 730-11398 730R-13322 730-13037 730-13400 730-13404 Part Number Reference ANT1 C12,C7 Description Manufacturer Part Number ECJ-0EC1H150J C0402C209C5GAC ECJ-0EC1H1R5C GRM155R60J474K E19D C0805C106K9PAC ECJ-0EB0J105M 0402YD473KAT2A 2.5GHZ H-STUB WIGGLE ANTENNA 32MIL 15PF CERAMIC 0402 Panasonic CERAMIC 0402 Kemet 1.5PF CERAMIC 0402 PANASONIC .47UF 6.3V 0402 Murata
CERAMIC 10UF 6.3V 0805 Kemet 6.3V CERAMIC 0402 Panasonic
C9,C10,C11, 0.047 CERAMIC C13,C15,C1 0402 LABEL1 LABEL2
730R-11952 800-13317 420-11976 800-13401 800-11651 800-10594 630-11356 610-13402 CYRF7936-40LFXC 800-13259 PDCR-9515 REV01 920-11206 920-51500 REV01
.10UF CERAMIC 0402 Kemet DIODE SCHOTTKY 0.5A SOT23 DIODES CONN HEADER GOLD Hirose Electric LTD. INDUCTOR 22NH FIXED 0603 INDUCTOR 1.8NH +-.3NH FIXED 0402 COIL 10UH 1100MA CHOKE 0805
C0402C104K8PAC BAT400D-7-F DF11-12DP-2DSA(0
Panasonic ELJ-RE22NGF2 Panasonic ELJ-RF1N8DF Newark 30K5421 9C08052A1R00FK CYRF7936-40LFXC GF-1200008 PDCR-9515 REV01
1.00 1/8W 0805 Yageo 1/16W 0402
Panasonic ERJ-2GEJ470X
RADIO QFN-40 Cypress Semiconductor CRYSTAL 12.00MHZ HC49 PRINTED CIRCUIT BOARD Serial Number eCERA Cypress Semiconductor
121R-51500 REV01
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0402
0402
IND0603
0402
VBAT2 VBAT1 VBAT0
VREG
IND0402
0.47
0402
VCC1 VCC2 VCC3
VBUS PACTL XTAL PACTL
0402
RFbias
0402
0402
zero
0402
LOAD
CY8C24794-24LFXI
GND1
Green PUSHBUTTON nLED2
0402 0402
ACTIVITY GREEN ACTIVITY
nLED1
0402
0.047
0402
0.047
0402
0.047
E-PAD
Power Supply
0805
VOUT PYBASS TPS79133
0402
0.01
Figure Recommended Circuit Systems where VBAT 2.4V 3.6V (PMU Disabled)
0805
0402
0402
LP_nSS LP_IRQ MISO CLKOUT MOSI LP_IRQ
0402
0402
PLUG P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7 P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 RESV NC10 NC11 NC12 NC13 NC14 NC15 NC16 XOUT CLKOUT
0402
0603
VBUS nLED2 MOSI MISO nLED1 LP_nSS MOSI MISO
0603
P0_1
P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7
Crystal
0402
0.047
0402
0.047
0402
0.047
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Table Recommended Systems where VBAT 2.4V 3.6V (PMU disabled) Item Part Number Reference 730-10012 730-11955 730-11398 730-13322 730-13404 ANT1 Description 2.5GHZ H-STUB WIGGLE ANTENNA 32MIL 15PF CERAMIC 0402 CERAMIC 0402 1.5PF CERAMIC 0402 0.47 6.3V CERAMIC 0402 Manufacturer Panasonic Kemet PANASONIC Murata ECJ-0EC1H150J C0402C209C5GACTU ECJ-0EC1H1R5C GRM155R60J474KE19D 0402YD473KAT2A Part Number
C6,C7,C8, 0.047 CERAMIC 0402 C9,C10, 1500PF CERAMIC 0402 CERAMIC 4.7UF 6.3V 0805 2.2UF 0805
730-11953 730-13040 730-12003
Kemet Kemet
C0402C152K5RACTU C0805C475K9PACTU
Murata GRM21BR71A225KA01L Electronics North America LITEON ACON LTST-C155KGJRKT UAR72-4N5J10
800-13333 420-13046 800-13401 800-11651 610-10037 610-10343 610-10016 610-13472 610-10684 200-13471
R9,R8 R10,
GREEN/RED BICOLOR 1210 CONN PLUG TYPE INDUCTOR 22NH FIXED 0603 INDUCTOR 1.8NH +-.3NH FIXED 0402 1/16W 0603 ZERO 1/16W 0402
Panasonic ELJ-RE22NGF2 Panasonic ELJ-RF1N8DF Panasonic ERJ-3GEYJ240V Panasonic ERJ-2GE0R00X
CHIP 1/16W 0402 Panasonic ERJ-2GEJ102X CHIP 1/16W 0402 Panasonic ERJ-2GEJ621X CHIP 1/16W 0402 Phycomp CyFi Transceiver QFN-40 PSoC Mixed Signal Array CRYSTAL 12.00MHZ HC49 Serial Number Cypress Semiconductor Cypress Semiconductor eCERA XXXXXX 9C1A04021000FLHF3
SWITCH 3.5MMX2.9MM 160GF Panasonic EVQ-P7J01K CYRF7936 CY8C24794-24LFXI GF-1200008
CYRF7936-40LFC CY8C24794-24LF 800-13259 LABEL1
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Register Descriptions
registers read writable, except where noted. Registers written read from individually sequential groups. Table Register Summary
Address
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x26 0x27 0x28 0x29 0x32 0x35 0x39 Register Files 0x20 0x21 0x22 0x23 0x24 0x25
Mnemonic
CHANNEL_ADR TX_LENGTH_ADR TX_CTRL_ADR TX_CFG_ADR TX_IRQ_STATUS_ADR RX_CTRL_ADR RX_CFG_ADR RX_IRQ_STATUS_ADR RX_STATUS_ADR RX_COUNT_ADR RX_LENGTH_ADR PWR_CTRL_ADR XTAL_CTRL_ADR IO_CFG_ADR GPIO_CTRL_ADR XACT_CFG_ADR FRAMING_CFG_ADR DATA32_THOLD_ADR DATA64_THOLD_ADR RSSI_ADR EOP_CTRL_ADR CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR TX_CRC_LSB_ADR TX_CRC_MSB_ADR RX_CRC_LSB_ADR RX_CRC_MSB_ADR TX_OFFSET_LSB_ADR TX_OFFSET_MSB_ADR MODE_OVERRIDE_ADR RX_OVERRIDE_ADR TX_OVERRIDE_ADR XTAL_CFG_ADR CLK_OVERRIDE_ADR CLK_EN_ADR RX_ABORT_ADR AUTO_CAL_TIME_ADR AUTO_CAL_OFFSET_AD ANALOG_CTRL_ADR TX_BUFFER_ADR RX_BUFFER_ADR SOP_CODE_ADR DATA_CODE_ADR PREAMBLE_ADR MFG_ID_ADR
Used
Default[1] Access[1]
-1001000 00000000 00000011 -000101 -00000111 10010-10 -00000000 00000000 10100000 000-100 00000000 0000-1-000000 10100101 -0100 -01010 0-100000 10100100 00000000 00000000 -11111111 11111111 00000000 -0000 00000-0 000000000000000 00000000 00000000 00000000 00000000 00000011 00000000 00000000 -Note Note Note -bbbbbbb bbbbbbbb bbbbbbbb -bbbbbb rrrrrrrr bbbbbbbb bbbbb-bb brrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbb-bbbb bbb-bbb bbbbbbbb bbbbrrrr b-bbbbbb bbbbbbbb -bbbb -bbbbb r-rrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbbbbbbb -bbbb wwwww-w bbbbbbbbbbbbbbb wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww rrrrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr
Used RXOW
Used RSVD SOPDET
TXB15 IRQEN DATA CODE LENGTH TXB15 RXB16 IRQEN RXB16
Channel Length TXB8 TXB0 IRQEN IRQEN
TXBERR IRQEN
IRQEN
IRQEN
LVIRQ
XOUT XOUT Used Used MISO Used Used Used Used
Mode Force XSIRQ MISO PACTL Used Used HINT
Used RSVD RSVD RSVD RSVD RSVD
Used RSVD RXTX RSVD RSVD RSVD RSVD
Used RXACK RSVD RSVD RSVD RSVD ABORT
DATA MODE SETTING TXB8 TXB0 TXBERR RXB8 RXB1 RXBERR IRQEN IRQEN IRQEN IRQEN IRQEN FAST TURN HILO Used RXOW RXB8 RXB1 RXBERR CRC0 Code Data Mode Count Length PFET OUTV disable Used Used FREQ XOUT PACTL PACTL 3PIN GPIO GPIO XOUT MISO PACTL STATE Used TH32 TH64 RSSI SEED SEED STRIM Used STRIM AWAKE Used Used RXDR CRC0 RXCRC Used TXACK OVRD TXCRC RSVD RSVD START RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD AUTO_CAL_TIME AUTO_CAL_OFFSET RSVD RSVD RSVD SLOW
RSVD
RSVD
RSVD
Buffer File Buffer File Code File Data Code File Preamble File File
Notes read/write; read only; write only; used, default value undefined. SOP_CODE_ADR default 0x17FF9E213690C782. DATA_CODE_ADR default PREAMBLE_ADR default 0x333302. count value must great than greater than Registers must configured accessed only when radio IDLE SLEEP mode. PMU, GPIOs, RSSI registers accessed Active mode. EOP_CTRL_ADR[6:4] must never have value "000", that Hint Symbol count must never PFET Bit: Setting this disables FET, therefore safely allowing Vbat connected separate reference from when disabled radio.
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Absolute Maximum Ratings
Exceeding maximum ratings shorten useful life device. User guidelines tested. Storage Temperature -65°C +150°C Ambient Temperature with Power Applied. -55°C +125°C Supply Voltage power supply relative .-0.3V +3.9V Voltage Logic Inputs[8] -0.3V +0.3V Voltage applied Outputs High-Z State. -0.3V +0.3V
Static Discharge Voltage (Digital)[9] >2000V Static Discharge Voltage (RF)[9] 1100V Latch-Up Current .+200 -200
Operating Conditions
.2.4V 3.6V .1.8V 3.6V VBAT .1.8V 3.6V (Ambient Temperature Under Bias) +70°C Ground Voltage. FOSC (Crystal Frequency). 12MHz
Characteristics
25°C, VBAT 2.4V, disabled, fOSC 12.000000 MHz)
Parameter
VREG[10] VREG[10] VIO[11] VOH1 VOH2 (GFSK)[13] VBAT
Description
Battery Voltage Output Voltage Output Voltage Voltage Voltage Output High Voltage Condition Output High Voltage Condition Output Voltage Input High Voltage Input Voltage Input Leakage Current Input Capacitance Average ICC, Mbps, slow channel Sleep Mode Sleep Mode Radio off, XTAL Active during Synth Start during Transmit during Transmit during Transmit during Receive during Receive Boost Converter Efficiency Average External Load current Average External Load current 0-70°C 0-70°C 2.4V mode 2.7V mode
Conditions
-100.0 -2.0
2.4[12]
0.7VIO
2.43 2.73
0.45 0.3VIO 0.26 0.87 31.4 20.8 26.2 34.1 18.4 21.2
except XTAL, RFN, RFP, RFBIAS way, bytes/10
(32-8DR)[13] Average ICC, kbps, fast channel way, bytes/10 ISB[14] ISB[14] enabled XOUT disabled dBm) dBm) dBm) off, VBAT 2.5V, VREG 2.73V, ILOAD VBAT 1.8V, VREG 2.73V, 0-50°C, Mode VBAT 1.8V, VREG 2.73V, 50-70°C, Mode
IDLE Isynth Boost ILOAD_EXT ILOAD_EXT
Unit
Notes permissible connect voltages above inputs through series resistor limiting input current timing guaranteed. Human Body Model (HBM). VREG depends battery input voltage. sleep mode, interface voltage reference VBAT. sleep mode, min. 1.8V. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including CRC16), changing receive mode, receiving handshake. Device sleep except during this transaction. guaranteed connected voltages higher than VIO.
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Characteristics
Characteristics CYRF7936 follow[12] Table Interface[16] Parameter tSCK_CYC tSCK_HI tSCK_LO tDAT_SU tDAT_HLD tDAT_VAL tDAT_VAL_TRI tSS_SU tSS_HLD tSS_PW tSCK_SU tSCK_HLD tRESET Clock Period Clock High Time Clock Time Input Data Setup Time Input Data Hold Time Output Data Valid Time Output Data Tri-state (MOSI from Slave Select Deassert) Slave Select Setup Time before first positive edge Slave Select Hold Time after last negative edge Slave Select Minimum Pulse Width Slave Select Setup Time Hold Time Minimum Pulse Width Figure Timing
tSCK_CYC tSCK_SU tSS_SU tDAT_SU MOSI input tDAT_VAL MISO tDAT_VAL_TRI tDAT_HLD tSS_HLD tSCK_HI tSCK_LO tSCK_HLD
Description
238.1
[17]
Unit
MOSI output
Notes values guaranteed voltage exceeding VIO. CLOAD must start time goes LOW, otherwise success transactions guaranteed.
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Characteristics
Table Radio Parameters Parameter Description Frequency Range Note Receiver 25°C, 3.0V, fOSC 12.000000 MHz, 1E-3) Sensitivity kbps 64-8DR 1E-3 Sensitivity kbps 32-8DR Sensitivity Sensitivity GFSK Gain Gain Maximum Received Signal RSSI Value PWRin RSSI Slope Interference Performance (CER 1E-3) Co-channel Interference rejection Carrier-to-Interference (C/I) Adjacent MHz) channel selectivity Adjacent MHz) channel selectivity Adjacent MHz) channel selectivity Out-of-Band Blocking MHz-12.75 MHz[19] Intermodulation Receive Spurious Emission Transmitter 25°C, 3.0V) Maximum Transmit Power Maximum Transmit Power Maximum Transmit Power Maximum Transmit Power Power Control Range Power Range Control Step Size Frequency Deviation Frequency Deviation Error Vector Magnitude (FSK error) Occupied Bandwidth Transmit Spurious Emission In-band Spurious Second Channel Power MHz) In-band Spurious Third Channel Power MHz) Seven steps, monotonic Code Pattern 10101010 Code Pattern 11110000 dBc, ResBW %rms ResBW ResBW ResBW dBm, 5,10 1E-3 1E-3 1E-3, SLOW Conditions 2.400 22.8 -31.7 2.497 Unit Count dB/Count
Notes Subject regulation. Exceptions 5C/3.
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CYRF7936
Table Radio Parameters (continued) Parameter Description Non-Harmonically Related Spurs (800 MHz) Non-Harmonically Related Spurs (1.6 GHz) Non-Harmonically Related Spurs (3.2 GHz) Harmonic Spurs (Second Harmonic) Harmonic Spurs (Third Harmonic) Fourth Greater Harmonics Power Management (Crystal eCERA GF-1200008) Crystal Start 10ppm Crystal Start Synth Settle Synth Settle Synth Settle Link Turnaround Time Link Turnaround Time Link Turnaround Time Link Turnaround Time Packet Length XSIRQ Slow channels Medium channels Fast channels GFSK kbps kbps <125 kbps crystal-to-crystal bytes Conditions Unit
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CYRF7936
Typical Operating Characteristics
typical operating characteristics CYRF7936 follow[20]
Transmit Power Temperature (Vcc 2.7v) Output Power (dBm) Temp (deg Output Power (dBm) Transmit Power (PMU off)
Transmit Power Channel
Output Power (dBm)
Channel
Typical RSSI Count Input Power
Average RSSI Temperature signal -70dBm) RSSI Count Temp (deg
Average RSSI signal -70dBm)
RSSI Count RSSI Count
-120
-100 Input Power (dBm)
RSSI Channel signal -70dBm)
Sensitivity (1Mbps CER) Receiver Sensitivity (dBm)
Sensitivity Temperature (1Mbps CER) Receiver Sensitivity (dBm)
RSSI Count Channel
8DR32
8DR32
Temp (deg
Receiver Sensitivity Frequency Offset Receiver Sensitivity (dBm) Receiver Sensitivity (dBm) -100 Crystal Offset (ppm)
Receiver Sensitivity Channel (3.0v, Room Temp)
Carrier Interferer (Narrow band, modulation) 20.0 10.0
GFSK
GFSK
(dB)
-10.0 -20.0 -30.0 -40.0
8DR64
-150
8DR32
-50.0 -60.0
Channel
Channel Offset (MHz)
Note With off, above -2dBm erroneous RSSI values read. Cross-checking RSSI with off/on recommended accurate readings.
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CYRF7936
Typical Operating Characteristics (continued)
Data Threshold (32-8DR) (SOP Threshold slow) 0.01 0.001 0.0001 0.00001 -100
GFSK (SOP Threshold slow) %BER 0.01 0.001 0.0001 0.00001 -100
Thru
%BER
GFSK
Input Power (dBm)
Input Power (dBm)
(LNA OFF) OPERATING CURRENT (mA) OPERATING CURRENT (mA) 20.5 19.5 18.5 17.5 TEMPERATURE 24.5
(LNA
SYNTH
3.3V 3.0V 2.7V 2.4V
23.5 22.5 21.5 20.5 19.5
3.3V 3.0V 2.7V 2.4V
TEMPERATURE
OPERATING CURRENT (mA)
3.3V 3.0V 2.7V 2.4V
TEMPERATURE
SYNTH OPERATING CURRENT (mA) 16.5 15.5 14.5 TEMPERATURE
17.5 OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
3.3V 3.0V 2.7V 2.4V
3.3V 3.0V 2.7V 2.4V
16.5 15.5 14.5
3.3V 3.0V 2.7V 2.4V
TEMPERATURE
TEMPERATURE
OPERATING CURRENT (mA) 17.5 16.5 15.5 TEMPERATURE
20.5 OPERATING CURRENT (mA)
3.3V 3.0V 2.7V 2.4V
OPERATING CURRENT (mA)
18.5 17.5 16.5 15.5
3.3V 3.0V 2.7V 2.4V
19.5 18.5 17.5 16.5
3.3V 3.0V 2.7V 2.4V
TEMPERATURE
TEMPERATURE
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CYRF7936
Typical Operating Characteristics (continued)
23.5 OPERATING CURRENT (mA) OPERATING CURRENT (mA) 22.5 21.5 20.5 19.5 TEMPERATURE OPERATING CURRENT (mA) 40.5 39.5 38.5 37.5 36.5 35.5 34.5 33.5 32.5
3.3V 3.0V 2.7V 2.4V
29.5 28.5 27.5 26.5 25.5 24.5
3.3V 3.0V 2.7V 2.4V
3.3V 3.0V 2.7V 2.4V
TEMPERATURE
TEMPERATURE
Test Loads Waveforms Digital Pins
Figure Test Loads Waveforms Digital Pins
Test Loads
OUTPUT INCLUDING SCOPE OUTPUT
Test Load
OUTPUT
INCLUDING Typical SCOPE INPUT PULSES
Parameter
1071 3.00
Unit
Rise time: V/ns Equivalent OUTPUT
Fall time: V/ns
EQUIVALENT
Ordering Information
Table Ordering Information Part Number CYRF7936-40LFXC Radio Transceiver Package Name Package Type Quad Flat Package Leads Pb-Free CYRF7936 Operating Range Commercial
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CYRF7936
Package Description
Figure 40-Pin Pb-Free LY40
SOLDERABLE EXPOSED
NOTES: HATCH SOLDERABLE EXPOSED AREA
REFERENCE JEDEC#: MO-220 PACKAGE WEIGHT: 0.086g DIMENSIONS [MIN/MAX] PACKAGE CODE
UNLESS OTHERWISE SPECIFIED
(SUBCON Punch Type WITH 3.50X3.50 EPAD)
DESIGNED DRAWN APPROVED APPROVED DATE DATE
PART LF40A LY40A
DESCRIPTION STANDARD PB-FREE
DIMENSIONS INCHES [MILLIMETERS] STANDARD TOLERANCES DECIMALS ANGLES .XXX .XXXX
07/10/08
DATE
CYPRESS COMPANY CONFIDENTIAL
TITLE
DATE DATE
40LD PACKAGE OUTLINE (SUBCON PUNCH TYPE with 3.50 3.50 EPAD)
PART
MATERIAL
SIZE
001-12917
NOTES
001-12917
recommended dimension size E-PAD underneath (width length).
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CYRF7936
Document History Page
Description Title: CYRF7936 CyFiTransceiver Document 001-48013 Rev. REV.
2557501
Orig. Change
KKU/AESA
Submission Date
09/10/08 Data Sheet
Description Change
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