Download

PDF Abstract Text:

AT91 ARM Thumb-based Microcontrollers AT91SAM9261 Preliminary Summary

NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com.

Features
· Incorporates the ARM926EJ-S ARM® Thumb® Processor
- DSP Instruction Extensions - ARM Jazelle® Technology for Java® Acceleration - 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer - 210 MIPS at 190 MHz - Memory Management Unit - EmbeddedICETM, Debug Communication Channel Support - Mid-level implementation Embedded Trace Macrocell Additional Embedded Memories - 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed - 160 Kbytes of Internal SRAM, Single-cycle Access at Maximum Processor or Bus Speed External Bus Interface (EBI) - Supports SDRAM, Static Memory, NAND Flash and CompactFlash® LCD Controller - Supports Passive or Active Displays - Up to 16-bits per Pixel in STN Color Mode - Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048 USB - USB 2.0 Full Speed (12 Mbits per second) Host Double Port · Dual On-chip Transceivers · Integrated FIFOs and Dedicated DMA Channels - USB 2.0 Full Speed (12 Mbits per second) Device Port · On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs Bus Matrix - Handles Five Masters and Five Slaves - Boot Mode Select Option - Remap Command Fully Featured System Controller (SYSC) for Efficient System Management, including - Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16 Bytes - Clock Generator and Power Management Controller - Advanced Interrupt Controller and Debug Unit - Periodic Interval Timer, Watchdog Timer and Real-time Timer - Three 32-bit PIO Controllers Reset Controller (RSTC) - Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control Shutdown Controller (SHDWC) - Programmable Shutdown Pin Control and Wake-up Circuitry Clock Generator (CKGR) - 32, 768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock - 3 to 20 MHz On-chip Oscillator and two PLLs Power Management Controller (PMC) - Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities - Four Programmable External Clock Signals
AT91 ARM Thumb-based Microcontrollers AT91SAM9261 Preliminary Summary
NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com.
6062GS-ATARM-05-Dec-06
· Advanced Interrupt Controller (AIC)
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
1. Description
The AT91SAM9261 is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz. The AT91SAM9261 is an optimized host processor for applications with an LCD display. Its integrated LCD controller supports BW and up to 16M color, active and passive LCD displays. The 160 Kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for LCD refresh on the overall processor performance. The External Bus Interface incorporates controllers for synchronous DRAM (SDRAM) and Static memories and features specific interface circuitry for CompactFlash and NAND Flash. The AT91SAM9261 integrates a ROM-based Boot Loader supporting code shadowing from, for example, external DataFlash® into external SDRAM. The software controlled Power Management Controller (PMC) keeps system power consumption to a minimum by selectively enabling / disabling the processor and various peripherals and adjustment of the operating frequency. The AT91SAM9261 also benefits from the integration of a wide range of debug features including JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real time trace. This enables the development and debug of all applications, especially those with real-time constraints.
6062GS-ATARM-05-Dec-06
2. Block Diagram
Figure 2-1.
JTAGSEL TDI TDO TMS TCK NTRST RTCK
AT91SAM9261 Block Diagram
ARM926EJ-S Core
ICE Instruction Cache 16K bytes TCM Interface
Data Cache 16K bytes BIU
JTAG Boundary Scan
TSYNC TCLK TPS0-TPS2 TPK0-TPK15 BMS D0-D15 A0 / NBS0 A1 / NBS2 / NWR2 A2-A15 / A18-A21 A22 / REG A16 / BA0 A17 / BA1 NCS0 NCS1 / SDCS NCS2 NCS3 / NANDCS NRD / CFOE NWR0 / NWE / CFWE NWR1 / NBS1 / CFIOR NWR3 / NBS3 / CFIOW SDCK SDCKE RAS-CAS SDWE SDA10 NWAIT A23-A24 A25 / CFRNW NCS4 / CFCS0 NCS5 / CFCS1 CFCE1 CFCE2 NCS6 / NANDOE NCS7 / NANDWE D16-D31 HDMA HDPA HDMB HDPB
System Controller TST FIQ IRQ0-IRQ2 DRXD DTXD PCK0-PCK3 PLLRCA PLLRCB XIN XOUT AIC PIO DBGU PDC
EBI CompactFlash NAND Flash
Fast SRAM 160K bytes
PLLA PLLB OSC PMC Fast ROM 32K bytes 5-layer Matrix PIT Peripheral Bridge Peripheral DMA Controller DMA RSTC POR APB PIOA PIOB PIOC FIFO USB Device USB Host FIFO Transceiver Transceiver
SDRAM Controller
GPBREG XIN32 XOUT32 SHDN WKUP VDDBU GNDBU VDDCORE NRST POR OSC RTT SHDWC
Static Memory Controller
DDM DDP
USART0 PDC PDC
USART1
PIO PIO
SSC1 PDC PDC PIO SSC2 PDC Timer Counter TC0 TC1 TC2 TWI PDC
USART2 PDC
SPI0 PDC
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
3. Signal Description
Table 3-1.
Signal Name
Signal Description by Peripheral
Function Power Type Active Level Comments
VDDIOM VDDIOP VDDBU VDDPLL VDDOSC VDDCORE GND GNDPLL GNDOSC GNDBU
EBI I / O Lines Power Supply Peripherals I / O Lines Power Supply Backup I / O Lines Power Supply PLL Power Supply Oscillator Power Supply Core Chip Power Supply Ground PLL Ground Oscillator Ground Backup Ground
Power Power Power Power Power Power Ground Ground Ground Ground
1.65 V to 1.95V and 3.0V to 3.6V 2.7V to 3.6V 1.08V to 1.32V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V
Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 - PCK3 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output PLL Filter PLL Filter Programmable Clock Output Input Output Input Output Input Input Output
Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-Up Input Output Input ICE and JTAG TCK RTCK TDI TDO TMS NTRST JTAGSEL Test Clock Returned Test Clock Test Data In Test Data Out Test Mode Select Test Reset Signal JTAG Selection ETM TSYNC TCLK TPS0 - TPS2 Trace Synchronization Signal Trace Clock Trace ARM Pipeline Status Output Output Output Input Output Input Output Input Input Input Low No pull-up resistor. Pull-up resistor. Pull-down resistor. Accepts between 0V and VDDBU. No pull-up resistor. No pull-up resistor. No pull-up resistor. Do not tie over VDDBU. Accepts between 0V and VDDBU.
6062GS-ATARM-05-Dec-06
Table 3-1.
Signal Name TPK0 - TPK15
Signal Description by Peripheral (Continued)
Function Trace Packet Port Type Output Reset / Test Active Level Comments
NRST TST BMS
Microcontroller Reset Test Mode Select Boot Mode Select
I / O Input Input Debug Unit
Pull-up resistor Pull-down resistor.
DRXD DTXD
Debug Receive Data Debug Transmit Data AIC
Input Output
IRQ0 - IRQ2 FIQ
External Interrupt Inputs Fast Interrupt Input PIO
Input Input
PA0 - PA31 PB0 - PB31 PC0 - PC31
Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C EBI
Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset
D0 - D31 A0 - A25 NWAIT
Data Bus Address Bus External Wait Signal SMC
I / O Output Input Low
Pulled-up input at reset 0 at reset
NCS0 - NCS7 NWR0 - NWR3 NRD NWE NBS0 - NBS3
Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal
Output Output Output Output Output CompactFlash Support
Low Low Low Low Low
CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 - CFCS1
CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines
Output Output Output Output Output Output Output
Low Low Low Low Low
NAND Flash Support NANDOE NANDWE NAND Flash Output Enable NAND Flash Write Enable Output Output Low Low
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
Table 3-1.
Signal Name NANDCS
Signal Description by Peripheral (Continued)
Function NAND Flash Chip Select Type Output SDRAM Controller Active Level Low Comments
SDCK SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10
SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line
Output Output Output Output Output Output Output Multimedia Card Interface Low Low High Low
MCCK MCCDA MCDA0 - MCDA3
Multimedia Card Clock Multimedia Card A Command Multimedia Card A Data USART
SCK0 - SCK2 TXD0 - TXD2 RXD0 - RXD2 RTS0 - RTS2 CTS0 - CTS2
Serial Clock Transmit Data Receive Data Request To Send Clear To Send
I / O Output Input Output Input Synchronous Serial Controller
TD0 - TD2 RD0 - RD2 TK0 - TK2 RK0 - RK2 TF0 - TF2 RF0 - RF2
Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync
Output Input I / O I / O I / O I / O Timer / Counter
TCLK0 - TCLK2 TIOA0 - TIOA2 TIOB0 - TIOB2
External Clock Input I / O Line A I / O Line B SPI
Master In Slave Out Master Out Slave In SPI Serial Clock
6062GS-ATARM-05-Dec-06
Table 3-1.
Signal Description by Peripheral (Continued)
Function SPI Peripheral Chip Select 0 Type I / O Active Level Low Comments
SPI Peripheral Chip Select
Output
Two-Wire Interface TWD TWCK Two-wire Serial Data Two-wire Serial Clock I / O I / O LCD Controller LCDD0 - LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC LCD Data Bus LCD Vertical Synchronization LCD Horizontal Synchronization LCD Dot Clock LCD Data Enable LCD Contrast Control Output Output Output Output Output Output USB Device Port DDM DDP USB Device Port Data USB Device Port Data + Analog Analog USB Host Port HDMA HDPA HDMB HDPB USB Host Port A Data USB Host Port A Data + USB Host Port B Data USB Host Port B Data + Analog Analog Analog Analog
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
4. Package and Pinout
The AT91SAM9261 is available in a 217-ball LFBGA RoHS-compliant package, 15 x 15 mm, 0.8 mm ball pitch
217-ball LFBGA Package Outline
Figure 4-1 shows the orientation of the 217-ball LFBGA Package. A detailed mechanical description is given in the section "AT91SAM9261 Mechanical Characteristics" of the product datasheet. Figure 4-1. 217-ball LFBGA Package Outline (Top View)
Ball A1
6062GS-ATARM-05-Dec-06
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4
Pinout
AT91SAM9261 Pinout for 217-ball LFBGA Package (1)
Signal Name A19 A16 / BA0 A14 A12 A9 A6 A3 A2 NC XOUT32 XIN32 DDP HDPB HDMB PB27 GND PB24 A20 A18 A15 A13 A11 A7 A4 A1 / NBS2 / NWR2 VDDBU JTAGSEL WKUP DDM PB31 HDMA PB26 PB25 PB19 A22 A21 VDDIOM A17 / BA1 VDDIOM A8 GND VDDIOM GNDBU TST GND HDPA PB30 NC VDDIOP PB21 TMS NCS2 NCS1 / SDCS GND VDDIOM Pin D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E14 E15 E16 E17 F1 F2 F3 F4 F14 F15 F16 F17 G1 G2 G3 G4 G14 G15 G16 G17 H1 H2 H3 H4 H8 H9 H10 H14 H15 H16 H17 J1 J2 J3 J4 J8 J9 J10 Signal Name VDDCORE A10 A5 A0 / NBS0 SHDN NC VDDIOP PB29 PB28 PB23 PB20 PB17 TCK NWR1 / NBS1 / CFIOR NWR0 / NWE / CFWE NRD / CFOE SDA10 PB22 PB18 PB15 TDI SDCKE RAS NWR3 / NBS3 / CFIOW NCS0 PB16 NRST TDO NTRST D0 D1 SDWE NCS3 / NANDCS PB14 PB12 PB11 PB8 D2 D3 VDDIOM SDCK GND GND GND PB10 PB13 PB7 PB5 D4 D5 GND CAS GND GND GND Pin J14 J15 J16 J17 K1 K2 K3 K4 K8 K9 K10 K14 K15 K16 K17 L1 L2 L3 L4 L14 L15 L16 L17 M1 M2 M3 M4 M14 M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 Signal Name VDDIOP PB9 PB6 PB4 D6 D8 D10 D7 GND GND GND VDDCORE PB3 / BMS PB1 PB2 D9 D11 D12 VDDIOM PA30 PA27 PA31 PB0 D13 D15 PC18 VDDCORE PA25 PA26 PA28 PA29 D14 PC17 PC31 VDDIOM PA22 PA21 PA23 PA24 PC16 PC30 PC22 PC24 PC28 PC1 PC7 PC11 GNDPLL PA3 VDDIOP VDDCORE PA15 PA16 VDDIOP PA19 Pin P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name PA20 PC19 PC21 GND PC27 PC29 PC4 PC8 PC12 PC14 VDDPLL PA0 PA7 PA10 PA13 PA17 GND PA18 PC20 PC23 PC26 PC2 VDDIOP PC5 PC9 PC10 PC15 VDDOSC GNDOSC PA1 PA4 PA6 PA8 PA11 PA14 PC25 PC0 PC3 GND PC6 VDDIOP GND PC13 PLLRCB PLLRCA XIN XOUT PA2 PA5 PA12 PA9 RTCK
Table 4-1.
Note:
1. Shaded cells define the pins powered by VDDIOM.
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
5. Power Considerations
5.1 Power Supplies
The AT91SAM9261 has six types of power supply pins: · VDDCORE pins: Power the core, including the processor, the memories and the peripherals voltage ranges from 1.08V and 1.32V, 1.2V nominal. · VDDIOM pins: Power the External Bus Interface I / O lines voltage ranges from 1.65V to 1.95V and 3.0V to 3.6V, 1.8V and 3.3V nominal. · VDDIOP pins: Power the Peripheral I / O lines and the USB transceivers voltage ranges from 2.7V and 3.6V, 3.3V nominal. · VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller voltage ranges from 1.08V and 1.32V, 1.2V nominal. · VDDPLL pin: Powers the PLL cells voltage ranges from 3.0V and 3.6V, 3.3V nominal. · VDDOSC pin: Powers the Main Oscillator cells voltage ranges from 3.0V and 3.6V, 3.3V nominal. The double power supplies VDDIOM and VDDIOP are identified in Table 4-1 on page 10. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins GND are common to VDDCORE, VDDIOM and VDDIOP pins power supplies. Separated ground pins are provided for VDDBU, VDDOSC and VDDPLL. The ground pins are GNDBU, GNDOSC and GNDPLL, respectively.
Power Consumption
The AT91SAM9261 consumes about 550 µA of static current on VDDCORE at 25°C. This static current rises at up to 5.5 mA if the temperature increases to 85°C. On VDDBU, the current does not exceed 3 µA @25°C, but can rise at up to 20 µA @85°C. For dynamic power consumption, the AT91SAM9261 consumes a maximum of 50 mA on VDDCORE at maximum speed in typical conditions (1.2V, 25°C), processor running full-performance algorithm.
6. I / O Line Considerations
6.1 JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates a permanent pull-down resistor of about 15 k to GNDBU, so that it can be left unconnected for normal operations. The NTRST pin is used to initialize the embedded ICE TAP Controller when asserted at a low level. It integrates a permanent pull-up resistor of about 15 k to VDDIOP, so that it can be left unconnected for normal operations.
6062GS-ATARM-05-Dec-06
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 k to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results.
Reset Pin
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP. As the product integrates power-on reset cells, the NRST pin can be left unconnected in case no reset from the system needs to be applied to the product. The NRST pin integrates a permanent pull-up resistor of 100 k minimum to VDDIOP. The NRST signal is inserted in the Boundary Scan.
PIO Controller A, B and C Lines
All the I / O lines PA0 to PA31, PB0 to PB31, and PC0 to PC31 integrate a programmable pull-up resistor of 100 k. Programming of this pull-up resistor is performed independently for each I / O line through the PIO Controllers. After reset, all the I / O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripherals at reset. This is explicitly indicated in the column "Reset State" of the PIO Controller multiplexing tables.
Shutdown Logic Pins
The SHDN pin is an output only, driven by Shutdown Controller. The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU.
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
7. Processor and Architecture
7.1 ARM926EJ-S Processor
· RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration · Two Instruction Sets - ARM High-performance 32-bit Instruction Set - Thumb High Code Density 16-bit Instruction Set · DSP Instruction Extensions · 5-Stage Pipeline Architecture: - Instruction Fetch (F) - Instruction Decode (D) - Execute (E) - Data Memory (M) - Register Write (W) · 16 Kbyte Data Cache, 16 Kbyte Instruction Cache - Virtually-addressed 4-way Associative Cache - Eight words per line - Write-through and Write-back Operation - Pseudo-random or Round-robin Replacement · Write Buffer - Main Write Buffer with 16-word Data Buffer and 4-address Buffer - DCache Write-back Buffer with 8-word Entries and a Single Address Entry - Software Control Drain · Standard ARM v4 and v5 Memory Management Unit (MMU) - Access Permission for Sections - Access Permission for large pages and small pages can be specified separately for each quarter of the page - 16 embedded domains · Bus Interface Unit (BIU) - Arbitrates and Schedules AHB Requests - Separate Masters for both instruction and data access providing complete AHB system flexibility - Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface - On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
6062GS-ATARM-05-Dec-06
Debug and Test Features
· Integrated Embedded In-circuit Emulator Real-Time - Two real-time Watchpoint Units - Two Independent Registers: Debug Control Register and Debug Status Register - Test Access Port Accessible through JTAG Protocol - Debug Communications Channel · Debug Unit - Two-pin UART - Debug Communication Channel Interrupt Handling - Chip ID Register · Embedded Trace Macrocell: ETM9 - Medium+ Level Implementation - Half-rate Clock Mode - Four Pairs of Address Comparators - Two Data Comparators - Eight Memory Map Decoder Inputs - Two 16-bit Counters - One 3-stage Sequencer - One 45-byte FIFO · IEEE1149.1 JTAG Boundary-scan on All Digital Pins
Bus Matrix
· Five Masters and Five Slaves handled - Handles Requests from the ARM926EJ-S, USB Host Port, LCD Controller and the Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD Controller and USB Host Port. - Round-Robin Arbitration (three modes supported: no default master, last accessed default master, fixed default master) - Burst Breaking with Slot Cycle Limit · One Address Decoder Provided per Master - Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap. · Boot Mode Select Option - Non-volatile Boot Memory can be Internal or External. - Selection is made by BMS pin sampled at reset. · Remap Command - Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory - Allows Handling of Dynamic Exception Vectors
Peripheral DMA Controller
· Transfers from / to peripheral to / from any memory space without intervention of the processor. · Next Pointer Support, forbids strong real-time constraints on buffer management.
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
· Nineteen channels - Two for each USART - Two for the Debug Unit - Two for each Serial Synchronous Controller - Two for each Serial Peripheral Interface - One for the Multimedia Card Interface
6062GS-ATARM-05-Dec-06
8. Memories
Figure 8-1. AT91SAM9261 Memory Mapping
Address Memory Space 0x0000 0000 Internal Memories
0x0FFF FFFF 0x0000 0000
Internal Memory Mapping Boot Memory (1) 256M Bytes
0x10 0000
0x1000 0000
0x20 0000
ITCM (2) EBI Chip Select 0 256M Bytes
0x30 0000
1M Bytes
DTCM (2)
1M Bytes
0x1FFF FFFF
0x2000 0000 EBI Chip Select 1 / SDRAMC 256M Bytes
SRAM (2)
0x40 0000
1M Bytes
0x2FFF FFFF
0x3000 0000 EBI Chip Select 2
0x3FFF FFFF
ROM 256M Bytes
0x50 0000
1M Bytes
UHP User Interface EBI Chip Select 3 / NANDFlash EBI Chip Select 4 / Compact Flash Slot 0 EBI Chip Select 5 / Compact Flash Slot 1 EBI Chip Select 6
0x60 0000
1M Bytes
0x4000 0000
256M Bytes LCD User Interface
0x70 0000
1M Bytes
0x4FFF FFFF
0x5000 0000
256M Bytes
0x0FFF FFFF
Reserved
0x5FFF FFFF
0x6000 0000
256M Bytes System Controller Mapping
0xFFFF C000
0x6FFF FFFF
0x7000 0000 256M Bytes Peripheral Mapping
0xF000 0000
0x7FFF FFFF
Reserved
0x8000 0000 EBI Chip Select 7
0x8FFF FFFF
256M Bytes
0xFFFA 0000
Reserved
0xFFFF EA00
SDRAMC TCO, TC1, TC2
16K Bytes 16K Bytes 0xFFFF EE00 16K Bytes 0xFFFF F000 16K Bytes 0xFFFF F200 0xFFFF EC00
512 Bytes
0x9000 0000
0xFFFA 4000
SMC UDP
512 Bytes
0xFFFA 8000
MATRIX
512 Bytes
0xFFFA C000
0xFFFB 0000
AIC DBGU
0xFFFF F400
512 Bytes
USART0
0xFFFB 4000
16K Bytes 16K Bytes 0xFFFF F600
512 Bytes
USART1
0xFFFB 8000
512 Bytes
Undefined (Abort)
1, 518M Bytes
0xFFFB C000
USART2 SSC0
0xFFFC 0000
16K Bytes
0xFFFF F800 16K Bytes
512 bytes
0xFFFF FA00 16K Bytes
512 bytes
0xFFFC 4000
Reserved
16K Bytes 0xFFFF FC00
0xFFFC 8000
16K Bytes 16K Bytes 0xFFFF FD00
256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes
0xFFFC C000
0xFFFF FD10 0xFFFF FD20 0xFFFF FD30
SHDWC RTT PIT WDT GPBR Reserved
0xFFFC D000 0xEFFF FFFF
0xF000 0000 Internal Peripherals
0xFFFF FFFF
Reserved 256M Bytes
0xFFFF C000
0xFFFF FD40 0xFFFF FD50 0xFFFF FD60
0xFFFF FFFF
16K Bytes 0xFFFF FFFF
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 areas of 256 Mbytes. The areas 1 to 8 are directed to the EBI that associates these areas to the external chip selects NCS0 to NCS7. The area 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. The area 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. The Bus Matrix manages five Masters and five Slaves. Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap. Refer to Table 8-3 for details. Table 8-1.
Master 0 Master 1 Master 2 Master 3 Master 4
List of Bus Matrix Masters
ARM926 Instruction ARM926 Data PDC LCD Controller USB Host
Each Slave has its own arbiter, thus allowing a different arbitration per Slave. Table 8-2.
Slave 0 Slave 1 Slave 2 Slave 3 Slave 4
List of Bus Matrix Slaves
Internal SRAM Internal ROM LCD Controller and USB Host Port Interfaces External Bus Interface Internal Peripherals
Embedded Memories
· 32 KB ROM - Single Cycle Access at full bus speed · 160 KB Fast SRAM - Single Cycle Access at full bus speed - Supports ARM926EJ-S TCM interface at full processor speed
6062GS-ATARM-05-Dec-06
Internal Memory Mapping Table 8-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the BMS state at reset. Internal Memory Mapping
Table 8-3.
Address
0x0000 0000 Note:
Int. ROM
1. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is defined by the reset state of SMC Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers.
Internal SRAM The AT91SAM9261 embeds a high-speed 160 Kbyte SRAM. This Internal SRAM is split into three areas. Its Memory Mapping is detailed in Table 8-3 above. · Internal SRAM A is the ARM926EJ-S Instruction TCM and the user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0010 0000. · Internal SRAM B is the ARM926EJ-S Data TCM and the user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0020 0000. · Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926 Data Masters. Within the 160 Kbyte SRAM size available, the amount of memory assigned to each block is software programmable as a multiple of 16 Kbytes according to Table 8-4. This table provides the size of the Internal SRAM C according to the size of the Internal SRAM A and the Internal SRAM B.
Table 8-4.
Internal SRAM Block Size
Internal SRAM A (ITCM) Internal SRAM C 0 16 Kbytes 32 Kbytes 0 160 Kbytes 144 Kbytes 128 Kbytes 96 Kbytes 16 Kbytes 144 Kbytes 128 Kbytes 112 Kbytes 80 Kbytes 32 Kbytes 128 Kbytes 112 Kbytes 96 Kbytes 64 Kbytes 64 Kbytes 96 Kbytes 80 Kbytes 64 Kbytes 32 Kbytes
Internal SRAM B (DCTM)
64 Kbytes
Note that among the ten 16 Kbyte blocks making up the Internal SRAM, two are permanently assigned to Internal SRAM C. At reset, the whole memory (160 Kbytes) is assigned to Internal SRAM C.
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and when the user dynamically changes the Internal SRAM configuration, the new 16 Kbyte block organization may affect the previous configuration from a software point of view. Table 8-5 illustrates different configurations and the related 16 Kbyte blocks (RB0 to RB9) assignments. Table 8-5. 16 Kbyte Block Allocation
Address 0x0010 0000
Internal SRAM A (ITCM)
0x0010 4000 0x0010 8000 0x0010 C000 0x0020 0000
Internal SRAM B (DTCM)
0x0020 4000 0x0020 8000 0x0020 C000 0x0030 0000 0x0030 4000 0x0030 8000 0x0030 C000
Internal SRAM C (AHB)
0x0031 0000 0x0031 4000 0x0031 8000 0x0031 C000 0x0032 0000 0x0032 4000
Note:
1. Configuration after reset.
Internal ROM The AT91SAM9261 integrates a 32 Kbyte Internal ROM mapped at address 0x0040 0000. It is also accessible at address 0x0 after reset and before remap if the BMS is tied high during reset. USB Host Port The AT91SAM9261 integrates a USB Host Port Open Host Controller Interface (OHCI). The registers of this interface are directly accessible on the AHB Bus and are mapped like a standard internal memory at address 0x0050 0000. LCD Controller The AT91SAM9261 integrates an LCD Controller. The interface is directly accessible on the AHB Bus and is mapped like a standard internal memory at address 0x0060 0000.
6062GS-ATARM-05-Dec-06
Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 8-1 on page 21.
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
4. Switch the main clock to the new value. 8.1.3 ETM Memories The eight ETM9 Medium+ memory map decoder inputs are connected to custom address decoders and the resulting memory mapping is summarized in Table 8-6. Table 8-6. ETM9 Memory Mapping
Area Internal Internal Internal Internal External External Internal Internal Access Type Data Fetch Data Fetch Data Fetch Data Data Start Address 0x0000 0000 0x0000 0000 0x0040 0000 0x0040 0000 0x1000 0000 0x1000 0000 0xF000 0000 0xFFFF C000 End Address 0x002F FFFF 0x002F FFFF 0x004F FFFF 0x004F FFFF 0x8FFF FFFF 0x8FFF FFFF 0xFFFF BFFF 0xFFFF FFFF
Product Resource SRAM SRAM ROM ROM External Bus Interface External Bus Interface User Peripherals System Peripherals
External Memories
The external memories are accessed through the External Bus Interface (Bus Matrix Slave 3). Refer to the memory map in Figure 8-1 on page 16.
6062GS-ATARM-05-Dec-06
9. System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Peripherals are all mapped within the highest 6 Kbytes of address space, between addresses 0xFFFF EA00 and 0xFFFF FFFF. Each peripheral has an address space of 256 or 512 Bytes, representing 64 or 128 registers. Figure 9-1 on page 23 shows the System Controller block diagram. Figure 8-1 on page 16 shows the mapping of the User Interfaces of the System Controller peripherals.
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
9.1 Block Diagram
System Controller Block Diagram
Figure 9-1.
ntrst
ARM926EJ-S
Boundary Scan TAP Controller
Reset Controller
VDDBU POR
SHDN WKUP
Shutdown Controller
XIN32 XOUT32 XIN XOUT PLLRCA PLLRCB
SLOW CLOCK OSC
LCD Controller
PLLACK PLLBCK
PA0-PA31 PB0-PB31 PC0-PC31
PIO Controllers
in out enable
6062GS-ATARM-05-Dec-06
Reset Controller
· Based on two Power-on-Reset cells · Status of the last reset - Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset · Controls the internal resets and the NRST pin output
Shutdown Controller
· Shutdown and Wake-up logic: - Software programmable assertion of the SHDN pin - Deassertion Programmable on a WKUP pin level change or on alarm
General-purpose Backup Registers
· Four 32-bit general-purpose backup registers
Clock Generator
· Embeds the Low-power 32768 Hz Slow Clock Oscillator - Provides the permanent Slow Clock to the system · Embeds the Main Oscillator - Oscillator bypass feature - Supports 3 to 20 MHz crystals · Embeds Two PLLs - Outputs 80 to 240 MHz clocks - Integrates an input divider to increase output accuracy - 1 MHz minimum input frequency · Provides SLCK, MAINCK, PLLACK and PLLBCK. Figure 9-2. Clock Generator Block Diagram
Clock Generator XIN32 XOUT32 XIN XOUT Main Oscillator Main Clock MAINCK Slow Clock Oscillator Slow Clock SLCK
PLLRCA
PLL and Divider A PLL and Divider B Status Control
PLLA Clock PLLACK PLLB Clock PLLBCK
PLLRCB
Power Management Controller
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
9.6 Power Management Controller
· The Power Management Controller provides: - the Processor Clock PCK - the Master Clock MCK - the USB Clock USBCK - the LCD Controller Clock LCDCK - up to thirty peripheral clocks - four programmable clock outputs: PCK0 to PCK3 Figure 9-3. Power Management Controller Block Diagram
LCDCK
PLLBCK
USB Clock Controller ON / OFF Divider / 1, / 2, / 4
Periodic Interval Timer
· Includes a 20-bit Periodic Counter with less than 1 µs accuracy · Includes a 12-bit Interval Overlay Counter · Real time OS or Linux® / WindowsCE® compliant tick generator
Watchdog Timer
· 12-bit key-protected only-once programmable counter · Windowed, prevents the processor to be in a dead-lock on the watchdog access
Real-time Timer
· 32-bit Free-running backup counter · Alarm Register capable to generate a wake-up of the system
6062GS-ATARM-05-Dec-06
Advanced Interrupt Controller
· Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor · Thirty-two individually maskable and vectored interrupt sources - Source 0 is reserved for the Fast Interrupt Input (FIQ) - Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) - Source 2 to Source 31 control up to thirty embedded peripheral interrupts or external interrupts - Programmable edge-triggered or level-sensitive internal sources - Programmable positive / negative edge-triggered or high / low level-sensitive · Four External Sources · 8-level Priority Controller - Drives the normal interrupt of the processor - Handles priority of the interrupt sources 1 to 31 - Higher priority interrupts can be served during service of lower priority interrupt · Vectoring - Optimizes Interrupt Service Routine Branch and Execution - One 32-bit Vector Register per interrupt source - Interrupt Vector Register reads the corresponding current Interrupt Vector · Protect Mode - Easy debugging by preventing automatic operations when protect mode is enabled · Fast Forcing - Permits redirecting any normal interrupt source on the Fast Interrupt of the processor · General Interrupt Mask - Provides processor synchronization on events without triggering an interrupt
Debug Unit
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
PIO Controllers
· Three PIO Controllers, each controlling up to 32 programmable I / O Lines - PIOA has 32 I / O Lines - PIOB has 32 I / O Lines - PIOC has 32 I / O Lines · Fully programmable through Set / Clear Registers · Multiplexing of two peripheral functions per I / O Line · For each I / O Line (whether assigned to a peripheral or used as general-purpose I / O) - Input change interrupt - Glitch filter - Multi-drive option enables driving in open drain - Programmable pull up on each I / O line - Pin data status register, supplies visibility of the level on the pin at any time · Synchronous output, provides Set and Clear of several I / O lines in a single write
6062GS-ATARM-05-Dec-06
10. Peripherals
10.1 User Interface
The User Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 16.
Peripheral Identifiers
Table 10-1 defines the Peripheral Identifiers of the AT91SAM9261. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller.
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
Table 10-1.
Peripheral Identifiers
Peripheral Mnemonic AIC SYSIRQ PIOA PIOB PIOC US0 US1 US2 MCI UDP TWI SPI0 SPI1 SSC0 SSC1 SSC2 TC0 TC1 TC2 UHP LCDC AIC AIC AIC Peripheral Name Advanced Interrupt Controller System Interrupt Parallel I / O Controller A Parallel I / O Controller B Parallel I / O Controller C Reserved USART 0 USART 1 USART 2 Multimedia Card Interface USB Device Port Two-Wire Interface Serial Peripheral Interface 0 Serial Peripheral Interface 1 Synchronous Serial Controller 0 Synchronous Serial Controller 1 Synchronous Serial Controller 2 Timer / Counter 0 Timer / Counter 1 Timer / Counter 2 USB Host Port LCD Controller Reserved Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 IRQ2 External Interrupt FIQ
Note:
Setting AIC, SYSIRQ, UHP, LCDC and IRQ0 to IRQ2 bits in the clock set / clear registers of the PMC has no effect.
Peripheral Multiplexing on PIO Lines
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
· using NCS4 and / or NCS5 to access other parallel devices 10.3.1.7 SPI0 and the MultiMedia Card Interface As the DataFlash Card is compatible with the SDCard, it is useful to multiplex SPI and MCI. Here, the SPI0 signal is multiplexed with the MCI. USARTs · Using the USART1 and USART2 control signals prevents using the ETM. · Alternatively, using USART0 with its control signals prevents using some clock outputs and interrupt lines. 10.3.1.9 Clock Outputs · Using the clock outputs multiplexed with the PIO A prevents using the Debug Unit and / or the Two Wire Interface. · Alternatively, using the second implementation of the clock outputs prevents using the LCD Controller Interface and / or USART0. 10.3.1.10 Interrupt Lines · Using FIQ prevents using the USART0 control signals. · Using IRQ0 prevents using the NWAIT EBI signal. · Using the IRQ1 and / or IRQ2 prevents using the SPI1.
6062GS-ATARM-05-Dec-06
PIO Controller A Multiplexing Multiplexing on PIO Controller A
Table 10-2.
I / O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
Peripheral B MCDA0 MCCDA MCCK
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
10.3.3 PIO Controller B Multiplexing Multiplexing on PIO Controller B
Table 10-3.
6062GS-ATARM-05-Dec-06
PIO Controller C Multiplexing Multiplexing on PIO Controller C
Table 10-4.
I / O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31
Peripheral A NANDOE NANDWE NWAIT A25 / CFRNW NCS4 / CFCS0 NCS5 / CFCS1 CFCE1 CFCE2 TXD0 RXD0 RTS0 CTS0 TXD1 RXD1 TXD2 RXD2 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
Peripheral B NCS6 NCS7 IRQ0
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
10.3.5 System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: · the SDRAM Controller · the Debug Unit · the Periodic Interval Timer · the Real-Time Timer · the Watchdog Timer · the Reset Controller · the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.3.6 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs.
External Bus Interface
6062GS-ATARM-05-Dec-06
Static Memory Controller
· External memory mapping, 256 Mbyte address space per Chip Select Line · Up to Eight Chip Select Lines · 8-, 16- or 32-bit Data Bus · Multiple Access Modes supported - Byte Write or Byte Select Lines - Asynchronous read in Page Mode supported (4- up to 32-byte page size) · Multiple device adaptability - Compliant with LCD Module - Control signal programmable setup, pulse and hold time for each Memory Bank · Multiple Wait State Management - Programmable Wait State Generation - External Wait Request - Programmable Data Float Time · Slow Clock Mode Supported
SDRAM Controller
· Supported Devices - Standard and Low Power SDRAM (Mobile SDRAM) · Numerous configurations supported - 2K, 4K, 8K Row Address Memory Parts - SDRAM with two or four Internal Banks - SDRAM with 16- or 32-bit Data Path · Programming Facilities - Word, half-word, byte access - Automatic page break when Memory Boundary has been reached - Multibank Ping-pong Access - Timing parameters specified by software - Automatic refresh operation, refresh rate is programmable · Energy-saving Capabilities - Self-refresh, power down and deep power down modes supported · Error detection - Refresh Error Interrupt · SDRAM Power-up Initialization by software · CAS Latency of 1, 2 and 3 supported · Auto Precharge Command not used
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
10.7 Serial Peripheral Interface
· Supports communication with serial external devices - Four chip selects with external decoder support allow communication with up to fifteen peripherals - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors · Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection · Very fast transfers supported - Transfers with baud rates up to MCK - The chip select line may be left active to speed up transfers on the same device
Two-wire Interface
· Compatibility with standard two-wire serial memory · One, two or three bytes for slave address · Sequential read / write operations
USART
6062GS-ATARM-05-Dec-06
- Communication at up to 115.2 Kbps · Test Modes - Remote Loopback, Local Loopback, Automatic Echo
10.10 Synchronous Serial Controller
· Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader and more). · Contains an independent receiver and transmitter and a common clock divider. · Offers a configurable frame sync and data length. · Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal. · Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal.
10.11 Timer Counter
· Three 16-bit Timer Counter Channels · Wide range of functions including: - Frequency Measurement - Event Counting - Interval Measurement - Pulse Generation - Delay Timing - Pulse Width Modulation - Up / down Capabilities · Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input / output signals · Two global registers that act on all three TC Channels
10.12 Multimedia Card Interface
· Compatibility with MultiMedia Card Specification Version 2.2 · Compatibility with SD Memory Card Specification Version 1.0 · Cards clock rate up to Master Clock divided by 2 · Embedded power management to slow down clock rate when not used · Each MCI has two slots, each supporting - One slot for one MultiMedia Card bus (up to 30 cards) or - One SD Memory Card · Support for stream, block and multi-block data read and write
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
10.13 USB
10.14 LCD Controller
· Single and Dual scan color and monochrome passive STN LCD panels supported · Single scan active TFT LCD panels supported. · 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported · Up to 24-bit single scan TFT interfaces supported · Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays · 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN · 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN · 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT · Single clock domain architecture · Resolution supported up to 2048 x 2048
6062GS-ATARM-05-Dec-06
11. Ordering Information
Table 11-1. AT91SAM9261 Ordering Information
Package BGA217 Package Type RoHS-compliant Temperature Operating Range Industrial -40°C to 85°C Ordering Code AT91SAM9261-CJ
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
AT91SAM9261 Preliminary
12. Revison History
Table 12-1.
Doc. Rev. 6062AS
Revision History
Source Comments Qualified / Internal: 23-Aug-04 Date: 02-Jun-05 CSR 04-370 CSR 04-371 CSR 04-376 CSR 04-446 CSR 04-447 CSR 04-461 CSR 04-475 Removed "Embedded Software Services" on page 18. Change to Additional Embedded Memories in "Features" on page 1. Change to Section 5.2 "Power Consumption" on page 11. Change to Table 8-3 on page 18. Change to AIC, "Features" on page 1, SMCS signal added to Table 3-1, "Signal Description by Peripheral, " on page 5, Change to Section 10.3.1.5 "NAND Flash Interface" on page 30. Added NTRST signal to"Block Diagram" on page 4. NTRST signal added to Table 3-1 on page 5. F1 modified in Table 4-1 on page 10. Change to "JTAG Port Pins" on page 11. Changed ROM access to single cycle in "Features" on page 1 and Section 8.1 "Embedded Memories" on page 17. Replaced "PDMA" with "PDC" throughout. Replaced "Peripheral DMA" with "Peripheral DMA Controller" throughout. New pinout for 217-ball LFBGA package, Table 2 updated. Updated Section 8.1.2 "Boot Program" on page 20.
6062BS CSR 05-023
Changed min voltage level for VDDIOM and VDDIOP to 2.7V throughout. Corrected nominal voltage level for VDDIOP and VDDIOP in Section 5.1 "Power Supplies" on page 11. Added information on chip select assignment management in Section 10.4 "External Bus Interface" on page 35.
CSR 05-024 Added information on configuration management of embedded pad pull-up in Section 10.13 "USB" on page 39. Throughout document: All references to SmartMedia removed and replaced by NAND Flash. All signals SMxx changed to NANDxx. Throughout document: Package now qualified as RoHS-compliant Changed pull-up resistor level to 10 kOhm in Section 6.4 "PIO Controller A, B and C Lines" on page 12. Changed typical conditions for VDDCORE to 1.2V in Section 5.2 "Power Consumption" on page 11. Corrected BMS state in Table 8-3, "Internal Memory Mapping, " on page 18. Corrected BMS reset condition for ROM access in Section 8.1.1.2 "Internal ROM" on page 19. Date: 15-Nov-05 Changed SPI pin names in Figure 2-1, "AT91SAM9261 Block Diagram, " on page 4, Table 31, "Signal Description by Peripheral, " on page 5, Table 10-2, "Multiplexing on PIO Controller A, " on page 32, Table 10-3, "Multiplexing on PIO Controller B, " on page 33 and Table 10-4, "Multiplexing on PIO Controller C, " on page 34. Updated A22 pin in Figure 2-1, "AT91SAM9261 Block Diagram, " on page 4. Changed value of programmable pull-up resistor in Section 6.4 "PIO Controller A, B and C Lines" on page 12. Updated Table 11-1, "AT91SAM9261 Ordering Information, " on page 40.
CSR 05-398 6062CS CSR 05-481 CSR 05-496 CSR 05-487
6062GS-ATARM-05-Dec-06
Table 12-1.
Doc. Rev.
Revision History
Source Comments Corrected MIPS and speed on page 1.
6062DS 2292 2946 2475 6062ES 2474 2480 3068 3147 6062FS 3067 3503 3660, 3695 6062GS 3660
AT91SAM9261 Preliminary
6062GS-ATARM-05-Dec-06
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF / Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics / Imaging / Hi-Rel MPU / High-Speed Converters / RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC / ASSP / Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com / literature
6062GS-ATARM-05-Dec-06