AT91 Thumb Microcontrollers AT91SAM9260 Summary Preliminary NOTE:

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AT91 Thumb Microcontrollers AT91SAM9260 Summary Preliminary NOTE:

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Instruction Extensions, Jazelle® Technology Java® Acceleration 8-KByte Data Cache, 8-KByte Instruction Cache, Write Buffer MIPS Memory Management Unit EmbeddedICETM, Debug Communication Channel Support Additional Embedded Memories KByte Internal ROM, Single-cycle Access Maximum Matrix Speed KByte Internal SRAM, Single-cycle Access Maximum Matrix Speed External Interface (EBI) Supports SDRAM, Static Memory, ECC-enabled NAND Flash CompactFlash® Full Speed Mbits second) Device Port On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM Full Speed Mbits second) Host Single Port 208-lead PQFP Package Double Port 217-ball LFBGA Package Single Dual On-chip Transceivers Integrated FIFOs Dedicated Channels Ethernet 10/100 Base Media Independent Interface Reduced Media Independent Interface 28-byte FIFOs Dedicated Channels Receive Transmit Image Sensor Interface ITU-R 601/656 External Interface, Programmable Frame Capture Rate 12-bit Data Interface Support High Sensibility Sensors Synchronization, Preview Path with Scaler, YCbCr Format Matrix 32-bit-layer Matrix Boot Mode Select Option, Remap Command Fully-featured System Controller, including Reset Controller, Shutdown Controller Four 32-bit Battery Backup Registers Total Bytes Clock Generator Power Management Controller Advanced Interrupt Controller Debug Unit Periodic Interval Timer, Watchdog Timer Real-time Timer Reset Controller (RSTC) Based Power-on Reset Cell, Reset Source Identification Reset Output Control Clock Generator (CKGR) Selectable 32,768 Low-power Oscillator Internal Power Oscillator Battery Backup Power Supply, Providing Permanent Slow Clock On-chip Oscillator, Power Management Controller (PMC) Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources Three External Interrupt Sources Fast Interrupt Source, Spurious Interrupt Protected
AT91 Thumb Microcontrollers AT91SAM9260 Summary Preliminary
NOTE: This summary document. complete document available Atmel website www.atmel.com.
6221DS-ATARM-22-Sep-06
Debug Unit (DBGU)
2-wire UART Support Debug Communication Channel, Programmable Access Prevention
Periodic Interval Timer (PIT)
20-bit Interval Timer plus 12-bit Interval Counter
Watchdog Timer (WDT) Key-protected, Programmable Only Once, Windowed 16-bit Counter Running Slow Clock Real-time Timer (RTT) 32-bit Free-running Backup Counter Running Slow Clock with 16-bit Prescaler 4-channel 10-bit Analog-to-Digital Converter Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC) Programmable Lines Multiplexed with Peripheral I/Os Input Change Interrupt Capability Each Line Individually Programmable Open-drain, Pull-up Resistor Synchronous Output High-current Drive Lines, Each Peripheral Controller Channels (PDC) Two-slot MultiMedia Card Interface (MCI) SDCard/SDIO MultiMediaCardCompliant Automatic Protocol Control Fast Automatic Data Transfers with Synchronous Serial Controller (SSC) Independent Clock Frame Sync Signals Each Receiver Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Four Universal Synchronous/Asynchronous Receiver Transmitters (USART) Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding Support ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Full Modem Signal Control USART0 2-wire UARTs Master/Slave Serial Peripheral Interfaces (SPI) 16-bit Programmable Data Length, Four External Peripheral Chip Selects Synchronous Communications Three-channel 16-bit Timer/Counters (TC) Three External Clock Inputs, Multi-purpose Pins Channel Double Generation, Capture/Waveform Mode, Up/Down Capability High-Drive Capability Outputs TIOA0, TIOA1, TIOA2 Two-wire Interface (TWI) Master, Multi-master Slave Mode Operation General Call Supported Slave Mode IEEE® 1149.1 JTAG Boundary Scan Digital Pins Required Power Supplies: 1.65V 1.95V VDDBU, VDDCORE VDDPLL 1.65V 3.6V VDDIOP1 (Peripheral I/Os) 3.0V 3.6V VDDIOP0 VDDANA (Analog-to-digital Converter) Programmable 1.65V 1.95V 3.0V 3.6V VDDIOM (Memory I/Os) Available 208-lead PQFP Green 217-ball LFBGA RoHS-compliant Package
AT91SAM9260 Preliminary
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AT91SAM9260 Preliminary
Description
AT91SAM9260 based integration ARM926EJ-S processor with fast memories wide range peripherals. AT91SAM9260 embeds Ethernet MAC, Device Port, Host controller. also integrates several standard peripherals, such USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, MultiMedia Card Interface. AT91SAM9260 architectured 6-layer matrix, allowing maximum internal bandwidth 32-bit buses. also features External Interface capable interfacing with wide range memory devices.
AT91SAM9260 Block Diagram
block diagram shows features 217-LFBGA package. Some functions accessible 208-pin PQFP package unavailable pins highlighted "Multiplexing Controller page "Multiplexing Controller page "Multiplexing Controller page Host Port available 208-pin package. Table page defines multiplexed multiplexed pins available 208-PQFP package.
Table 2-1.
Unavailable Signals 208-lead PQFP Package
PA30 PA31 PB12 PB13 PC12 Peripheral HDPB HDMB SCK2 SCK0 TXD5 RXD5 IRQ0 Peripheral RXD4 TXD4 ISI_D10 ISI_D11 PCK1 SPI1_NPCS3 NCS7
6221DS-ATARM-22-Sep-06
Figure 2-1.
ETXC ECXE ERRS ERXE
MASTER
SLAVE
IRQ0-IRQ2 DRXD DTXD PCK0-PCK1 PLLRCA
Filter
System Controller DBGU
JTAG Selection Boundary Scan Transc.
In-Circuit Emulator
NPCS NPCS3 NPCS2 IOA2
AT91SAM9260 Preliminary
6221DS-ATARM-22-Sep-06
AT91SAM9260 Block Diagram
Transc.
ARM926EJ-S Processor
ICache Kbytes Interface DCache Kbytes
10/100 Ethernet
FIFO FIFO
Image Sensor Interface
OHCI
PLLA PLLB OSCSEL XIN32 XOUT32 SHDN WKUP VDDBU VDDCORE NRST 4GPREG PIOA SHDC RSTC PIOB PIOC Kbytes
XOUT
6-layer Matrix
Fast SRAM Kbytes
Fast SRAM Kbytes
Peripheral Bridge
22-channel Peripheral
CompactFlash NAND Flash
SDRAM Controller USART0 USART1 USART2 USART3 USART4 USART5 SPI0 SPI1 4-channel 10-bit DPRAM Device Static Memory Controller Controller Transceiver
D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18-A20 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NWR0/NWE NWR1/NBS1 NWR3/NBS3 SDCK, SDCKE RAS, SDWE, SDA10 NANDOE, NANDWE A21/NANDALE A22/NANDCLE D16-D31 NWAIT A23-A24 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW CFCE1-CFCE2 NCS2, NCS6, NCS7 NCS3/NANDCS
TXD0- DSD5 DCR0
SPI0_, SPI1_
AT91SAM9260 Preliminary
Signal Description
Table 3-1.
Signal Name
Signal Description List
Function Power Supplies Type Active Level Comments
VDDIOM VDDIOP0 VDDIOP1 VDDBU VDDANA VDDPLL VDDCORE GNDPLL GNDANA GNDOSC GNDBU
Lines Power Supply Peripherals Lines Power Supply Peripherals Lines Power Supply Backup Lines Power Supply Analog Power Supply Power Supply Core Chip Power Supply Ground Ground Analog Ground Oscillator Ground Backup Ground
Power Power Power Power Power Power Power Ground Ground Ground Ground Ground
1.65V 1.95V 3.0V to3.6V 3.0V 3.6V 1.65V 3.6V 1.65V 1.95V 3.0V 3.6V 1.65V 1.95V 1.65V 1.95V
Clocks, Oscillators PLLs XOUT XIN32 XOUT32 OSCSEL PLLRCA PCK0 PCK1 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Slow Clock Oscillator Selection Filter Programmable Clock Output Input Output Input Output Input Input Output Accepts between VDDBU.
Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-up Input JTAG NTRST JTAGSEL Test Reset Signal Test Clock Test Data Test Data Test Mode Select JTAG Selection Input Input Input Output Input Input pull-up resistor Pull-down resistor. Accepts between VDDBU. Pull-up resistor pull-up resistor pull-up resistor Output Input Driven only. over VDDBU. Accepts between VDDBU.
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Table 3-1.
Signal Name RTCK
Signal Description List (Continued)
Function Return Test Clock Reset/Test Type Output Active Level Comments
NRST
Microcontroller Reset Test Mode Select Boot Mode Select Debug Unit DBGU
Input Input
Pull-up resistor Pull-down resistor. Accepts between VDDBU.
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
Advanced Interrupt Controller IRQ0 IRQ2 External Interrupt Inputs Fast Interrupt Input Input Input
Controller PIOA PIOB PIOC PA31 PB31 PC31 Parallel Controller Parallel Controller Parallel Controller Pulled-up input reset Pulled-up input reset Pulled-up input reset
External Interface NWAIT Data Address External Wait Signal Output Input Pulled-up input reset reset
Static Memory Controller NCS0 NCS7 NWR0 NWR3 NBS0 NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output CompactFlash Support CFCE1 CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 CFCS1 CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash Read CompactFlash Write CompactFlash Read Write CompactFlash Chip Select Lines Output Output Output Output Output Output Output
NAND Flash Support NANDCS NAND Flash Chip Select Output
AT91SAM9260 Preliminary
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AT91SAM9260 Preliminary
Table 3-1.
Signal Name NANDOE NANDWE NANDALE NANDCLE
Signal Description List (Continued)
Function NAND Flash Output Enable NAND Flash Write Enable NAND Flash Address Latch Enable NAND Flash Command Latch Enable Type Output Output Output Output Active Level Comments
SDRAM Controller SDCK SDCKE SDCS SDWE SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Column Signal SDRAM Address Line Output Output Output Output Output Output Output High
Multimedia Card Interface MCCK MCCDA MCDA0 MCDA3 MCCDB MCDB0 MCDB3 Multimedia Card Clock Multimedia Card Slot Command Multimedia Card Slot Data Multimedia Card Slot Command Multimedia Card Slot Data Output
Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx TXDx RXDx RTSx CTSx DTR0 DSR0 DCD0 USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request Send USARTx Clear Send USART0 Data Terminal Ready USART0 Data Ready USART0 Data Carrier Detect USART0 Ring Indicator Input Output Input Output Input Input Input
Synchronous Serial Controller Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync Output Input
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Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Timer/Counter Active Level Comments
TCLKx TIOAx TIOBx
Channel External Clock Input Channel Line Channel Line
Input
Serial Peripheral Interface SPIx_ SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1-SPIx_NPCS3 Master Slave Master Slave Serial Clock Peripheral Chip Select Peripheral Chip Select Output
Two-Wire Interface TWCK Two-wire Serial Data Two-wire Serial Clock Host Port HDPA HDMA HDPB HDMB Host Port Data Host Port Data Host Port Data Host Port Data Device Port Device Port Data Device Port Data Ethernet 10/100 ETXCK ERXCK ETXEN ETX0-ETX3 ETXER ERXDV ERX0-ERX3 ERXER ECRS ECOL EMDC EMDIO EF100 Transmit Clock Reference Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Receive Data Receive Error Carrier Sense Data Valid Collision Detect Management Data Clock Management Data Input/Output Force 100Mbit/sec. Input Input Output Output Output Input Input Input Input Input Output Output High only only ETX0-ETX1 only RMII only RXDV CRSDV RMII ERX0-ERX1 only RMII only, REFCK RMII only Analog Analog Analog Analog Analog Analog
AT91SAM9260 Preliminary
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AT91SAM9260 Preliminary
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Image Sensor Interface Active Level Comments
ISI_D0-ISI_D11 ISI_MCK ISI_HSYNC ISI_VSYNC ISI_PCK
Image Sensor Data Image Sensor Reference Clock Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data clock
Input Output Input Input Input
Analog Digital Converter AD0-AD3 ADVREFP ADTRG Analog Inputs Analog Positive Reference Trigger Analog Analog Input Digital pulled-up inputs reset
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Package Pinout
AT91SAM9260 available packages: 208-pin PQFP Green package (0.5mm pitch) (Figure 4-1) 217-ball LFBGA RoHS-compliant package (0.8 ball pitch) (Figure 4-2).
208-pin PQFP Package Outline
Figure shows orientation 208-pin PQFP package. detailed mechanical description given section "AT91SAM9260 Mechanical Characteristics" product datasheet. Figure 4-1. 208-pin PQFP Package
AT91SAM9260 Preliminary
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AT91SAM9260 Preliminary
208-pin PQFP Pinout
Pinout 208-pin PQFP Package
Signal Name PA24 PA25 PA26 PA27 VDDIOP0 PA28 PA29 VDDIOP0 PB14 PB15 PB16 VDDIOP0 PB17 PB18 PB19 VDDIOP0 NTRST NRST RTCK VDDCORE OSCSEL JTAGSEL GNDBU XOUT32 XIN32 VDDBU WKUP SHDN HDMA HDPA VDDIOP0 Signal Name PC13 PC11 PC10 PC14 VDDIOM NCS0 CFOE/NRD CFWE/NWE/NWR0 NANDOE NANDWE VDDCORE BA1/A17 BA0/A16 VDDIOM NWR2/NBS2/A1 NBS0/A0 SDA10 CFIOW/NBS3/NWR3 CFIOR/NBS1/NWR1 SDCS/NCS1 Signal Name VDDIOM SDCK SDWE SDCKE PC15 PC16 PC17 PC18 PC19 VDDIOM PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 VDDCORE VDDPLL XOUT GNDPLL GNDPLL PLLRCA VDDPLL GNDANA Signal Name ADVREFP VDDANA PB10 PB11 PB20 PB21 PB22 PB23 PB24 PB25 VDDIOP1 PB26 PB27 VDDCORE PB28 PB29 PB30 PB31 VDDIOP0 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 VDDIOP0 PA18 PA19 VDDCORE PA20 PA21 PA22 PA23
Table 4-1.
6221DS-ATARM-22-Sep-06
217-ball LFBGA Package Outline
Figure shows orientation 217-ball LFBGA package. detailed mechanical description given section "AT91SAM9260 Mechanical Characteristics" product datasheet. Figure 4-2. 217-ball LFBGA Package (Top View)
Ball
AT91SAM9260 Preliminary
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AT91SAM9260 Preliminary
217-ball LFBGA Pinout
Pinout 217-ball LFBGA Package
Signal Name
CFIOW/NBS3/NWR3 NBS0/A0 NWR2/NBS2/A1 BA0/A16 CFWE/NWE/NWR0 CFOE/NRD NCS0 SDCK CFIOR/NBS1/NWR1 SDCS/NCS1 SDA10 NANDWE PC10 PC13 PC11 PC14 WKUP BA1/A17 NANDOE PC12 HDMB VDDIOP0 SHDN
Table 4-2.
Signal Name
VDDCORE VDDIOM HDPB VDDBU XIN32 HDPA HDMA GNDBU XOUT32 SDWE OSCSEL JTAGSEL PC15 SDCKE VDDIOM NRST RTCK PC18 VDDCORE NTRST PB18 PC19 PC17 VDDIOM PC16
Signal Name
PB19 PB16 PC24 PC20 PC21 PB17 PB15 PC26 PC25 VDDIOP0 PA28 PB14 VDDCORE PC31 PC22 VDDPLL PC23 PC27 PA31 PA30 XOUT VDDPLL PC30 PC28 PB11 PB13 PB24 VDDIOP1 PB30 PB31 PA26 PA25
Signal Name
GNDANA PC29 VDDANA PB12 PB23 PB26 PB28 PA10 PA21 PA23 PA24 PA29 PLLRCA GNDPLL PB10 PB22 PB29 PA11 VDDCORE PA20 PA22 PA27 GNDPLL ADVREFP PB20 PB21 PB25 PB27 PA12 PA13 PA14 PA15 PA19 PA17 PA16 PA18 VDDIOP0
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Power Considerations
Power Supplies
AT91SAM9260 several types power supply pins: VDDCORE pins: Power core, including processor, embedded memories peripherals; voltage ranges from 1.65V 1.95V, 1.8V nominal. VDDIOM pins: Power External Interface lines; voltage ranges between 1.65V 1.95V (1.8V typical) between 3.0V 3.6V (3.3V nominal). expected voltage range selectable software. VDDIOP0 pins: Power Peripheral lines transceivers; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDIOP1 pins: Power Peripherals lines involving Image Sensor Interface; voltage ranges from 1.65V 3.6V, 1.8V, 2.5V, 3.3V nominal. VDDBU pin: Powers Slow Clock oscillator part System Controller; voltage ranges from 1.65V 1.95V, 1.8V nominal. VDDPLL pin: Powers cells; voltage ranges from 1.65V 1.95V, 1.8V nominal. VDDANA pin: Powers Analog Digital Converter; voltage ranges from 3.0V 3.6V, 3.3V nominal. power supplies VDDIOM, VDDIOP0 VDDIOP1 identified pinout table multiplexing tables. These supplies enable user power device differently interfacing with memories interfacing with peripherals. Ground pins common VDDCORE, VDDIOM, VDDIOP0 VDDIOP1 pins power supplies. Separated ground pins provided VDDBU, VDDPLL VDDANA. These ground pins respectively GNDBU, GNDOSC, GNDPLL GNDANA.
Power Consumption
AT91SAM9260 consumes about static current VDDCORE 25°C. This static current rises temperature increases 85°C. VDDBU, current does exceed worst case conditions. dynamic power consumption, AT91SAM9260 consumes maximum VDDCORE maximum conditions (1.8V, 25°C, processor running full-performance algorithm high speed memories).
Programmable Lines Power Supplies
power supplies pins VDDIOM accept voltage ranges. This allows device reach maximum speed either 1.8V 3.3V external memories. target maximum speed SDCK (SDRAM Clock) loaded with power supply 1.8V power supply 3.3V. other signals (control, address data signals) exceed MHz. voltage ranges determined programming registers Chip Configuration registers located Matrix User Interface. reset, selected voltage defaults 3.3V nominal, power supply pins accept either 1.8V 3.3V. Obviously, device cannot reach maximum speed voltage sup-
AT91SAM9260 Preliminary
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AT91SAM9260 Preliminary
plied pins 1.8V only. user must program voltage range before getting device Slow Clock Mode.
Line Considerations
JTAG Port Pins
TMS, Schmitt trigger inputs have pull-up resistors. RTCK outputs, driven VDDIOP0, have pull-up resistors. JTAGSEL used select JTAG boundary scan when asserted high level (tied VDDBU). integrates permanent pull-down resistor about GNDBU, that left unconnected normal operations. NTRST signal described Section 6.3. JTAG signals supplied with VDDIOP0.
Test
used manufacturing test purposes when asserted high. integrates permanent pull-down resistor about GNDBU, that left unconnected normal operations. Driving this line high level leads unpredictable results. This supplied with VDDBU.
Reset Pins
NRST bidirectional with open-drain output integrating non-programmable pull-up resistor. driven with voltage VDDIOP0. NTRST input which allows reset JTAG Test Access port. action processor. product integrates power-on reset cells, which manages processor JTAG reset, NRST NTRST pins left unconnected. NRST NTRST pins both integrate permanent pull-up resistor VDDIOP0. value found table Characteristics" section "AT91SAM9260 Electrical Characteristics" product datasheet. NRST signal inserted Boundary Scan.
Controllers
lines managed Controllers integrate programmable pull-up resistor typical. Programming this pull-up resistor performed independently each line through Controllers. After reset, lines default inputs with pull-up resistors enabled, except those which multiplexed with External Interface signals that must enabled Peripheral reset. This explicitly indicated column "Reset State" Controller multiplexing tables.
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Line Drive Levels
lines high-drive current capable. Each these lines drive permanently.
Shutdown Logic Pins
SHDN output only, which driven Shutdown Controller. WKUP input-only. accept voltages only between VDDBU.
Slow Clock Selection
AT91SAM9260 slow clock generated either external 32,768 crystal on-chip oscillator. Table page defines states OSCSEL signal. Table 6-1.
OSCSEL
Slow Clock Selection
Slow Clock Internal External 32,768
Processor Architecture
ARM926EJ-S Processor
RISC Processor Based v5TEJ Architecture with Jazelle technology Java acceleration Instruction Sets High-performance 32-bit Instruction Thumb High Code Density 16-bit Instruction Instruction Extensions 5-Stage Pipeline Architecture: Instruction Fetch Instruction Decode Execute Data Memory Register Write 8-Kbyte Data Cache, 8-Kbyte Instruction Cache Virtually-addressed 4-way Associative Cache Eight words line Write-through Write-back Operation Pseudo-random Round-robin Replacement Write Buffer Main Write Buffer with 16-word Data Buffer 4-address Buffer DCache Write-back Buffer with 8-word Entries Single Address Entry Software Control Drain
AT91SAM9260 Preliminary
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AT91SAM9260 Preliminary
Standard Memory Management Unit (MMU) Access Permission Sections Access Permission large pages small pages specified separately each quarter page embedded domains Interface Unit (BIU) Arbitrates Schedules Requests Separate Masters both instruction data access providing complete Matrix system flexibility Separate Address Data Buses both 32-bit instruction interface 32-bit data interface Address Data Buses, data 8-bit (Bytes), 16-bit (Half-words) 32bit (Words)
Matrix
6-layer Matrix, handling requests from masters Programmable Arbitration strategy Fixed-priority Arbitration Round-Robin Arbitration, either with default master, last accessed default master fixed default master Burst Management Breaking with Slot Cycle Limit Support Undefined Burst Length Support Address Decoder provided Master Three different slaves assigned each decoded memory area: internal boot, external boot, after remap Boot Mode Select Non-volatile Boot Memory internal external Selection made sampled reset Remap Command Allows Remapping Internal SRAM Place Boot Non-Volatile Memory Allows Handling Dynamic Exception Vectors
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7.2.1
Matrix Masters Matrix AT91SAM9260 manages Masters, which means that each master perform access concurrently with others, according slave accesses available. Each Master decoder that defined specifically each master. order simplify addressing, masters have same decodings. Table 7-1.
Master Master Master Master Master Master
List Matrix Masters
ARM926Instruction ARM926 Data Controller Ethernet Host
7.2.2
Matrix Slaves Each Slave arbiter, thus allowing different arbitration Slave programmed. Table 7-2.
Slave Slave Slave Host User Interface Slave Slave External Interface Internal Peripherals
List Matrix Slaves
Internal SRAM0 4kBytes Internal SRAM1 4kBytes Internal
7.2.3
Master Slave Access Masters normally access Slaves. However, some paths make sense, such allowing access from Ethernet Internal Peripherals. Thus, these paths forbidden simply wired, shown following table. Table 7-3. AT91SAM9260 Masters Slaves Access
Master Slave Internal SRAM KBytes Internal SRAM KBytes Internal User Interface External Interface Internal Peripherals ARM926 Instruction Data Peripheral Controller Controller Ethernet Host Controller
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AT91SAM9260 Preliminary
Peripheral Controller
Acting Matrix Master Allows data transfers from/to peripheral to/from memory space without intervention processor. Next Pointer Support, forbids strong real-time constraints buffer management. Twenty-two channels each USART Debug Unit each Serial Synchronous Controller each Serial Peripheral Interface Multimedia Card Interface Analog-to-Digital Converter Peripheral Controller handles transfer requests from channel according following priorities (Low High priorities): DBGU Transmit Channel USART5 Transmit Channel USART4 Transmit Channel USART3 Transmit Channel USART2 Transmit Channel USART1 Transmit Channel USART0 Transmit Channel SPI1 Transmit Channel SPI0 Transmit Channel Transmit Channel DBGU Receive Channel USART5 Receive Channel USART4 Receive Channel USART3 Receive Channel USART2 Receive Channel USART1 Receive Channel USART0 Receive Channel Receive Channel SPI1 Receive Channel SPI0 Receive Channel Receive Channel Transmit/Receive Channel
Debug Test ARM926 Real-time In-circuit Emulator real-time Watchpoint Units Independent Registers: Debug Control Register Debug Status Register
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Test Access Port Accessible through JTAG Protocol Debug Communications Channel Debug Unit Two-pin UART Debug Communication Channel Interrupt Handling Chip Register IEEE1149.1 JTAG Boundary-scan Digital Pins
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AT91SAM9260 Preliminary
Memories
Figure 8-1. AT91SAM9260 Memory Mapping
Address Memory Space 0x0000 0000 Internal Memories
0x0FFF FFFF
Internal Memory Mapping
0x0000 0000 Boot Memory
Notes ROM, EBI_NCS0 SRAM depending REMAP
256M Bytes
0x10 0000 0x10 8000 Reserved Bytes
0x1000 0000 Chip Select
0x1FFF FFFF
256M Bytes
0x20 0000 SRAM0 0x20 1000 Reserved Bytes
0x2000 0000 Chip Select SDRAMC 256M Bytes
0x30 0000
SRAM1 0x30 1000 Reserved 0x50 0000
Bytes
0x2FFF FFFF
0x3000 0000 Chip Select
0x3FFF FFFF
256M Bytes
0x50 4000 Reserved
Bytes
0x4000 0000
Chip Select NANDFlash Chip Select Compact Flash Slot Chip Select Compact Flash Slot Chip Select
256M Bytes
0x0FFF FFFF
0x4FFF FFFF
0x5000 0000
256M Bytes
0x5FFF FFFF
0x6000 0000
Peripheral Mapping 256M Bytes
0xF000 0000
0x6FFF FFFF
0x7000 0000 256M Bytes
Reserved
0xFFFA 0000 TCO, TC1, 0xFFFA 4000 0xFFFA 8000 Bytes Bytes
System Controller Mapping
0xFFFF C000 Reserved 0xFFFF E800 Bytes
0x7FFF FFFF
0x8000 0000 Chip Select
0x8FFF FFFF
256M Bytes
0xFFFA C000
0xFFFB 0000 USART0 0xFFFB 4000 USART1 0xFFFB 8000 USART2 0xFFFB C000 0xFFFC 0000 0xFFFC 4000 EMAC 0xFFFC 8000
Bytes Bytes
0xFFFF EA00 SDRAMC 0xFFFF EC00 Bytes
0x9000 0000
Bytes 0xFFFF EE00 Bytes Bytes Bytes Bytes Bytes 0xFFFF F600 Bytes Bytes 0xFFFF F800
MATRIX 0xFFFF EF10 0xFFFF F000 CCFG 0xFFFF F200 DBGU 0xFFFF F400 PIOA
Bytes
Bytes
Bytes
Bytes
Bytes
Undefined (Abort)
1,518M Bytes
0xFFFC C000
SPI0
PIOB
bytes
SPI1 0xFFFD 0000 USART3 0xFFFD 4000 USART4 0xFFFD 8000 USART5 0xFFFD C000 TC3, TC4, 0xFFFE 0000 0xEFFF FFFF 0xFFFE 4000
PIOC Bytes Bytes Bytes 0xFFFF FA00 Reserved 0xFFFF FC00 0xFFFF FD00 RSTC 0xFFFF FD10 Bytes Bytes 0xFFFF FD20 0xFFFF FD30 0xFFFF FD40 WDTC SHDC RTTC PITC 0xFFFF FD50 0xFFFF FD60 Bytes 0xFFFF FFFF
bytes
Bytes Bytes Bytes Bytes Bytes Bytes Bytes
0xF000 0000 Internal Peripherals
0xFFFF FFFF
Reserved 256M Bytes
0xFFFF C000 SYSC 0xFFFF FFFF
GPBR Reserved
6221DS-ATARM-22-Sep-06
first level address decoding performed Matrix, i.e., implementation Advanced High Performance (AHB) Master Slave interfaces with additional features. Decoding breaks bytes address space into banks Mbytes. banks directed that associates these banks external chip selects EBI_NCS0 EBI_NCS7. Bank reserved addressing internal memories, second level decoding provides Mbyte internal memory area. Bank reserved peripherals provides access Advanced Peripheral (APB). Other areas unused performing access within them provides abort master requesting such access. Each Master decoder, thus allowing different memory mapping Master. However, order simplify mappings, masters have similar address decoding. Regarding Master Master (ARM926 Instruction Data), three different Slaves assigned memory space decoded address 0x0: internal boot, external boot, after remap. Refer Table 8-1, "Internal Memory Mapping," page details. complete memory presented Figure page
Embedded Memories
Single Cycle Access full matrix speed Fast SRAM Single Cycle Access full matrix speed
8.1.1
Boot Strategies Table summarizes Internal Memory Mapping each Master, depending Remap status state reset. Table 8-1. Internal Memory Mapping
REMAP Address 0x0000 0000 EBI_NCS0 SRAM0 REMAP
system always boots address 0x0. ensure maximum number possibilities boot, memory layout configured with parameters. REMAP allows user first internal SRAM bank ease development. This done software once system booted. When REMAP ignored. Refer Matrix Section more details. When REMAP allows user 0x0, convenience, external memory. This done hardware reset.
Note: Memory blocks affected these parameters always seen their specified base addresses. complete memory presented Figure page
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AT91SAM9260 Preliminary
AT91SAM9260 matrix manages boot memory that depends level reset. internal memory area mapped between address 0x000F FFFF reserved this purpose. detected boot memory embedded ROM. detected boot memory memory connected Chip Select External Interface. 8.1.1.1 Boot Embedded system boots using Boot Program. Boot slow clock (On-chip 32,768 Auto baudrate detection Downloads runs application from external storage media into internal SRAM Downloaded code size depends embedded SRAM size Automatic detection valid application Bootloader non-volatile memory DataFlash® connected NPCS0 NPCS1 SPI0 8-bit and/or 16-bit NANDFlash SAM-BABoot case valid program detected external NVM, supporting Serial communication DBGU Device Port 8.1.1.2 Boot External Memory Boot slow clock (On-chip 32,768 Boot with default configuration Static Memory Controller, byte select mode, 16bit data bus, Read/Write controlled Chip Select, allows boot 16-bit non-volatile memory. customer-programmed software must perform complete configuration. speed boot sequence when booting (BMS=0), user must take following steps: Program (main oscillator enable bypass mode). Program start PLL. Reprogram setup, cycle, hold, mode timings registers adapt them clock. Switch main clock value.
External Memories
external memories accessed through External Interface. Each Chip Select line 256-Mbyte memory area assigned. Refer memory Figure page
8.2.1
External Interface Integrates three External Memory Controllers Static Memory Controller
6221DS-ATARM-22-Sep-06
SDRAM Controller Controller Additional logic NANDFlash Full 32-bit External Data 26-bit Address 64MBytes linear) chip selects, Configurable Assignment: Static Memory Controller NCS0 SDRAM Controller Static Memory Controller NCS1 Static Memory Controller NCS2 Static Memory Controller NCS3, Optional NAND Flash support Static Memory Controller NCS4 NCS5, Optional CompactFlash support Static Memory Controller NCS6-NCS7 8.2.2 Static Memory Controller 32-bit Data Multiple Access Modes supported Byte Write Byte Select Lines Asynchronous read Page Mode supported 32-byte page size) Multiple device adaptability Compliant with Module Control signals programmable setup, pulse hold time each Memory Bank Multiple Wait State Management Programmable Wait State Generation External Wait Request Programmable Data Float Time Slow Clock mode supported 8.2.3 SDRAM Controller Supported devices Standard Low-power SDRAM (Mobile SDRAM) Numerous configurations supported Address Memory Parts SDRAM with four Internal Banks SDRAM with 32-bit Datapath Programming facilities Word, half-word, byte access Automatic page break when Memory Boundary been reached Multibank Ping-pong Access Timing parameters specified software Automatic refresh operation, refresh rate programmable Energy-saving capabilities
AT91SAM9260 Preliminary
6221DS-ATARM-22-Sep-06
AT91SAM9260 Preliminary
Self-refresh, power down deep power down modes supported Error detection Refresh Error Interrupt SDRAM Power-up Initialization software Latency supported Auto Precharge Command used 8.2.4 Error Corrected Code Controller Tracking accesses NAND Flash device trigging corresponding chip select Single error correction 2-bit Random detection Automatic Hamming Code Calculation while writing value available register Automatic Hamming Code Calculation while reading Error Report, including error flag, correctable error flag word address being detected erroneous Support 16-bit NAND Flash devices with 512-, 1024-, 2048- 4096-bytes pages
6221DS-ATARM-22-Sep-06
System Controller
System Controller peripherals that allows handling elements system, such power, resets, clocks, time, interrupts, watchdog, etc. System Controller User Interface also embeds registers that configure Matrix registers chip configuration. chip configuration registers configure chip select assignment voltage range external memories System Controller's peripherals mapped within highest Kbytes address space, between addresses 0xFFFF E800 0xFFFF FFFF. However, registers System Controller mapped address space. registers System Controller addressed from single pointer using standard instruction set, Load/Store instruction indexing mode Kbytes. Figure page shows System Controller block diagram. Figure page shows mapping User Interfaces System Controller peripherals.
AT91SAM9260 Preliminary
6221DS-ATARM-22-Sep-06
AT91SAM9260 Preliminary
Block Diagram
AT91SAM9260 System Controller Block Diagram
System Controller VDDCORE Powered irq0-irq2 periph_irq[2.24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd debug periph_nreset SLCK debug idle proc_nreset Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC NRST VDDCORE por_ntrst jtag_nreset rstc_irq Reset Controller periph_nreset proc_nreset backup_nreset VDDBU Powered SLCK rtt_irq rtt_alarm UDPCK periph_clk[10] SLOW CLOCK SLCK MAIN PLLA PLLB MAINCK Power Management Controller Shutdown Controller periph_nreset periph_irq[10] General-purpose Backup Registers Device Port UHPCK periph_clk[20] periph_nreset periph_irq[20] Host Port Debug Unit Advanced Interrupt Controller por_ntrst ntrst ARM926EJ-S nirq nfiq
Figure 9-1.
dbgu_irq dbgu_txd pit_irq
proc_nreset debug
jtag_nreset wdt_irq periph_nreset
Boundary Scan Controller
Matrix
VDDBU
VDDBU
SLCK backup_nreset SLCK SHDN WKUP backup_nreset rtt0_alarm OSC_SEL XIN32 XOUT32
Real-time Timer
periph_clk[2.27] pck[0-1] UDPCK UHPCK
XOUT PLLRCA
PLLACK PLLBCK
periph_nreset
pmc_irq idle
periph_clk[6.24] periph_nreset
periph_nreset periph_clk[2.4] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31
Controllers
periph_irq[2.4] irq0-irq2 dbgu_txd
Embedded Peripherals periph_irq[6.24] enable
6221DS-ATARM-22-Sep-06
Reset Controller
Based Power-on-reset cells VDDBU VDDCORE Status last reset Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset watchdog reset Controls internal resets NRST output Allows shaping reset signal external devices
Shutdown Controller
Shutdown Wake-up logic Software programmable assertion SHDWN Deassertion Programmable WKUP level change alarm
Clock Generator
Embeds Low-power 32,768 Slow Clock Oscillator Low-power oscillator selectable with OSCSEL signal Provides permanent Slow Clock SLCK system Embeds Main Oscillator Oscillator bypass feature Supports crystals Embeds PLLs PLLA outputs clock PLLB outputs clock Both integrate input divider increase output accuracy PLLB embeds filter
AT91SAM9260 Preliminary
6221DS-ATARM-22-Sep-06
AT91SAM9260 Preliminary
Figure 9-2. Clock Generator Block Diagram
Clock Generator OSC_SEL Chip XIN32 XOUT32 XOUT Main Oscillator Main Clock MAINCK Slow Clock Oscillator
Slow Clock SLCK
PLLRCA
Divider Divider
PLLA Clock PLLACK PLLB Clock PLLBCK
Status
Control
Power Management Controller
Power Management Controller
Provides: Processor Clock Master Clock MCK, particular Matrix memory interfaces Device Clock UDPCK independent peripheral clocks, typically frequency programmable clock outputs: PCK0, PCK1 Five flexible operating modes: Normal Mode, processor peripherals running programmable frequency Idle Mode, processor stopped waiting interrupt Slow Clock Mode, processor peripherals running frequency Standby Mode, Idle Backup Mode, peripheral running frequency, processor stopped waiting interrupt Backup Mode, Main Power Supplies off, VDDBU powered battery
6221DS-ATARM-22-Sep-06
Figure 9-3.
AT91SAM9260 Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,.,/64 Divider /1,/2,/3,/4 Peripherals Clock Controller ON/OFF Idle Mode periph_clk[.]
Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,.,/64 pck[.]
Clock Controller ON/OFF PLLBCK Divider /1,/2,/4 UDPCK UHPCK
Periodic Interval Timer
Includes 20-bit Periodic Counter, with less than accuracy Includes 12-bit Interval Overlay Counter Real Time Linux®/Windows compliant tick generator
Watchdog Timer
16-bit key-protected only-once-Programmable Counter Windowed, prevents processor being dead-lock watchdog access
Real-time Timer
Real-time Timer 32-bit free-running back-up Counter Integrates 16-bit programmable prescaler running slow clock Alarm Register capable generating wake-up system through Shutdown Controller
General-purpose Back-up Registers
Four 32-bit backup general-purpose registers
9.10
Advanced Interrupt Controller
Controls interrupt lines (nIRQ nFIQ) Processor Thirty-two individually maskable vectored interrupt sources Source reserved Fast Interrupt Input (FIQ) Source reserved system peripherals (PIT, RTT, PMC, DBGU, etc.)
AT91SAM9260 Preliminary
6221DS-ATARM-22-Sep-06
AT91SAM9260 Preliminary
Programmable Edge-triggered Level-sensitive Internal Sources Programmable Positive/Negative Edge-triggered High/Low Level-sensitive Three External Sources plus Fast Interrupt signal 8-level Priority Controller Drives Normal Interrupt processor Handles priority interrupt sources Higher priority interrupts served during service lower priority interrupt Vectoring Optimizes Interrupt Service Routine Branch Execution 32-bit Vector Register interrupt source Interrupt Vector Register reads corresponding current Interrupt Vector Protect Mode Easy debugging preventing automatic operations when protect models enabled Fast Forcing Permits redirecting normal interrupt source Fast Interrupt processor
9.11
Debug Unit
Composed functions: Two-pin UART Debug Communication Channel (DCC) support Two-pin UART Implemented features 100% compatible with standard Atmel USART Independent receiver transmitter with common programmable Baud Rate Generator Even, Odd, Mark Space Parity Generation Parity, Framing Overrun Error Detection Automatic Echo, Local Loopback Remote Loopback Channel Modes Support channels with connection receiver transmitter Debug Communication Channel Support Offers visibility interrupt trigger from COMMRX COMMTX signals from Processor's Interface
9.12
Chip Identification
Chip 0x019803A0 JTAG 0x05B1303F ARM926 0x0792603F
6221DS-ATARM-22-Sep-06
Peripherals
10.1 User Interface
peripherals mapped upper Mbytes address space between addresses 0xFFFA 0000 0xFFFC FFFF. Each User Peripheral allocated Kbytes address space. complete memory presented Figure page
10.2
Identifiers
Table 10-1 defines Peripheral Identifiers AT91SAM9260. peripheral identifier required control peripheral interrupt with Advanced Interrupt Controller control peripheral clock with Power Management Controller. Table 10-1.
Peripheral
AT91SAM9260 Peripheral Identifiers
Peripheral Mnemonic SYSC PIOA PIOB PIOC SPIO SPI1 EMAC Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel Controller Parallel Controller Parallel Controller Analog Digital Converter USART USART USART Multimedia Card Interface Device Port Two-wire Interface Serial Peripheral Serial Peripheral Serial Peripheral Interface Reserved Reserved Timer/Counter Timer/Counter Timer/Counter Host Port Ethernet Image Sensor Interface USART USART USART Timer/Counter Timer/Counter Timer/Counter Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 IRQ2 External Interrupt
AT91SAM9260 Preliminary
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AT91SAM9260 Preliminary
10.2.1 10.2.1.1 Peripheral Interrupts Clock Control System Interrupt System Interrupt Source wired-OR interrupt signals coming from: SDRAM Controller Debug Unit Periodic Interval Timer Real-time Timer Watchdog Timer Reset Controller Power Management Controller clock these peripherals cannot deactivated Peripheral only used within Advanced Interrupt Controller. 10.2.1.2 External Interrupts external interrupt signals, i.e., Fast Interrupt signal Interrupt signals IRQ0 IRQ2, dedicated Peripheral However, there clock control associated with these peripheral IDs.
10.3
Peripheral Signal Multiplexing Lines
AT91SAM9260 features controllers (PIOA, PIOB, PIOC) that multiplex lines peripheral set. Each Controller controls lines. Each line assigned peripheral functions, Table 10-2 page Table 10-3 page Table 10-4 page define lines peripherals multiplexed Controllers. columns "Function" "Comments" have been inserted this table user's comments; they used track pins defined application. Note that some peripheral functions which output only might duplicated within both tables. column "Reset State" indicates whether Line resets mode peripheral mode. appears, Line resets input with pull-up enabled, that device maintained static state soon reset released. result, corresponding Line register PIO_PSR (Peripheral Status Register) resets low. signal name appears "Reset State" column, Line assigned this function corresponding PIO_PSR resets high. This case pins controlling memories, particular address lines, which require driven soon reset released. Note that pull-up resistor also enabled this case.
6221DS-ATARM-22-Sep-06
10.3.1
Controller Multiplexing Multiplexing Controller
Controller Application Usage Comments Reset State MCDB3 MCDB2 MCDB1 ETX2 ETX3 ETXER ETX2 ETX3 ERX2 ERX3 ERXCK ECRS ECOL RXD4 Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Function Comments
Table 10-2.
Line PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Note:
Peripheral SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 RTS2 CTS2 MCDA0 MCCDA MCCK MCDA1 MCDA2 MCDA3 ETX0 ETX1 ERX0 ERX1 ETXEN ERXDV ERXER ETXCK EMDC EMDIO ADTRG TWCK TCLK0 TIOA0 TIOA1 TIOA2 SCK1 SCK2
Peripheral MCDB0 MCCDB
SCK0 TXD4 available 208-lead PQFP package.
AT91SAM9260 Preliminary
6221DS-ATARM-22-Sep-06
AT91SAM9260 Preliminary
10.3.2 Controller Multiplexing Multiplexing Controller
Controller Line PB10 PB11 PB12(1) PB13(1) PB14 PB15 Peripheral SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 TXD3 RXD3 TXD5 RXD5 DRXD DTXD ISI_D8 ISI_D9 ISI_D10 ISI_D11 TCLK1 TCLK2 Peripheral TIOA3 TIOB3 TIOA4 TIOA5 Comments Reset State Application Usage Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP0 VDDIOP0
RDY/BUSY signal NANDFlash boot
Table 10-3.
Function
Comments
PB16
TCLK3
VDDIOP0
PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30
DSR0 DCD0 DTR0 RTS0 CTS0 RTS1 CTS1 PCK0
TCLK4 TIOB4 TIOB5 ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_VSYNC ISI_HSYNC
VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1
PB31 PCK1 ISI_MCK Note: available 208-lead PQFP package.
6221DS-ATARM-22-Sep-06
10.3.3
Controller Multiplexing Multiplexing Controller
Controller Application Usage Comments Reset State Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Function Comments
Table 10-4.
Line
Peripheral
Peripheral SCK3 PCK0 PCK1 SPI1_NPCS3
TIOB2 TIOB1 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW NCS2 IRQ0 NCS3/NANDCS NWAIT
SPI1_NPCS2 SPI1_NPCS1 CFCE1 CFCE2 RTS3 TIOB0 CTS3 SPI0_NPCS1 NCS7 NCS6 IRQ2 IRQ1 SPI0_NPCS2 SPI0_NPCS3 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 EF100 TCLK5
PC10 PC11 PC12(1) PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30
PC31 Note: available 208-lead PQFP package.
AT91SAM9260 Preliminary
6221DS-ATARM-22-Sep-06
AT91SAM9260 Preliminary
10.4
10.4.1
Embedded Peripherals
Serial Peripheral Interface Supports communication with serial external devices Four chip selects with external decoder support allow communication with peripherals Serial memories, such DataFlash 3-wire EEPROMs Serial peripherals, such ADCs, DACs, Controllers, Controllers Sensors External co-processors Master slave serial peripheral interface 16-bit programmable data length chip select Programmable phase polarity chip select Programmable transfer delays between consecutive transfers between clock data chip select Programmable delay between consecutive transfers Selectable mode fault detection Very fast transfers supported Transfers with baud rates chip select line left active speed transfers same device
10.4.2
Two-wire Interface Master, MultiMaster Slave modes supported General Call supported Slave mode
10.4.3
USART Programmable Baud Rate Generator 9-bit full-duplex synchronous asynchronous serial communications stop bits Asynchronous Mode stop bits Synchronous Mode Parity generation error detection Framing error detection, overrun error detection MSB- LSB-first Optional break generation detection by-16 over-sampling receiver frequency Hardware handshaking RTS-CTS Optional modem signal management DTR-DSR-DCD-RI Receiver time-out transmitter timeguard Optional Multi-drop Mode with address generation detection Optional Manchester Encoding RS485 with driver control signal ISO7816, Protocols interfacing with smart cards NACK handling, error counter with repetition iteration limit
6221DS-ATARM-22-Sep-06
IrDA modulation demodulation Communication 115.2 Kbps Test Modes Remote Loopback, Local Loopback, Automatic Echo USART contains features allowing management Modem Signals DTR, DSR, AT91SAM9260, only USART0 implements these signals, named DTR0, DSR0, DCD0 RI0. USART1 USART2 implement modem signals. Only (RTS1 CTS1, RTS2 CTS2, respectively) implemented these USARTs other features. Thus, programming USART1, USART2 USART3 Modem Mode lead unpredictable results. these USARTs, commands relating Modem Mode have effect status bits relating status modem signals never activated. 10.4.4 Serial Synchronous Controller Provides serial synchronous communication links used audio telecom applications (with CODECs Master Slave Modes, I2S, Buses, Magnetic Card Reader, etc.) Contains independent receiver transmitter common clock divider Offers configurable frame sync data length Receiver transmitter programmed start automatically detection different event frame sync signal Receiver transmitter include data signal, clock signal frame synchronization signal 10.4.5 Timer Counter 16-bit Timer Counter Channels Wide range functions including Frequency Measurement Event Counting Interval Measurement Pulse Generation Delay Timing Pulse Width Modulation Up/down Capabilities Each channel user-configurable contains Three external clock inputs Five internal clock inputs multi-purpose input/output signals global registers that three Channels 10.4.6 Multimedia Card Interface double-channel MultiMedia Card Interface Compatibility with MultiMedia Card Specification Version
AT91SAM9260 Preliminary
6221DS-ATARM-22-Sep-06
AT91SAM9260 Preliminary
Compatibility with Memory Card Specification Version Compatibility with SDIO Specification Version V1.0. Card clock rate Master Clock divided Embedded power management slow down clock rate when used slots, each supporting slot MultiMediaCard cards) Memory Card Support stream, block multi-block data read write 10.4.7 Host Port Compliance with Open Specification Compliance with V2.0 Full-speed Low-speed Specification Supports both Low-Speed Mbps Full-speed Mbps devices Root integrated with downstream ports 217-LFBGA package embedded transceivers Supports power management Operates master Matrix 10.4.8 Device Port V2.0 full-speed compliant, MBits second Embedded V2.0 full-speed transceiver Embedded 2,432-byte dual-port endpoints Suspend/Resume logic Ping-pong mode (two memory banks) isochronous bulk endpoints general-purpose endpoints Endpoint bytes, ping-pong mode Endpoint bytes, ping-pong mode Endpoint bytes, ping-pong mode Embedded pull-up 10.4.9 Ethernet 10/100 Compatibility with IEEE Standard 802.3 MBits second data throughput capability Full- half-duplex operations RMII interface physical layer Register Interface address, data, status control registers Interface, operating master Memory Controller Interrupt generation signal receive transmit completion 28-byte transmit 28-byte receive FIFOs Automatic generation transmitted frames Address checking logic recognize four 48-bit addresses Support promiscuous mode where valid frames copied memory
6221DS-ATARM-22-Sep-06
Support physical layer management through MDIO interface 10.4.10 Image Sensor Interface ITU-R 601/656 8-bit mode external interface support Support ITU-R BT.656-4 synchronization Vertical horizontal resolutions 2048 2048 Preview Path 640*480 Support packed data formatting YCbCr 4:2:2 formats Preview scaler generate smaller size image Programmable frame capture rate 10.4.11 Analog-to-Digital Converter 4-channel 10-bit 312K samples/sec. Successive Approximation Register -2/+2 Integral Linearity, -1/+1 Differential Linearity Individual enable disable each channel External voltage reference better accuracy voltage inputs Multiple trigger source Hardware software trigger External trigger Timer Counter outputs TIOA0 TIOA2 trigger Sleep Mode conversion sequencer Automatic wakeup trigger back sleep mode after conversions enabled channels Four analog inputs shared with digital signals
AT91SAM9260 Preliminary
6221DS-ATARM-22-Sep-06
AT91SAM9260 Preliminary
Package Drawings
Figure 11-1. 208-lead TQFP Package Drawing
6221DS-ATARM-22-Sep-06
Figure 11-2. 217-ball LFBGA Package Drawing
AT91SAM9260 Preliminary
6221DS-ATARM-22-Sep-06
AT91SAM9260 Preliminary
AT91SAM9260 Ordering Information
Table 12-1. AT91SAM9260 Ordering Information
Package PQFP208 BGA217 Package Type Green RoHS-compliant Temperature Operating Range Industrial -40°C 85°C
Ordering Code AT91SAM9260-QU AT91SAM9260-CJ
6221DS-ATARM-22-Sep-06
Revision History
Table 13-1.
Revision 6221AS
Revision History
Comments First issue. Power consumption figures updated with current values Section "Power Consumption" page Change signal name Section "Pinout 208-pin PQFP Package" page VDDIOP1, added supported voltage levels Table 3-1, "Signal Description List," page corrected supported voltage levels Section "Power Consumption" page Removed package marking updated package outline information Section "Package Pinout" page Change signal name Section "Pinout 208-pin PQFP Package" page Inserted voltage information JTAGSEL signal Table 3-1, "Signal Description List" Section "JTAG Port Pins" page Table 3-1, "Signal Description List," page added voltage information OSCSEL pins. Section "Reset Pins" page information NRST NRTST pins. Corrected features Section 10.4.11 "Analog-to-Digital Converter" page Removed references VDDOSC "Features", Table 3-1, "Signal Description List", Section "Power Supplies" page Corrected VDDPLLA VDDPLLB with VDDPLL GNDPLLA GNDPLLB with GNDPLL Table 4-1, "Pinout 208-pin PQFP Package," page Table 4-2, "Pinout 217-ball LFBGA Package," page Figure page corrected range SCKx pins; label change matrix block. Change Request Ref.
6221BS
2843
2874
2922 2907 2947 2979 3003 2923
6221CS
3183
3235, 3071 3066 3236 3237 3245
6221DS
Figure page Section "Peripheral Controller" page removed channels. Section "Reset Pins" page added NRST bidirectional. Figure page added UHPCK Clock Controller output. Section 10.4.3 "USART" page added information modem signals.
AT91SAM9260 Preliminary
6221DS-ATARM-22-Sep-06
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6221DS-ATARM-22-Sep-06

AT91 Thumb Microcontrollers AT91SAM9260 Summary Preliminary NOTE:

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