AT91 Thumb-based Microcontrollers AT91SAM7SE512 AT91SAM7SE256 AT91SAM7

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AT91 Thumb-based Microcontrollers AT91SAM7SE512 AT91SAM7SE256 AT91SAM7

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High-performance 32-bit RISC Architecture High-density 16-bit Instruction Leader MIPS/Watt EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash Kbytes, Organized Contiguous Banks 1024 Pages Bytes Dual Plane (AT91SAM7SE512) Kbytes (AT91SAM7SE256) Organized Bank 1024 Pages Bytes Single Plane (AT91SAM7SE256) Kbytes (AT91SAM7SE32) Organized Bank Pages Bytes Single Plane (AT91SAM7SE32) Single Cycle Access Worst Case Conditions Prefetch Buffer Optimizing Thumb Instruction Execution Maximum Speed Page Programming Time: Including Page Auto-erase, Full Erase Time: 10,000 Erase Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Fast Flash Programming Interface High Volume Production Kbytes (AT91SAM7SE512/256) Kbytes (AT91SAM7SE32) Internal High-speed SRAM, Single-cycle Access Maximum Speed External Interface (EBI) Supports SDRAM, Static Memory, Glueless Connection CompactFlash® ECC-enabled NAND Flash Memory Controller (MC) Embedded Flash Controller Memory Protection Unit Abort Status Misalignment Detection Reset Controller (RSTC) Based Power-on Reset Cells Low-power Factory-calibrated Brownout Detector Provides External Reset Signal Shaping Reset Source Status Clock Generator (CKGR) Low-power Oscillator, On-chip Oscillator Power Management Controller (PMC) Power Optimization Capabilities, Including Slow Clock Mode (Down Idle Mode Three Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources External Interrupt Sources Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) Two-wire UART Support Debug Communication Channel interrupt, Programmable Access Prevention Periodic Interval Timer (PIT) 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) 12-bit key-protected Programmable Counter Provides Reset Interrupt Signals System Counter Stopped While Processor Debug State Idle Mode
AT91 Thumb-based Microcontrollers AT91SAM7SE512 AT91SAM7SE256 AT91SAM7SE32 Advance Information Summary
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Real-time Timer (RTT)
32-bit Free-running Counter with Alarm Runs Internal Oscillator Three Parallel Input/Output Controllers (PIO) Eighty-eight Programmable Lines Multiplexed with Peripheral I/Os Input Change Interrupt Capability Each Line Individually Programmable Open-drain, Pull-up Resistor Synchronous Output Schmitt Trigger inputs Eleven Peripheral Controller (PDC) Channels Full Speed Mbits second) Device Port On-chip Transceiver, Eight Endpoints, 2688-byte Configurable Integrated FIFOs Synchronous Serial Controller (SSC) Independent Clock Frame Sync Signals Each Receiver Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Universal Synchronous/Asynchronous Receiver Transmitters (USART) Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation Support ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Full Modem Line Support USART1 Master/Slave Serial Peripheral Interfaces (SPI) 16-bit Programmable Data Length, Four External Peripheral Chip Selects Three-channel 16-bit Timer/Counter (TC) Three External Clock Inputs, Multi-purpose Pins Channel Double Generation, Capture/Waveform Mode, Up/Down Capability Four-channel 16-bit Controller (PWMC) Two-wire Interface (TWI) Master, Multi-Master Slave Mode Support, Two-wire Atmel EEPROMs Supported General Call Supported Slave Mode 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os SAM-BA- Default Boot program Interface with SAM-BA Graphic User Interface IEEE® 1149.1 JTAG Boundary Scan Digital Pins Four High-current Drive lines, Each Power Supplies Embedded 1.8V Regulator, Drawing Core External Components 1.8V 3,3V VDDIO Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply 1.8V VDDCORE Core Power Supply with Brownout Detector Fully Static Operation: 1.65V Worst Case Conditions Available 128-lead LQFP Green Package, 144-ball LFBGA RoHS-compliant Package
AT91SAM7SE512/256/32 [Advance Information Summary]
6222AS-ATARM-21-Aug-06
AT91SAM7SE512/256/32 [Advance Information Summary]
Description
Atmel's AT91SAM7SE Series member Smart Microcontroller family based 32-bit ARM7RISC processor high-speed Flash memory. AT91SAM7SE512 features Kbyte high-speed Flash Kbyte SRAM. AT91SAM7SE256 features Kbyte high-speed Flash Kbyte SRAM. AT91SAM7SE32 features Kbyte high-speed Flash Kbyte SRAM. also embeds large peripherals, including device, External Interface (EBI), complete system functions minimizing number external components. incorporates controllers synchronous DRAM (SDRAM) Static memories features specific circuitry facilitating interface NAND Flash, SmartMedia CompactFlash. device ideal migration path 8/16-bit microcontroller users looking additional performance, extended memory higher levels system integration. embedded Flash memory programmed in-system JTAG-ICE interface parallel interface production programmer prior mounting. Built-in lock bits security protect firmware from accidental overwrite preserve confidentiality. AT91SAM7SE Series system controller includes reset controller capable managing power-on sequence microcontroller complete system. Correct device operation monitored built-in brownout detector watchdog running integrated oscillator. combining ARM7TDMI processor with on-chip Flash SRAM, wide range peripheral functions, including USART, SPI, External Interface, Timer Counter, Analog-to-Digital Converters monolithic chip, AT91SAM7SE512/256/32 powerful device that provides flexible, cost-effective solution many embedded control applications.
Configuration Summary AT91SAM7SE512, AT91SAM7SE256 AT91SAM7SE32
AT91SAM7SE512, AT91SAM7SE256 AT91SAM7SE32 differ memory sizes organization. Table below summarizes configurations three devices.
Table 1-1.
Device
Configuration Summary
Flash Size 512K bytes 256K bytes bytes Flash Organization dual plane single plane single plane Size bytes bytes bytes
AT91SAM7SE512 AT91SAM7SE256 AT91SAM7SE32
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Block Diagram
Figure 2-1. AT91SAM7SE512/256/32 Block Diagram Signal Description
JTAGSEL
JTAG SCAN
ARM7TDMI Processor 1.8V Voltage Regulator Memory Controller Embedded Address Flash Decoder Controller Abort Status Misalignment Detection Flash
Kbytes (SE512) Kbytes (SE256) Kbytes (SE32) VDDFLASH ERASE VDDIN VDDOUT VDDCORE
System Controller
IRQ0-IRQ1
SRAM
Kbytes (SE512/256) Kbytes (SE32)
VDDIO
DRXD DTXD
DBGU
PCK0-PCK2 PLLRC XOUT
RCOSC
Memory Protection Unit
Peripheral Bridge
VDDFLASH VDDCORE VDDCORE NRST
Reset Controller
Peripheral Controller Channels
PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3 PGMD0-PGMD15 PGMNCMD PGMEN0-PGMEN1
Fast Flash Programming Interface
SAM-BA
PIOA PIOB PIOC
RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DSR1 DTR1 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 ADTRG ADVREF
USART0 USART1 CompactFlash NAND Flash
SDRAM Controller
Timer Counter
Static Memory Controller
Controller
Transciever
D[31:0] A0/NBS0 A1/NBS2 A[15:2], A[20:18] A21/NANDALE A22/REG/NANDCLE A16/BA0 A17/BA1 NCS0 NCS1/SDCS NCS2/CFCS1 NCS3/NANDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NBS3/CFIOW SDCKE SDWE SDA10 CFRNW NCS4/CFCS0 NCS5/CFCE1 NCS6/CFCE2 NCS7 NANDOE NANDWE NWAIT SDCK
FIFO Device
PWMC
PWM0 PWM1 PWM2 PWM3 TWCK
AT91SAM7SE512/256/32 [Advance Information Summary]
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AT91SAM7SE512/256/32 [Advance Information Summary]
Signal Description
Table 3-1.
Signal Name
Signal Description List
Function Power Type Active Level Comments
VDDIN VDDOUT VDDFLASH VDDIO VDDCORE VDDPLL
Voltage Regulator Power Supply Input Voltage Regulator Output Flash Power Supply Lines Power Supply Core Power Supply Ground
Power Power Power Power Power Power Ground
3.6V 1.85V 3.6V 3.6V 1.65V 1.95V 1.65V 1.95V 1.65V 1.95V
Clocks, Oscillators PLLs XOUT PLLRC PCK0 PCK2 Main Oscillator Input Main Oscillator Output Filter Programmable Clock Output Input Output Input Output JTAG JTAGSEL Test Clock Test Data Test Data Test Mode Select JTAG Selection Input Input Output Input Input Flash Memory ERASE Flash Configuration Bits Erase Command Reset/Test NRST Microcontroller Reset Test Mode Select Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data IRQ0 IRQ1 External Interrupt Inputs Fast Interrupt Input Input Input Input Output Input High Pull-Up resistor Pull-down resistor Input High Pull-down resistor pull-up resistor. Pull-down resistor. pull-up resistor pull-up resistor.
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Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Active Level Comments
PA31 PB31 PC23
Parallel Controller Parallel Controller Parallel Controller
Device Port
Pulled-up input reset Pulled-up input reset Pulled-up input reset
Device Port Data Device Port Data USART
Analog Analog
SCK0 SCK1 TXD0 TXD1 RXD0 RXD1 RTS0 RTS1 CTS0 CTS1 DCD1 DTR1 DSR1
Serial Clock Transmit Data Receive Data Request Send Clear Send Data Carrier Detect Data Terminal Ready Data Ready Ring Indicator
Input Output Input Input Output Input Input Synchronous Serial Controller
Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync
Output Input Timer/Counter
TCLK0 TCLK2 TIOA0 TIOA2 TIOB0 TIOB2
External Clock Inputs Timer Counter Line Timer Counter Line
Input Controller
PWM0 PWM3
Channels
Output Serial Peripheral Interface
MISO MOSI SPCK NPCS0 NPCS1-NPCS3
Master Slave Master Slave Serial Clock Peripheral Chip Select Peripheral Chip Select
Output
AT91SAM7SE512/256/32 [Advance Information Summary]
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AT91SAM7SE512/256/32 [Advance Information Summary]
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Two-Wire Interface Active Level Comments
TWCK
Two-wire Serial Data Two-wire Serial Clock
Analog-to-Digital Converter
AD0-AD3 AD4-AD7 ADTRG ADVREF
Analog Inputs Analog Inputs Trigger Reference
Analog Analog Input Analog Fast Flash Programming Interface
Analog Inputs Digital pulled-up inputs reset
PGMEN0-PGMEN2 PGMM0-PGMM3 PGMD0-PGMD15 PGMRDY PGMNVALID PGMNOE PGMCK PGMNCMD
Programming Enabling Programming Mode Programming Data Programming Ready Data Direction Programming Read Programming Clock Programming Command
Input Input Output Output Input Input Input External Interface High
D[31:0] A[22:0] NWAIT
Data Address External Wait Signal
Output Input Static Memory Controller
NCS[7:0] NWR[1:0]
Chip Select Lines Write Signals Read Signal Write Enable NUB: Upper Byte Select NLB: Lower Byte Select
Output Output Output Output Output Output CompactFlash Support
CFCE[2:1] CFOE CFWE CFIOR CFIOW CFRNW CFCS[1:0]
CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash Read Signal CompactFlash Write Signal CompactFlash Read Write Signal CompactFlash Chip Select Lines
Output Output Output Output Output Output Output
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Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type NAND Flash Support Active Level Comments
NANDCS NANDOE NANDWE NANDCLE NANDALE
NAND Flash Chip Select Line NAND Flash Output Enable NAND Flash Write Enable NAND Flash Command Line Enable NAND Flash Address Line Enable
Output Output Output Output Output
SDRAM Controller SDCK SDCKE SDCS BA[1:0] SDWE NBS[3:0] SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Line Bank Select SDRAM Write Enable Column Signal Byte Mask Signals SDRAM Address Line Output Output Output Output Output Output Output Output High Tied after reset
AT91SAM7SE512/256/32 [Advance Information Summary]
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AT91SAM7SE512/256/32 [Advance Information Summary]
Package
AT91SAM7SE512/256/32 available 128-lead LQFP package with lead pitch. 144-ball LFBGA package with lead pitch
128-lead LQFP Package Outline
Figure shows orientation 128-lead LQFP package detailed mechanical description given Mechanical Characteristics section full datasheet.
Figure 4-1.
128-lead LQFP Package Outline (Top View)
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128-lead LQFP Pinout
Pinout 128-lead LQFP Package
ADVREF VDDOUT VDDIN PA20/PGMD8/AD3 PA19/PGMD7/AD2 PA18/PGMD6/AD1 PA17/PGMD5/AD0 PA16/PGMD4 PA15/PGMD3 PA14/PGMD2 PA13/PGMD1 PA12/PGMD0 PA11/PGMM3 PA10/PGMM2 PA9/PGMM1 VDDIO VDDCORE PA8/PGMM0 PA7/PGMNVALID PA6/PGMNOE PA5/PGMRDY PA4/PGMNCMD PA2/PGMEN2 PA1/PGMEN1 PA0/PGMEN0 PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 VDDIO VDDCORE PB19 PB18 PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10 VDDIO VDDCORE NRST ERASE JTAGSEL PC23 PC22 PC21 PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12 PC11 PC10 VDDIO VDDCORE SDCK PA31 PA30 PA29 PA28 PA27/PGMD15 PA26/PGMD14 PA25/PGMD13 PA24/PGMD12 PA23/PGMD11 PA22/PGMD10 PA21/PGMD9 VDDCORE VDDIO VDDFLASH XIN/PGMCK XOUT PLLRC VDDPLL
Table 4-1.
AT91SAM7SE512/256/32 [Advance Information Summary]
6222AS-ATARM-21-Aug-06
AT91SAM7SE512/256/32 [Advance Information Summary]
144-ball LFBGA Package Outline
Figure shows orientation 144-ball LFBGA package detailed mechanical description given Mechanical Characteristics section. Figure 4-2. 144-ball LFBGA Package Outline (Top View)
Ball
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144-ball LFBGA Pinout
Table 4-2.
PB12 PB13 PB16 PB22 PB23 PB25 PB29 PB30 PB31 PB10 PB14 PB18 PB20 PB24 PB28
SAM7SE512/256/32 Pinout 144-ball LFBGA Package
Signal Name VDDCORE VDDCORE PB17 PB26 PA14/PGMD2 PA12/PGMD0 PA11/PGMM3 PA8/PGMM0 PA7/PGMNVALID PC22 PC23 NRST ERASE TEST VDDCORE VDDCORE PA9/PGMM1 PA10/PGMM2 PA13/PGMD1 PC21 PC20 PC19 JTAGSEL VDDIO PA15/PGMD3 PA16/PGMD4 Signal Name PC18 PC16 PC17 VDDIO VDDIN VDDOUT PC15 PC14 PC13 VDDCORE VDDCORE PA19/PGMD7/AD2 PA20/PGMD8/AD3 VDDIO PC12 PC10 PA30 PA28 PA23/PGMD11 PA22/PGMD10 VDDCORE VDDCORE VDDCORE VDDIO Signal Name PC11 PA27/PGMD15 PA26/PGMD14 VDDCORE VDDFLASH VDDIO VDDIO PA18/PGMD6/AD1 SDCK PA29 PA24/PGMD12 PA21/PGMD9 ADVREF VDDFLASH VDDFLASH PA17/PGMD5/AD0 PA31 PA25/PGMD13 XIN/PGMCK XOUT PLLRC VDDPLL
Signal Name
PA4/PGMNCMD PA0/PGMEN0 PA1/PGMEN1 PB11 PB15 PB19 PB21 PB27 PA6/PGMNOE PA5/PGMRDY PA2/PGMEN2
AT91SAM7SE512/256/32 [Advance Information Summary]
6222AS-ATARM-21-Aug-06
AT91SAM7SE512/256/32 [Advance Information Summary]
Power Considerations
Power Supplies
AT91SAM7SE512/256/32 types power supply pins integrates voltage regulator, allowing device supplied with only voltage. power supply types are: VDDIN pin. powers voltage regulator ADC; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDOUT pin. output 1.8V voltage regulator. VDDIO pin. powers lines; voltage ranges supported: from 3.0V 3.6V, 3.3V nominal from 1.65V 1.95V, 1.8V nominal. VDDFLASH pin. powers transceivers part Flash. required Flash operate correctly; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDCORE pins. They power logic device; voltage ranges from 1.65V 1.95V, 1.8V typical. connected VDDOUT with decoupling capacitor. VDDCORE required device, including embedded Flash, operate correctly. VDDPLL pin. powers oscillator PLL. connected directly VDDOUT pin. order decrease current consumption, voltage regulator used, VDDIN, ADVREF, AD4, AD5, should connected GND. this case VDDOUT should left unconnected. separate ground pins provided different power supplies. Only pins provided should connected shortly possible system ground plane.
Power Consumption
AT91SAM7SE512/256/32 static current less than VDDCORE 25°C, including oscillator, voltage regulator power-on reset when brownout detector deactivated. Activating brownout detector adds static current. dynamic power consumption VDDCORE less than full speed when running Flash. Under same conditions, power consumption VDDFLASH does exceed
Voltage Regulator
AT91SAM7SE512/256/32 embeds voltage regulator that managed System Controller. Normal Mode, voltage regulator consumes less than static current draws output current. voltage regulator also Low-power Mode. this mode, consumes less than static current draws output current. Adequate output supply decoupling mandatory VDDOUT reduce ripple avoid oscillations. best achieve this capacitors parallel:
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external capacitor should connected between VDDOUT close chip possible. external capacitor should connected between VDDOUT GND. Adequate input supply decoupling mandatory VDDIN order improve startup stability reduce source voltage drop. input decoupling capacitor should placed close chip. example, capacitors used parallel: X7R.
Typical Powering Schematics
AT91SAM7SE512/256/32 supports 3.3V single supply mode. internal regulator input connected 3.3V source output feeds VDDCORE VDDPLL. Figure shows power schematics used bus-powered systems. Figure 5-1. 3.3V System Single Power Supply Schematic
VDDFLASH Power Source ranges from 4.5V (USB)
VDDIO DC/DC Converter VDDIN 3.3V VDDOUT Voltage Regulator
VDDCORE
VDDPLL
AT91SAM7SE512/256/32 [Advance Information Summary]
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AT91SAM7SE512/256/32 [Advance Information Summary]
Lines Considerations
JTAG Port Pins
TMS, schmitt trigger inputs 5V-tolerant. TMS, integrate pull-up resistor. output, driven VDDIO, pull-up resistor. JTAGSEL used select JTAG boundary scan when asserted high level. JTAGSEL integrates permanent pull-down resistor about GND, that left unconnected normal operations.
Test
used manufacturing test fast programming mode AT91SAM7SE512/256/32 when asserted high. integrates permanent pull-down resistor about GND, that left unconnected normal operations. enter fast programming mode, pins should tied high tied low. Driving high level while driven leads unpredictable results.
Reset
NRST bidirectional. handled on-chip reset controller driven provide reset signal external components asserted externally reset microcontroller. There constraint length reset pulse, reset controller guarantee minimum pulse length. This allows connection simple push-button NRST system user reset, NRST signal reset components system. external power-on reset drive this during start-up instead using internal power-on reset circuit. NRST integrates permanent pull-up about resistor VDDIO. This 5V-tolerant schmitt trigger input.
ERASE
ERASE used re-initialize Flash content some bits. integrates permanent pull-down resistor about GND, that left unconnected normal operations. This debounced oscillator improve glitch tolerance. When tied high during less than ERASE taken into account. must tied high during more than perform re-initialization Flash.
SDCK
SDCK dedicated SDRAM Clock output-only without pull-up 5V-tolerant. Maximum Output Frequency this 3.0V 1.65V with maximum load
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Controller lines
lines PA31, PB31, PC23 integrate programmable pull-up resistor. Programming this pull-up resistor performed independently each line through controllers. Typical pull-up value lines have schmitt trigger inputs.
Lines Current Drawing
lines high-drive current capable. Each these lines drive permanently. remaining lines draw only However, total current drawn lines cannot exceed
AT91SAM7SE512/256/32 [Advance Information Summary]
6222AS-ATARM-21-Aug-06
AT91SAM7SE512/256/32 [Advance Information Summary]
Processor Architecture
ARM7TDMI Processor
RISC processor based ARMv4T Neumann architecture Runs MHz, providing MIPS/MHz instruction sets ARM® high-performance 32-bit instruction Thumb® high code density 16-bit instruction Three-stage pipeline architecture Instruction Fetch Instruction Decode Execute
Debug Test EmbeddedICE(Integrated embedded in-circuit emulator) watchpoint units Test access port accessible through JTAG protocol Debug communication channel Debug Unit Two-pin UART Debug communication channel interrupt handling Chip Register IEEE1149.1 JTAG Boundary-scan digital pins
Memory Controller
Programmable Arbiter Handles requests from ARM7TDMI Peripheral Controller Address decoder provides selection signals Four internal Mbyte memory areas 256-Mbyte embedded peripheral area Eight external 256-Mbyte memory areas Abort Status Registers Source, Type parameters access leading abort saved Facilitates debug detection pointers Misalignment Detector Alignment checking data accesses Abort generation case misalignment Remap Command Remaps SRAM place embedded non-volatile memory Allows handling dynamic exception vectors 16-area Memory Protection Unit (Internal Memory peripheral protection only)
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Individually programmable size between Byte Byte Individually programmable protection against write and/or user access Peripheral protection against write and/or user access Embedded Flash Controller Embedded Flash interface, three programmable wait states Prefetch buffer, buffering anticipating 16-bit requests, reducing required wait states Key-protected program, erase lock/unlock sequencer Single command erasing, programming locking operations Interrupt generation case forbidden operation
External Interface
Integrates Three External Memory Controllers: Static Memory Controller SDRAM Controller Controller Additional Logic NAND Flash CompactFlash® Support NAND Flash support: 8-bit well 16-bit devices supported CompactFlash support: modes (Attribute Memory, Common Memory, I/O, True IDE) supported signals _IOIS16 (I/O True modes) -ATA (True mode) handled. Optimized External Bus: 32-bit Data (32-bit Data SDRAM only) 23-bit Address Bus, 8-Mbytes Addressable Chip Selects, each reserved eight Memory Areas Optimized multiplexing reduce latencies External Memories Configurable Chip Select Assignment: Static Memory Controller NCS0 SDRAM Controller Static Memory Controller NCS1 Static Memory Controller NCS2, Optional CompactFlash Support Static Memory Controller NCS3, NCS5 NCS6, Optional NAND Flash Support Static Memory Controller NCS4, Optional CompactFlash Support Static Memory Controller NCS7
Static Memory Controller
External memory mapping, 512-Mbyte address space 16-bit Data Chip Select Lines Multiple Access Modes supported Byte Write Byte Select Lines different Read Protocols each Memory Bank
AT91SAM7SE512/256/32 [Advance Information Summary]
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AT91SAM7SE512/256/32 [Advance Information Summary]
Multiple device adaptability Compliant with Module Programmable Setup Time Read/Write Programmable Hold Time Read/Write Multiple Wait State Management Programmable Wait State Generation External Wait Request Programmable Data Float Time
SDRAM Controller
Numerous configurations supported Address Memory Parts SDRAM with four Internal Banks SDRAM with 32-bit Data Path Programming facilities Word, half-word, byte access Automatic page break when Memory Boundary been reached Multibank Ping-pong Access Timing parameters specified software Automatic refresh operation, refresh rate programmable Energy-saving capabilities Self-refresh, Low-power Modes supported Error detection Refresh Error Interrupt SDRAM Power-up Initialization software Latency clocks (CAS Latency Supported) Auto Precharge Command used
Error Corrected Code Controller
Tracking accesses NAND Flash device triggering corresponding chip select Single error correction 2-bit Random detection. Automatic Hamming Code Calculation while writing value available register Automatic Hamming Code Calculation while reading Error Report, including error flag, correctable error flag word address being detected erroneous Supports 16-bit NAND Flash devices with 512-, 1024-, 2048- 4096-byte pages
Peripheral Controller
Handles data transfer between peripherals memories Eleven channels
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each USART Debug Unit Serial Synchronous Controller Serial Peripheral Interface Analog-to-digital Converter arbitration overhead Master Clock cycle needed transfer from memory peripheral Master Clock cycles needed transfer from peripheral memory Next Pointer management reducing interrupt latency requirements
AT91SAM7SE512/256/32 [Advance Information Summary]
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AT91SAM7SE512/256/32 [Advance Information Summary]
Memories
Kbytes Flash Memory (AT91SAM7SE512) dual plane contiguous banks 1024 pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 write cycles, 10-year data retention capability lock bits, each protecting lock regions pages Protection Mode secure contents Flash Kbytes Flash Memory (AT91SAM7SE256) single plane bank 1024 pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 cycles, 10-year data retention capability lock bits, each protecting lock regions pages Protection Mode secure contents Flash Kbytes Flash Memory (AT91SAM7SE32) single plane bank pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 cycles, 10-year data retention capability lock bits, each protecting lock regions pages Protection Mode secure contents Flash Kbytes Fast SRAM (AT91SAM7SE512/256) Single-cycle access full speed Kbytes Fast SRAM (AT91SAM7SE32) Single-cycle access full speed
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Figure 8-1.
0x0000 0000
AT91SAM7SE Memory Mapping
Address Memory Space
0x0000 0000
Internal Memory Mapping Boot Memory Flash before Remap SRAM after Remap
Note: ROM, Flash SRAM depending GPNVM2 REMAP
Internal Memories
0x0FFF FFFF
MBytes
0x000F FFFF 0x0010 0000
MBytes
0x1000 0000 Chip Select
0x1FFF FFFF
MBytes
0x001F FFFF 0x0020 0000
Internal Flash
MBytes
0x2000 0000 Chip Select SDRAMC Chip Select Chip Select SMC/NANDFlash/ SmartMedia Chip Select Compact Flash Chip Select Compact Flash Chip Select
0x7FFF FFFF
MBytes
Internal SRAM
0x002F FFFF 0x0030 0000
MBytes
0x2FFF FFFF
0x3000 0000 MBytes
0x003F FFFF 0x0040 0000
Internal
MBytes
0x3FFF FFFF
0x4000 0000
MBytes
0x0FFF FFFF
Reserved
MBytes System Controller Mapping 0xFFFF F000
0x4FFF FFFF
0x5000 0000
MBytes
0xFFFF F1FF 0xFFFF F200 DBGU 0xFFFF F3FF 0xFFFF F400 Peripheral Mapping 0xF000 0000 PIOA Reserved 0xFFFF F5FF 0xFFFF F600 PIOB 0xFFFF F7FF 0xFFFF F800 PIOC Kbytes 0xFFFF F9FF 0xFFFF FA00 Reserved Kbytes Kbytes 0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F PWMC Reserved Reserved 0xFFFF FD60 Reserved SYSC 0xFFFF FFFF Kbytes 0xFFFF FC6F 0xFFFF FD70 0xFFFF FEFF 0xFFFF FF00 Kbytes Kbytes Kbytes 0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F 0xFFFF FBFF 0xFFFF FC00 Bytes/64 registers Bytes/128 registers Bytes/128 registers Bytes/128 registers Bytes/128 registers Bytes/128 registers
0x5FFF FFFF
0x6000 0000
MBytes
0x6FFF FFFF
0x7000 0000
MBytes
0x8000 0000 Chip Select
0x8FFF FFFF
MBytes
0xFFF9 FFFF 0xFFFA 0000 0xFFFA 3FFF 0xFFFA 4000 0xFFFA FFFF 0xFFFB 0000 0xFFFB 3FFF 0xFFFB 4000
TC0, TC1, Reserved Reserved
Kbytes
0x9000 0000
Kbytes
0xFFFB 7FFF 0xFFFB 8000 0xFFFB BFFF 0xFFFB C000 0xFFFB FFFF 0xFFFC 0000
Reserved USART0 USART1 Reserved
Undefined (Abort)
MBytes 1,536 MBytes
0xFFFC 3FFF 0xFFFC 4000 0xFFFC 7FFF 0xFFFC 8000 0xFFFC BFFF 0xFFFC C000 0xFFFC FFFF 0xFFFD 0000 0xFFFD 3FFF 0xFFFD 4000 0xFFFD 7FFF 0xFFFD 8000 0xFFFD BFFF 0xFFFD C000 0xFFFD FFFF 0xFFFE 0000
RSTC Reserved Reserved VREG Reserved
Bytes/4 registers
Bytes/4 registers Bytes/4 registers Bytes/4 registers
Bytes/1 register
0xEFFF FFFF
0xF000 0000 Internal Peripherals
0xFFFF FFFF
0xFFFE 3FFF 0xFFFE 4000
MBytes
0xFFFF EFFF 0xFFFF F000 0xFFFF FFFF
Bytes/64 registers
AT91SAM7SE512/256/32 [Advance Information Summary]
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AT91SAM7SE512/256/32 [Advance Information Summary]
first level address decoding performed Memory Controller, i.e., implementation Advanced System (ASB) with additional features. Decoding splits bytes address space into areas 256M bytes. areas directed that associates these areas external chip selects NCS7. area reserved addressing internal memories, second level decoding provides byte internal memory area. area reserved peripherals provides access Advanced Peripheral (APB). Other areas unused performing access within them provides abort master requesting such access.
8.1.1 8.1.1.1
Embedded Memories
Internal Memories Internal SRAM AT91SAM7SE512/256 embeds high-speed 32-Kbyte SRAM bank. AT91SAM7SE32 embeds high-speed 8-Kbyte SRAM bank. After reset until Remap Command performed, SRAM only accessible address 0x0020 0000. After Remap, SRAM also becomes available address 0x0.
8.1.1.2
Internal AT91SAM7SE512/256/32 embeds Internal ROM. time, mapped address 0x30 0000. contains FFPI SAM-BA boot program.
8.1.1.3
Internal Flash AT91SAM7SE512 features banks Kbytes Flash. AT91SAM7SE256 features bank Kbytes Flash. AT91SAM7SE32 features bank Kbytes Flash. time, Flash mapped address 0x0010 0000. general purpose (GPNVM) used boot either (default) from Flash. This GPNVM cleared respectively through commands "Clear General-purpose Bit" "Set General-purpose Bit" User Interface. Setting GPNVM selects boot from Flash, clearing selects boot from ROM. Asserting ERASE clears GPNVM thus selects boot from default.
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Figure 8-2.
Internal Memory Mapping with GPNVM (default)
0x0000 0000
0x000F FFFF
Before Remap SRAM After Remap Internal FLASH
Bytes
0x0010 0000 Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
Bytes Bytes Bytes
Internal
0x003F FFFF 0x0040 0000
Undefined Areas (Abort)
0x0FFF FFFF
Figure 8-3.
Internal Memory Mapping with GPNVM
0x0000 0000
0x000F FFFF
Flash Before Remap SRAM After Remap Internal FLASH
Bytes
0x0010 0000 Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
Bytes Bytes Bytes
Internal
0x003F FFFF 0x0040 0000
Undefined Areas (Abort)
0x0FFF FFFF
8.1.2 8.1.2.1
Embedded Flash Flash Overview Flash AT91SAM7SE512 organized banks (dual plane) 1024 pages bytes. reads 131,072 32-bit words. Flash AT91SAM7SE256 organized 1024 pages (single plane) bytes. reads 65,536 32-bit words. Flash AT91SAM7SE32 organized pages (single plane) bytes. reads 32,768 32-bit words. Flash AT91SAM7SE32 contains 128-byte write buffer, accessible through 32-bit interface. Flash AT91SAM7SE512/256 contains 256-byte write buffer, accessible through 32-bit interface.
AT91SAM7SE512/256/32 [Advance Information Summary]
6222AS-ATARM-21-Aug-06
AT91SAM7SE512/256/32 [Advance Information Summary]
Flash benefits from integration power reset cell from brownout detector. This prevents code corruption during power supply changes, even worst conditions. 8.1.2.2 Embedded Flash Controller Embedded Flash Controller (EFC) manages accesses performed masters system. enables reading Flash writing write buffer. also contains User Interface, mapped within Memory Controller APB. User Interface allows: programming access parameters Flash (number wait states, timings, etc.) starting commands such full erase, page erase, page program, set, clear, etc. getting status last command getting error status programming interrupts last commands errors Embedded Flash Controller also provides dual 32-bit Prefetch Buffer that optimizes 16-bit access Flash. This particularly efficient when processor running Thumb mode. EFCs (EFC0 EFC1) embedded SAM7SE512 control each plane KBytes. Dual plane organization allows concurrent Read Program. (EFC0) embedded SAM7SE256 control single plane KBytes. (EFC0) embedded SAM7SE32 control single plane KBytes. 8.1.2.3 Lock Regions AT91SAM7SE512 Embedded Flash Controller manages lock bits protect regions flash against inadvertent flash erasing programming commands. AT91SAM7SE512 contains lock regions each lock region contains pages bytes. Each lock region size Kbytes. AT91SAM7SE256 Embedded Flash Controller manages lock bits protect regions flash against inadvertent flash erasing programming commands. AT91SAM7SE256 contains lock regions each lock region contains pages bytes. Each lock region size Kbytes. AT91SAM7SE32 Embedded Flash Controller manages lock bits protect regions flash against inadvertent flash erasing programming commands. AT91SAM7SE32 contains lock regions each lock region contains pages bytes. Each lock region size Kbytes. locked-region's erase program command occurs, command aborted trigs interrupt. (AT91SAM7SE512), (AT91SAM7SE256) (AT91SAM7SE32) bits software programmable through User Interface. command "Set Lock Bit" enables protection. command "Clear Lock Bit" unlocks lock region. Asserting ERASE clears lock bits, thus unlocking entire Flash. 8.1.2.4 Security Feature AT91SAM7SE512/256/32 features security bit, based specific NVM-bit. When security enabled, access Flash, either through interface through Fast Flash Programming Interface, forbidden.
6222AS-ATARM-21-Aug-06
security only enabled through Command "Set Security Bit" User Interface. Disabling security only achieved asserting ERASE after full flash erase performed. When security deactivated, accesses flash permitted. important note that assertion ERASE should always longer than ERASE integrates permanent pull-down, left unconnected during normal operation. However, safer connect directly final application. 8.1.2.5 Non-volatile Brownout Detector Control general purpose (GPNVM) bits used controlling brownout detector (BOD), that even after power loss, brownout detector operations remain their state. These GPNVM bits cleared respectively through commands "Clear General-purpose Bit" "Set General-purpose Bit" User Interface. GPNVM used brownout detector enable bit. Setting GPNVM enables BOD, clearing disables BOD. Asserting ERASE clears GPNVM thus disables brownout detector default. GPNVM used brownout reset enable signal reset controller. Setting GPNVM enables brownout reset when brownout detected, Clearing GPNVM disables brownout reset. Asserting ERASE disables brownout reset default. 8.1.2.6 Calibration Bits Sixteen bits used calibrate brownout detector voltage regulator. These bits factory configured cannot changed user. ERASE effect calibration bits. 8.1.3 Fast Flash Programming Interface Fast Flash Programming Interface allows programming device through either serial JTAG interface through multiplexed fully-handshaked parallel port. allows gang-programming with market-standard industrial programmers. FFPI supports read, page program, page erase, full erase, lock, unlock protect commands. Fast Flash Programming Interface enabled Fast Programming Mode entered when pins tied high tied low. Flash AT91SAM7SE512 organized 2048 pages bytes (dual plane). reads 131,072 32-bit words. Flash AT91SAM7SE256 organized 1024 pages bytes (single plane). reads 65,536 32-bit words. Flash AT91SAM7SE32 organized pages bytes (single plane). reads 32,768 32-bit words. Flash AT91SAM7SE512/256 contains 256-byte write buffer, accessible through 32-bit interface. Flash AT91SAM7SE32 contains 128-byte write buffer, accessible through 32bit interface.
AT91SAM7SE512/256/32 [Advance Information Summary]
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AT91SAM7SE512/256/32 [Advance Information Summary]
8.1.4 SAM-BABoot SAM-BA Boot default Boot Program which provides easy program in-situ on-chip Flash memory. SAM-BA Boot Assistant supports serial communication DBGU Device Port. Communication DBGU supports wide range crystals from software auto-detection. Communication Device Port limited 18.432 crystal. SAM-BA Boot provides interface with SAM-BA Graphic User Interface (GUI). SAM-BA Boot mapped Flash address when GPNVM
External Memories
external memories accessed through External Interface. Refer memory Figure page
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System Controller
System Controller manages vital blocks microcontroller: interrupts, clocks, power, time, debug reset. System Controller peripherals mapped highest Kbytes address space, between addresses 0xFFFF F000 0xFFFF FFFF. Figure page shows System Controller Block Diagram. Figure page shows mapping User Interface System Controller peripherals. Note that Memory Controller configuration user interface also mapped within this address space.
AT91SAM7SE512/256/32 [Advance Information Summary]
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AT91SAM7SE512/256/32 [Advance Information Summary]
Figure 9-1. System Controller Block Diagram
System Controller
jtag_nreset
Boundary Scan Controller
irq0-irq1 periph_irq[2.18]
nirq
Advanced Interrupt Controller
nfiq proc_nreset debug
ARM7TDMI
pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq
power_on_reset force_ntrst
periph_nreset dbgu_rxd debug periph_nreset SLCK periph_nreset SLCK debug idle proc_nreset gpnvm[0] gpnvm[1] flash_wrdis power_on_reset jtag_nreset
Debug Unit
dbgu_irq force_ntrst dbgu_txd security_bit
Periodic Interval Timer Real-Time Timer Watchdog Timer
wdt_fault WDRPROC bod_rst_en
pit_irq flash_poe rtt_irq flash_wrdis wdt_irq gpnvm[0.2]
Embedded Flash
proc_nreset
Memory Controller
flash_poe
Reset Controller
periph_nreset proc_nreset
NRST SLCK
rstc_irq
Voltage Regulator Mode Controller
standby
Voltage Regulator
RCOSC
SLCK
periph_clk[2.18] pck[0-3]
UDPCK periph_clk[11] periph_nreset periph_irq[11] usb_suspend
XOUT
MAINCK
Power Management Controller
UDPCK
Device Port
PLLRC
PLLCK pmc_irq idle periph_clk[4.18] periph_nreset
periph_nreset usb_suspend
periph_nreset periph_clk[2-3] dbgu_rxd
periph_irq{2-3] irq0-irq1
Embedded Peripherals
Controller
dbgu_txd
periph_irq[4.18]
PA0-PA31 PB0-PB31 PC0-PC29 enable
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Reset Controller
Based power-on reset cell double brownout detector Status last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset Controls internal resets NRST output Allows shape signal NRST line, guaranteeing that length pulse meets requirement.
9.1.1
Brownout Detector Power Reset AT91SAM7SE512/256/32 embeds brownout detection circuit power-on reset cell. power-on reset supplied with monitors VDDCORE. Both signals provided Flash prevent code corruption during power-up powerdown sequences brownouts occur VDDCORE power supply. power-on reset cell limited-accuracy threshold around 1.5V. output remains during power-up until VDDCORE goes over this voltage level. This signal goes reset controller allows full re-initialization device. brownout detector monitors VDDCORE VDDFLASH levels during operation comparing fixed trigger level. secures system operations most difficult environments prevents code corruption case brownout VDDCORE VDDFLASH. When brownout detector enabled VDDCORE decreases value below trigger level (Vbot18-, defined Vbot18 hyst/2), brownout output immediately activated. When VDDCORE increases above trigger level (Vbot18+, defined Vbot18 hyst/2), reset released. brownout detector only detects drop voltage VDDCORE stays below threshold voltage longer than about 1µs. VDDCORE threshold voltage hysteresis about ensure spike free brownout detection. typical value brownout detector threshold 1.68V with accuracy factory calibrated. When brownout detector enabled VDDFLASH decreases value below trigger level (Vbot33-, defined Vbot33 hyst/2), brownout output immediately activated. When VDDFLASH increases above trigger level (Vbot33+, defined Vbot33 hyst/2), reset released. brownout detector only detects drop voltage VDDCORE stays below threshold voltage longer than about 1µs. VDDFLASH threshold voltage hysteresis about ensure spike free brownout detection. typical value brownout detector threshold 2.80V with accuracy 3.5% factory calibrated. brownout detector low-power, consumes less than static current. However, deactivated save static current. this case, consumes less than 1µA. deactivation configured through GPNVM Flash.
Clock Generator
Clock Generator embeds low-power Oscillator, Main Oscillator with following characteristics: Oscillator ranges between
AT91SAM7SE512/256/32 [Advance Information Summary]
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AT91SAM7SE512/256/32 [Advance Information Summary]
Main Oscillator frequency ranges between Main Oscillator bypassed output ranges between provides SLCK, MAINCK PLLCK. Figure 9-2. Clock Generator Block Diagram
Clock Generator
Embedded Oscillator
Slow Clock SLCK
XOUT
Main Oscillator
Main Clock MAINCK
PLLRC
Divider
Clock PLLCK
Status
Control
Power Management Controller
Power Management Controller
Power Management Controller uses Clock Generator outputs provide: Processor Clock Master Clock Clock UDPCK peripheral clocks, independently controllable three programmable clock outputs Master Clock (MCK) programmable from hundred maximum operating frequency device. Processor Clock (PCK) switches when entering processor idle mode, thus allowing reduced power consumption while waiting interrupt.
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Figure 9-3.
Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,.,/64 Peripherals Clock Controller ON/OFF Idle Mode
periph_clk[2.14]
Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,.,/64
pck[0.2]
Clock Controller ON/OFF PLLCK Divider /1,/2,/4
usb_suspend
UDPCK
Advanced Interrupt Controller
Controls interrupt lines (nIRQ nFIQ) Processor Individually maskable vectored interrupt sources Source reserved Fast Interrupt Input (FIQ) Source reserved system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.) Other sources control peripheral interrupts external interrupts Programmable edge-triggered level-sensitive internal sources Programmable positive/negative edge-triggered high/low level-sensitive external sources 8-level Priority Controller Drives normal interrupt nIRQ processor Handles priority interrupt sources Higher priority interrupts served during service lower priority interrupt Vectoring Optimizes interrupt service routine branch execution 32-bit vector register interrupt source Interrupt vector register reads corresponding current interrupt vector Protect Mode Easy debugging preventing automatic operations Fast Forcing Permits redirecting interrupt source fast interrupt General Interrupt Mask Provides processor synchronization events without triggering interrupt
AT91SAM7SE512/256/32 [Advance Information Summary]
6222AS-ATARM-21-Aug-06
AT91SAM7SE512/256/32 [Advance Information Summary]
Debug Unit
Comprises: two-pin UART Interface Debug Communication Channel (DCC) support Chip Registers Interface providing Access Prevention Two-pin UART USART-compatible User Interface Programmable Baud Rate Generator Parity, Framing Overrun Error Automatic Echo, Local Loopback Remote Loopback Channel Modes Debug Communication Channel Support Offers visibility COMMRX COMMTX signals from Processor Chip Registers Identification device revision, sizes embedded memories, peripherals Chip 0x272A 0A40 (VERSION AT91SAM7SE512 Chip 0x272A 0940 (VERSION AT91SAM7SE256 Chip 0x2728 0340 (VERSION AT91SAM7SE32
Periodic Interval Timer
20-bit programmable counter plus 12-bit interval counter
Watchdog Timer
12-bit key-protected Programmable Counter running prescaled SLCK Provides reset interrupt signals system Counter stopped while processor debug state idle mode
Real-time Timer
32-bit free-running counter with alarm running prescaled SLCK Programmable 16-bit prescaler SLCK accuracy compensation
Controllers
Three Controllers. each control lines controls lines. Fully programmable through set/clear registers Multiplexing peripheral functions line each line (whether assigned peripheral used general-purpose I/O) Input change interrupt Half clock period glitch filter Multi-drive option enables driving open drain Programmable pull-up each line data status register, supplies visibility level time
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Synchronous output, provides Clear several lines single write
9.10
Voltage Regulator Controller
purpose this controller select Power Mode Voltage Regulator between Normal Mode (bit cleared) Standby Mode (bit set).
AT91SAM7SE512/256/32 [Advance Information Summary]
6222AS-ATARM-21-Aug-06
AT91SAM7SE512/256/32 [Advance Information Summary]
Peripherals
10.1 User Interface
User Peripherals mapped MBytes address space between 0xF000 0000 0xFFFF EFFF. Each peripheral allocated Kbytes address space. complete memory presented Figure page
10.2
Peripheral Identifiers
AT91SAM7SE512/256/32 embeds wide range peripherals. Table 10-1 defines Peripheral Identifiers AT91SAM7SE512/256/32. Unique peripheral identifiers defined both Advanced Interrupt Controller Power Management Controller. Table 10-1.
Peripheral 16-28
Peripheral Identifiers
Peripheral Mnemonic SYSIRQ PIOA PIOB PIOC PWMC
Peripheral Name Advanced Interrupt Controller
External Interrupt
Parallel Controller Parallel Controller Parallel Controller Serial Peripheral Interface USART USART Synchronous Serial Controller Two-wire Interface Controller Device Port Timer/Counter Timer/Counter Timer/Counter Analog-to Digital Converter
reserved Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1
Note:
Setting SYSIRQ bits clock set/clear registers effect. System Controller continuously clocked. clock automatically started first conversion. Sleep Mode clock automatically stopped after each conversion.
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10.3
Peripheral Multiplexing Lines
AT91SAM7SE512/256/32 features three controllers, PIOA, PIOB PIOC, that multiplex lines peripheral set. Controller control lines; Controller controls lines. Each line assigned peripheral functions, Some them also multiplexed with analog inputs Controller. Table 10-2 page defines lines peripherals analog inputs multiplexed Controller columns "Function" "Comments" have been inserted user's comments; they used track pins defined application. Note that some peripheral functions that output only duplicated table. reset, lines automatically configured input with programmable pull-up enabled, that device maintained static state soon reset detected.
AT91SAM7SE512/256/32 [Advance Information Summary]
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AT91SAM7SE512/256/32 [Advance Information Summary]
10.4 Controller Multiplexing
Table 10-2.
Multiplexing Controller
Controller Application Usage Comments High-Drive High-Drive High-Drive High-Drive Function Comments
Line PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
Peripheral PWM0 PWM1 PWM2 TWCK RXD0 TXD0 RTS0 CTS0 DRXD DTXD NPCS0 MISO MOSI SPCK RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DTR1 DSR1 IRQ1 NPCS1
Peripheral A0/NBS0 A1/NBS2 A16/BA0 A17/BA1 NBS3/CFIOW NCS4/CFCS0 NCS2/CFCS1 NCS6/CFCE2 NCS5/CFCE1 NWR1/NBS1/CFIOR SDA10 SDCKE NCS1/SDCS SDWE
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10.5
Controller Multiplexing
Table 10-3.
Multiplexing Controller
Controller Application Usage Comments Function Comments
Line PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31
Peripheral TIOA0 TIOB0 SCK0 NPCS3 TCLK0 NPCS3 PCK0 PWM3 ADTRG NPCS1 NPCS2 PWM0 PWM1 PWM2 PWM3 TIOA1 TIOB1 PCK1 PCK2 IRQ0 PCK1 NPCS3 PWM0 PWM1 PWM2 TIOA2 TIOB2 TCLK1 TCLK2 NPCS2 PCK2
Peripheral A0/NBS0 A1/NBS2 A16/BA0 A17/BA1
AT91SAM7SE512/256/32 [Advance Information Summary]
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AT91SAM7SE512/256/32 [Advance Information Summary]
10.6 Controller Multiplexing
Multiplexing Controller
Controller Line PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 CFRNW Peripheral A21/NANDALE A22/REG/NANDCLE NCS7 NWR0/NWE/CFWE NRD/CFOE NCS0 NPCS1 NCS3/NANDCS NWAIT NANDOE NANDWE RTS1 DTR1 PCK0 PCK1 PCK2 Peripheral Comments Application Usage Function Comments
10.7
Serial Peripheral Interface
Supports communication with external serial devices Four chip selects with external decoder allow communication with peripherals Serial memories, such DataFlash® 3-wire EEPROMs Serial peripherals, such ADCs, DACs, Controllers, Controllers Sensors External co-processors Master slave serial peripheral interface
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16-bit programmable data length chip select Programmable phase polarity chip select Programmable transfer delays chip select, between consecutive transfers between clock data Programmable delay between consecutive transfers Selectable mode fault detection Maximum frequency Master Clock
10.8
Wire Interface
Master, Multi-Master Slave Mode Operation Compatibility with standard two-wire serial memories One, three bytes slave address Sequential read/write operations Rate: Kbit/s General Call Supported Slave Mode
10.9
USART
Programmable Baud Rate Generator 9-bit full-duplex synchronous asynchronous serial communications stop bits Asynchronous Mode stop bits Synchronous Mode Parity generation error detection Framing error detection, overrun error detection first Optional break generation detection over-sampling receiver frequency Hardware handshaking Modem Signals Management DTR-DSR-DCD-RI USART1 Receiver time-out transmitter timeguard Multi-drop Mode with address generation detection RS485 with driver control signal ISO7816, Protocols interfacing with smart cards NACK handling, error counter with repetition iteration limit IrDA® modulation demodulation Communication 115.2 Kbps Test Modes Remote Loopback, Local Loopback, Automatic Echo
10.10 Serial Synchronous Controller
Provides serial synchronous communication links used audio telecom applications Contains independent receiver transmitter common clock divider
AT91SAM7SE512/256/32 [Advance Information Summary]
6222AS-ATARM-21-Aug-06
AT91SAM7SE512/256/32 [Advance Information Summary]
Offers configurable frame sync data length Receiver transmitter programmed start automatically detection different event frame sync signal Receiver transmitter include data signal, clock signal frame synchronization signal
10.11 Timer Counter
Three 16-bit Timer Counter Channels Three output compare input capture Wide range functions including: Frequency measurement Event counting Interval measurement Pulse generation Delay timing Pulse Width Modulation Up/down capabilities Each channel user-configurable contains: Three external clock inputs Five internal clock inputs, defined Table 10-4 Table 10-4. Timer Counter Clocks Assignment
Clock input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024
multi-purpose input/output signals global registers that three channels
10.12 Controller
Four channels, 16-bit counter channel Common clock generator, providing thirteen different clocks Modulo counter providing eleven clocks independent linear dividers working modulo counter outputs Independent channel programming Independent enable/disable commands Independent clock selection Independent period duty cycle, with double buffering Programmable selection output waveform polarity Programmable center left aligned output waveform
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10.13 Device Port
V2.0 full-speed compliant,12 Mbits second. Embedded V2.0 full-speed transceiver Embedded 2688-byte dual-port endpoints Eight endpoints Endpoint 64bytes Endpoint bytes ping-pong Endpoint bytes Endpoint bytes ping-pong Endpoint bytes ping-pong Ping-pong Mode (two memory banks) Isochronous bulk endpoints Suspend/resume logic Integrated Pull-up
10.14 Analog-to-Digital Converter
8-channel 10-bit Ksamples/sec. 8-bit Ksamples/sec. Successive Approximation Register -3/+3 Integral Linearity, -2/+2 Differential Linearity Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs External voltage reference better accuracy voltage inputs Individual enable disable each channel Multiple trigger sources Hardware software trigger External trigger Timer Counter outputs TIOA0 TIOA2 trigger Sleep Mode conversion sequencer Automatic wakeup trigger back sleep mode after conversions enabled channels Each analog input shared with digital signals
AT91SAM7SE512/256/32 [Advance Information Summary]
6222AS-ATARM-21-Aug-06
AT91SAM7SE512/256/32 [Advance Information Summary]
Package Drawings
Figure 11-1. 128-lead LQFP Package Drawing
Table 11-1.
Device LQFP Package Maximum Weight
AT91SAM7SE512/256/32
Table 11-2.
Package Reference
MS-026
JEDEC Drawing Reference JESD97 Classification
Table 11-3.
LQFP Package Characteristics
Moisture Sensitivity Level
This package respects recommendations NEMI User Group.
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Figure 11-2. 144-ball LFBGA Package Drawing
dimensions
Table 11-4.
Device LFBA Package Maximum Weight
AT91SAM7SE512/256/32
Table 11-5.
Package Reference
MS-026
JEDEC Drawing Reference JESD97 Classification
Table 11-6.
LFBGA Package Characteristics
Moisture Sensitivity Level
This package respects recommendations NEMI User Group.
AT91SAM7SE512/256/32 [Advance Information Summary]
6222AS-ATARM-21-Aug-06
AT91SAM7SE512/256/32 [Advance Information Summary]
Ordering Information
Table 12-1. Ordering Information
Package LQFP128 LQFP128 LQFP128 LFBGA144 LFBGA144 LFBGA144 Package Type Green Green Green Green Green Green Temperature Operating Range Industrial (-40° Industrial (-40° Industrial (-40° Industrial (-40° Industrial (-40° Industrial (-40°
Ordering Code AT91SAM7SE512-AU AT91SAM7SE256-AU AT91SAM7SE32-AU AT91SAM7SE512-CJ AT91SAM7SE256-CJ AT91SAM7SE32-CJ
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Revision History
Doc.
Comments First issue
Change Request Ref.
622AS
Revised Memories with condensed mapping. Added Package Outlines 144-ball LFBGA ordering information.
#2709
AT91SAM7SE512/256/32 [Advance Information Summary]
6222AS-ATARM-21-Aug-06
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AT91 Thumb-based Microcontrollers AT91SAM7SE512 AT91SAM7SE256 AT91SAM7

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