Dual 13x16 Matrix Head Driver DRIVES 13X16 MATRIX HEADS HEAD TEMP
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L6452
Dual 13x16 Matrix Head Driver
DRIVES 13X16 MATRIX HEADS HEAD TEMPERATURE SENSING POWER SYSTEM ELECTRICAL NOZZLE CHECK PROTECTED OUTPUTS PQFP100
Description
L6452 device designed drive 13x16 matrix print heads printer applications. output stage able source simultaneously each power lines (columns) with duty cycle normal printing head pre-heating. address lines (rows), load only capacitive (MOS driving capability). driver control print heads, only active time. address scanning counter included disabled allow different scanning scheme. order avoid output activation during supply transient, internal power-up system implemented. supporting function, L6452 capable sensing head silicon temperature electrically check each nozzle. device protection. also integrating thermal
Order codes
Part number E-L6452 L6452DIE8 Temp range, Package PQFP100 Packing Tray
February 2006
1/22
www.st.com
Contents
L6452
Contents
Block diagrams description Electrical specifications
Absolute maximum ratings Electrical characteristics Counter Truth Table Decoder Truth Table
Print Head Temperature Control Part
Introduction Print Head Block Diagram (Figure
Package information Revision history
2/22
L6452
Block diagrams
Figure
Block diagrams
Block diagram
POWER LOGICAL SUPPLIES PRINT HEAD DRIVER POWER LINES
CONTROL LINES
ADDRESS LINES CHANNEL
PRINT HEAD
ADDRESS LINES CHANNEL
PRINT HEAD
PRINT HEAD TEMPERATURE CONTROL LINES
PRINT HEAD TEMPERATURE CONTROL
ANALOG INPUTS
D97IN523
Figure
Block Diagram: Power Line Output Stage.
1.25mA
DATA
OUTPUT0
DATA FROM DATA LATCH
OUTPUT1
DATA
LONGPULSE SHORTPULSE TRIGGER NCEN
D97IN525B
OUTPUT15
NCOUT
3/22
Block diagrams
L6452
Figure
Block Diagram: Nozzle activation part
LONGPULSE SHORTPULSE OUTPUT0 OUTPUT1 OUTPUT2 OUTPUT3 OUTPUT4 OUTPUT5 SERIAL INPUT PARALLEL OUTPUT OUTPUT6 LATCH POWER OUTPUT STAGES OUTPUT7 OUTPUT8 OUTPUT9 OUTPUT10 OUTPUT11 OUTPUT12 OUTPUT13 OUTPUT14 OUTPUT15
LATCHCLEAR LATCHDATA NCEN NCOUT
HSA1 HSA2 HSA3 HSA4 HSA5 DRIVERS CHANNEL UP/DOWN COUNTER HSA6 HSA7 HSA8 HSA9 HSA10 HSA11 HSA12 LINES DECODER HSA13
SELECTOR ENIC UPC/S2 RESC/S1 CLKC/S0
HSB1 HSB2 HSB3 HSB4 HSB5 DRIVERS CHANNEL HSB6 HSB7 HSB8 HSB9 HSB10
CHSEL ENCH
D97IN524A
HSB11 HSB12 HSB13
4/22
L6452
description
description
Figure connection (Top view)
STEPUPBOOST ONENABLE CRCLOCK STEPUPGND VSTEP-UP CLKC/S0 RESC/S1
CRDATA
UPC/S2
CSGND
CRLATCH OUTPUT15 POWGND OUTPUT14 OUTPUT13 OUTPUT12 OUTPUT11 OUTPUT10 OUTPUT9 OUTPUT8 POWGND OUTPUT7 OUTPUT6 OUTPUT5 OUTPUT4 OUTPUT3 OUTPUT2 OUTPUT1 POWGND OUTPUT0 LATCHCLEAR NCEN
D97IN489C
CHSEL
ENCH
REXT
ENIC HSA1 HSA2 HSA3 HSA4 HSA5 HSA6 HSA7 HSA8 HSA9 HSA10 HSA11 HSA12 HSA13 HSB13 HSB12 HSB11 HSB10 HSB9 HSB8 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1
ADCK
ADDATA
ANALOGND
CONVSTART
ADCGND
RESET
NCOUT
CH0BUF
VREF
LATCHDATA
LONGPULSE
Table
function
Name CRlatch Function rising edge transfer information from shift register into control register latching data falling edge
Output15.0
High side DMOS outputs. active, ShortPulse and/or LongPulse NcEn must have level
SHORTPULSE
5/22
description
L6452
function continued
Name Function
Table
Outputs Power Supply
LatchClear
logic power ground high level resets latch high level enables internal current sources disables DMOS outputs. active, internal current sources must have their corresponding latch LongPulse must level. This function called Nozzle Check Enable. rising edge latches stored shift register latch Serial data input shift register data presented stored into register rising edge this level activates outputs having their corresponding latch (this internal pull-up resistor) level activates outputs having their corresponding latch reset (this internal pull-up resistor) level disables functions clears registers high level enables start conversion clock signal; ADDATA signal valid falling edge this NcEn high this output provides high level when open load detected output. NcEn this output provides high level when short circuit detected HSA/B output Analog output signal (CH0 buffered) serial data output Analog ground connection Ground internal Power supply Reference voltage generator input signals Head selector address output channel Head Select Power Supply Head selector address output channel Enable Internal Counter: high level enables counter internal decoder will activate outputs according counter's outputs. Signal becomes ClkC becomes ResC
NcEn
LatchData LongPulse ShortPulse Reset ConvStart ADCK
NCOut CH0buf ADDATA AnalogGND ADCGND Vref CH5.CH1 HSB1.HSB13 HSA13.HSA1
EnlC
6/22
L6452
Table
description
function continued
Name ChSel UpC/S2 Function Channel Select: level enables channel high level enables channel Decoder input signals when EnIC UpCount/S2: high level enables internal counter counting. level enables down counting depending EnlC value becomes Reset Count/S1: level resets internal counter depending EnlC value becomes Enable Channel: level enables selected channel (this input internal pull resistor) high level clocks internal counter depending EnlC value becomes Ground step block Boost voltage Driving voltage power DMOS stage logic supply external resistor connected ground fixes internal current source value Current source outputs RxA, voltage after optional external filter level enables current source generator according ON/OFF control register Data CRdata stored into register rising edge this Control register serial data input
ResC/S1
EnCh
ClkC/S0 StepUpGND StepUpBoost VstepUp Rext RxB, VxA, OnEnable CRclock CRdata
7/22
Electrical specifications
L6452
Electrical specifications
Absolute maximum ratings
Table
Symbol Vstep_up Iout Tamb Tstg
Absolute maximum ratings
Parameter Power line supply voltage Address line supply voltage Analog supply voltage Logic supply voltage Driving voltage power DMOS stage accordance with 1000-4-2 Logic input voltage range Output continuous current Junction temperature Operating temperature range Storage temperature range Value -0.3 Unit
pins connected passed Contact Electrostatic Discharge ±4kV (150pF, 330Ohm source).
Table
Electrical characteristics
Electrical characteristics 25°C)
Parameter Power Line Supply voltage Address line supply voltage Analog supply voltage Logic supply voltage sleep supply current sleep supply current sleep supply current supply current supply current supply current IRext= OnEnable Reset
Symbol
Test Condition
Min. 10.5
Typ. 11.5 11.5 11.5
Max. 12.5 12.5 12.5
Unit
10.5 10.5
8/22
L6452
Table
Symbol Vref Irefext Iccs Iccs/Iccs Vampout
Electrical specifications
Electrical characteristics 25°C) continued
Parameter supply current Reference Voltage Reference current (external) Programmed constant current Constant current regulation Output voltage integrated amplifier Va=11V Tamb 55°C 0.33 Va-1 Test Condition sleep normal condition Tamb= 55°C 4.85 Min. Typ. Max. 5.15 13.5 Unit
Operating input voltage pins Vref= g1=1.2
Vstep-up
Amp. Voltage gain Amp.A2 Voltage gain Driving Voltage power DMOS
1.188 2.95
3.02
1.212 3.10
CONVERTER VA/D input voltage Selected Channel: Selected Ch=CH0 Input selected Vref Vref
Iexch
input current
OFFSET VOLTAGE GENERATION Voffset Vstep Kdac Offset Voltage Voltage increment (1LSB) Voffset/Vref Vref
Vref=
7.34
step
CONVERTER TIMINGS Tcscks Tcsckh Tckout Tcsz Fadck Tcslow ConvStart time ConvStart hold time Falling edge clock data valid delay ConvStart falling edge output Hi-Z delay Clock frequency Conv. Start level time Cload 20pF
9/22
Electrical specifications
L6452
Table
Symbol Tacqth Tacqpr
Electrical characteristics 25°C) continued
Parameter Theoretical acquisition time Real acquisition time Test Condition fadck= fadck= Min. 32.4 Typ. Max. Unit
DIGITAL INTERFACE INPUT Vinp Vinm
Vhys
Schmitt Trigger positive-going Threshold Schmitt Trigger negative-going Threshold Schmitt Trigger Hysteresis Input Current (Vin=0; Vdd=5) 1/3Vdd
2/3Vdd
LATCH TIMINGS Tlhigh Tlconv tstore Latch time Latch high time Latch data valid input valid delay Latching data time Selected channel: CH1.CH5
Note:
control register (driving signals CRdata, CRclock) accessed with same timing specifications data shift register (signals SDI, SDC)
SHIFT REGISTER LATCH TIMING Tset time Hold time Serial clock time Serial clock high time Serial clock period Latch time Latch data high time NcEn setup time with respect LongPulse ShortPulse) Asserted NcEn hold time with respect LongPulse ShortPulse) Asserted Set-up time from latch Pulse (short long) Time from Pulse deassertion data latching
Thold
10/22
L6452
Table
Symbol
Electrical specifications
Electrical characteristics 25°C) continued
Parameter Test Condition Min. Typ. Max. Unit
OUTPUTS ELECTRICAL CHARACTERISTICS Iout Rds(ON) Tpdr Output Current (outputs 0.15) Resistance Power output Turn Time DC=33%; preheating DC=66% 25°C From LongPulse power output rising edge Load parallel with 1.5nF From LongPulse power output falling edge Load parallel with 1.5nF
Rpon
Toff delay time Open Nozzle Check
HEAD ADDRESS SELECTOR OUTPUT UpC/S2, ResC/S1, ChSel, ClkC/S0 EnIC set-up time with respect EnCh UpC/S2, ResC/S1, ChSel, ClkC/S0 EnIC hold time with respect EnCh UpC/S2 with respect hold time ClkC/S0 UpC/S2 with respect setup time ClkC/S0 Enable input active output delay time Clock active output delay time Disable input inactive output delay time Counter Clock Frequency Clock duty cycle Address Turn time Address Turn time From ClkC/S0 selector signal address output variation Load: Figure
fclk-counter Clkdc Toff
three supply voltage independent inside specified value; Min. value power line been verified down application lab.; nevertheless parameters guaranteed within spec limit above ELECTRICAL CHARACTERISTICS table. Vstep This applies input pins having internal pull-up (ENCH, LONGPULSE, SHORTPULSE)
11/22
Electrical specifications
L6452
Counter Truth Table
EnIC UpC/S2 ResC/S1
Clock Counter
EnIC UpC/S2 ResC/S1
Clock Counter
12/22
L6452
Electrical specifications
Decoder Truth Table
OUTPUTS (HS) ACTIVE inactive inactive inactive
when EnIC This table valid both Channel Channel when EnCh level.
13/22
Print Head Temperature Control Part
L6452
Print Head Temperature Control Part
Introduction
quality printing, necessary know control temperature print head. Thus, latter built aluminium resistor, whose value changes slightly with temperature. temperature determination done injecting constant current resistor, measuring voltage drop across Since high printers have heads, must also possible switch quickly measurement process from other. function foreseen integrated into head driver, described hereafter.
Print Head Block Diagram (Figure
first have constant current source, which disabled external (OnEnable) control register, described later. value current programmed external resistor, given This current injected either into resistor head (Ralu. (Ralu. depending switch SW3. resistors grounded, voltage their side (Vx) re-entered pins VxB. Using separate pins from permits more flexible, filter eventually added shown drawing. voltage amplified then converted digital value. compatible with input range converter, necessary subtract offset voltage Voffset from Moreover, initial value aluminum resistor very imprecise. Voffset must adjustable; this done means converter, giving different values. Finally, voltage input converter VCH0 VOFFSET VCH0 Ralu ICCS VOFFSET; VOFFSET VREF/2 VREF/32 reference voltage generator (VREF) integrated, used current source both converters. this way, system performance independent from precision VREF; this should, however, stable. Vref also available #45, used consumption purposes. (The external sinked current current). system under control register, accessed serially transparent latch, which used trying latch signal latch VCC).
14/22
L6452
Figure Print Head Block Diagram
Print Head Temperature Control Part
VREF VOLT VREF VREF CONVSTART ADCK ADDATA VOFFSET VREF CH0BUF INPUTS
REXT
HIGH-SIDE CONSTANT CURRENT SOURCE
VREF/2
ONENABLE
LATCH
CRLATCH CONTROL REGISTER CRCLOCK CRDATA
SHIFT REG. ON/OFF ADDR2 ADDR1 ADDR0
RXA,
VXA,
ANALOG
RALU
RALU Note; analog ground separated from digital ground remaining part driver
D97IN533C
Figure
Control Register details.
SHIFT DIRECTION
ON/OFF
ADDR2 ADDR1 ADDR0
SELECTION RESISTOR (A/B (A/B TEMPERATURE MEASUREMENT
INPUTS OFFSET COMPENSATION POSITIVE LOGIC
CHANNEL SELECTION INPUT
D97IN534B
INTERNAL CHANNEL MEASUREMENT) FIVE UNCOMMITTED, GENRAL-PURPOSE EXTERNAL CHANNELS
SWITCHES CURRENT SOURCE OFF; LINKED WITH ONENABLE INPUT
ADDR2 ADDR1 ADDR0 CHANNEL ADDRESS
(INTERNAL) (EXTERNAL) (EXTERNAL) (EXTERNAL) (EXTERNAL) (EXTERNAL)
CH0BUF
ON/OFF
ONENABLE
ACTION
15/22
Print Head Temperature Control Part
L6452
Figure
Latch Timings
CRDATA ADDR2 ADDR1 ADDR0
CRCLOCK
tlhigh tstore
CRLATCH
tlconv
CONVSTART
D97IN535B
Figure
CONVSTART
Converter Timings
ADCK
ADDATA
HIGH IMPEDANCE
tcscks tcsckh
tckout
HIGH IMPEDANCE
tcsx
D97IN536
Figure
Power Output Timing
LONGPULSE SHORTPULSE
POWER OUTPUT
tpdr
D97IN526B
does include falling edge time because this strictly dependent load.
Figure Trigger Nozzle Check Signal
VPOWER FROM COMMON CONNECTION ANALOG MULTIPLEXERS VLOGIC NOZZLE CHECK OUTPUT
INTERNAL REFERENCE NCEN
HSA/B SHORT CIRCUIT DETECTION
D97IN527A
16/22
L6452
Figure Address load reference
Print Head Temperature Control Part
OUTPUT 250pF
Figure Mode Counter
UpC/S2
ResC/S1
ChSel
EnIC
ClkC/S0
EnCh
HSA1 HSB1
D97IN529B
17/22
Print Head Temperature Control Part
L6452
Figure Mode Selelector
ChSel
EnIC
EnCh
HSA1 HSB1
D97IN530A
Figure Sequence Shift Register Data Loading
LATCHDATA LONGPULSE SHORTPULSE OUTPUT OUTPUT CORRESPONDING DATA CORRESPONDING DATA RESET
D97IN531C
18/22
L6452
Figure Latch Timing
Print Head Temperature Control Part
SDCK
LATCHDATA
D97IN532A
19/22
Package information
L6452
Package information
order meet environmental requirements, offers these devices ECOPACK® packages. These packages have Lead-free second level interconnect. category second Level Interconnect marked package inner label, compliance with JEDEC Standard JESD97. maximum ratings related soldering conditions also marked inner label. ECOPACK trademark. ECOPACK specifications available www.st.com.
Figure PQFP100 Mechanical Data Package Dimensions
DIM. MIN. 0.65 16.95 13.90 0.25 2.55 0.22 0.13 22.95 19.90 23.20 20.00 18.85 0.65 17.20 14.00 12.35 0.80 1.60 0°(min.), 7°(max.) 0.95 0.026 17.45 14.10 0.667 0.547 2.80 3.05 0.38 0.23 23.45 20.10 TYP. MAX. 3.40 0.010 0.100 0.0087 0.005 0.903 0.783 0.913 0.787 0.742 0.026 0.677 0.551 0.486 0.031 0.063 0.037 0.687 0.555 0.110 0.120 0.015 0.009 0.923 0.791 MIN. inch TYP. MAX. 0.134
OUTLINE MECHANICAL DATA
PQFP100
20/22
L6452
Revision history
Revision history
Date 15-Mar-1999 Revision Initial release. Modified Electrical Specification Time Diagrams. Modified signal names through spec. Modified Table function pins Added parameter Table Absolute maximum ratings. Modified Table Tset, Thold Rpon parameters. Modified Figure Changes
06-Feb-2006
21/22
L6452
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