PIC24FJ128GA010 Family Rev. Silicon Errata PIC24FJ128GA010 family
|
|
|
Top Searches for this datasheet
PIC24FJ128GA010
PIC24FJ128GA010 Family Rev. Silicon Errata
PIC24FJ128GA010 family Rev. parts have received conform functionally Device Data Sheet (DS39747C), except anomalies described below. Data Sheet Clarification issues related PIC24FJ128GA010 Family will reported separate Data Sheet errata. Please check Microchip site existing issues. following silicon errata apply only PIC24FJ128GA010 devices with these Device/ Revision IDs: Part Number PIC24FJ128GA010 PIC24FJ96GA010 PIC24FJ64GA010 PIC24FJ128GA008 PIC24FJ96GA008 PIC24FJ64GA008 PIC24FJ128GA006 PIC24FJ96GA006 PIC24FJ64GA006 Device 040Dh 040Ch 040Bh 040Ah 0409h 0408h 0407h 0406h 0405h Revision
Module: JTAG
current JTAG programming implementation compatible with third party programmers using (Serial Vector Format) description language. JTAG boundary scan supported third party JTAG solutions affected. Work around Program devices with In-Circuit Serial ProgrammingTM. JTAG programming accomplished using custom JTAG software. current implementation supported future PIC24F revisions. JTAG boundary scan supported. Date Codes that pertain this issue: engineering production devices.
Module:
Master mode (MODE<1:0> 10), backto-back operations cause PMRD signal generated. This limitation occurs when peripheral configured zero wait states (WAITM<3:0> 0000). Work around PMRD signal will generated correctly minimum instruction cycle delay inserted between back-to-back operations. instruction, other instruction, adequate. Selecting delay other than zero will also permit PMRD signal generated. Date Codes that pertain this issue: engineering production devices.
Device (DEVID DEVREV) located last implemented addresses program memory. They shown hexadecimal format "DEVID DEVREV".
Module: Core
With Doze mode enabled, DOZEN (CLKDIV<11>) set, Peripheral Clock Ratio Select bits (CLKDIV<14:12>) configured value except 0b000, writes locations performed. Work around Disable Doze mode, select peripheral clock ratio before modifying stated locations, avoid writing stated locations while Doze mode enabled peripheral clock ratio other than selected. Configure device prior entering Doze mode mode only monitor applications activity. Date Codes that pertain this issue: engineering production devices.
Module: Interrupts
device exit Doze mode certain trap conditions occur. Address error, stack error math error traps affected. Oscillator failure interrupt sources affected cause device correctly exit Doze mode. Work around None. Date Codes that pertain this issue: engineering production devices.
2007 Microchip Technology Inc.
DS80330A-page
PIC24FJ128GA010
Module: Output Compare
output compare module output single glitch after module enabled (OCM<2:0> 000). This issue occurs when output state associated Data Latch register (LATx) opposite state Output Compare mode when peripheral enabled. also occur when switching between Output Compare modes with opposite output states. Work around output glitch must avoided, verify that associated data latch value matches initial state desired Output Compare mode. example, Output Compare configured mode, OCM<2:0> 001, ensure that LATD<4> clear prior writing bits. port latch output value will match initial output state avoid glitch when peripheral enabled. Date Codes that pertain this issue: engineering production devices.
Module: UART
UART1 UART2 hardware flow control options available 64-pin variants PIC24FJ128GA010 product family. result, UxCTS UxRTS pins available UEN<1:0> control bits read (unimplemented). UART2 hardware flow control available 80-pin PIC24FJ128GA010 variants. Therefore associated pins bits available these devices. Work around None. Date Codes that pertain this issue: engineering production devices.
Module: UART
When UART High-Speed mode (BRGH auto-baud sequence calculate baud rate were Low-Speed mode. Work around calculated baud rate modified following equation: Value (Auto-Baud user should verify baud rate error does exceed application limits. Date Codes that pertain this issue: engineering production devices.
Module: UART
timing transmitting Sync Break changed this revision silicon. Sync Break transmitted soon UTXBRK set. dummy write UxTXREG still required must performed before Sync Break finished transmitting. Otherwise, UxTX held active state until write occurred. Work around UTXBRK when Sync Break required perform dummy UxTXREG immediately following. This sequence will avoid holding UxTX active state. Date Codes that pertain this issue: engineering production devices.
Module: UART
With auto-baud feature selected, Sync Break character (0x55) loaded into FIFO data. Work around prevent Sync Break character from being loaded into FIFO, load UxBRG register with either 0x0000 0xFFFF prior enabling auto-baud feature (ABAUD Date Codes that pertain this issue: engineering production devices.
Module: UART
When UART High-Speed mode, BRGH (UxMODE<3>) set, some optimal UxBRG values cause reception fail. Work around Test UxBRG values application find UxBRG value that works consistently more high-speed applications. User should verify that UxBRG baud rate error does exceed application limits. Date Codes that pertain this issue: engineering production devices.
DS80330A-page
2007 Microchip Technology Inc.
PIC24FJ128GA010
Module:
Gain error high LSbs external references (VREF+ VREF-) LSbs internal reference (AVDD AVSS). Work around Determine gain error from known reference voltage compensate result software. Date Codes that pertain this issue: engineering production devices.
Module:
Master mode receptions using SPI1 SPI2 modules function correctly rates above Mbps master (SPIxCON1<9>) cleared (master samples data middle serial clock period). this case, data transmitted slave received, shifted right bit, master. example, data transmitted slave 0xAAAA, data received master would 0x5555 (0xAAAA shifted right bit). Work around Users module that rate Mbps lower. Alternatively, rate configured higher than Mbps, (SPIxCON1<9>) master must (master samples data serial clock period). Date Codes that pertain this issue: engineering production devices.
Module:
With External Interrupt (INT0) selected start conversion (SSRC<2:0> 001), device wake-up from Sleep Idle mode more than conversion selected interrupt (SMPI<3:0> 0000). Interrupts generated correctly device Sleep Idle mode. Work around Configure generate interrupt after every conversion (SMPI<3:0> 0000). another wake-up source, such another interrupt source, exit Sleep Idle mode. Alternatively, perform conversions mode. Date Codes that pertain this issue: engineering production devices.
Module:
frame synchronization pulse output Master mode pulse selected coincide with first clock (SPIFE SCKx SDOx waveforms affected. Work around Select frame sychronization pulses proceed first clock (SPIFE frame pulses will output correctly described product data sheet. Date Codes that pertain this issue: engineering production devices.
Module:
Enhanced modes, selected setting Enhanced Buffer Enable bit, SPIBEN (SPIxCON2<0>), available. Work around Standard mode clearing Enhanced Buffer Enable bit, SPIBEN. Date Codes that pertain this issue: engineering production devices.
2007 Microchip Technology Inc.
DS80330A-page
PIC24FJ128GA010
Module:
Slave mode (MSTEN with slave select option enabled (SSEN peripheral accept transfers regardless state. received data SSPxBUF will accurate intended device. Work around Slave select option required (e.g., device multiple slave nodes network), potential work arounds exist: Configure port associated with input periodically read PORT register. read `0', disable peripheral (SPIEN Enable peripheral (SPIEN read logic `1'. Read associated with after transfer complete, indicated SPIxF being set. port read digital `1', read SSPxBUF discard contents. Date Codes that pertain this issue: engineering production devices.
Module: Core
clock failure occurs when device Idle mode, oscillator failure trap does vector Trap Service Routine. Instead, device will simply wake-up from Idle mode continue code execution Fail-Safe Clock Monitor (FSCM) enabled. Work around Whenever device wakes from Idle (assuming FSCM enabled), user software should check status OSCFAIL (INTCON1<1>) determine whether clock failure occurred then perform appropriate clock switch operation. Date Codes that pertain this issue: engineering production devices.
Module: Core
Brown-out Reset, both bits set. This cause Brown-out Reset condition indistinguishable from Power-on Reset. Work around None. Date Codes that pertain this issue: engineering production devices.
Module: Oscillator
Two-Speed Start-up feature available exit from Sleep mode with IESO (Internal/External Switchover mode) enabled. Upon wake-up, device will wait clock source used prior entering Sleep mode become ready. Work around None. Date Codes that pertain this issue: engineering production devices.
Module: Ports
RC15 output digital after Reset until Configuration Word settings processed. duration time this effect TRST which nominally After Configuration Word processed, RC15 into reset state digital input. Work around Connect components adversely affected digital signal RC15. Date Codes that pertain this issue: engineering production devices.
Module: Core
CLKDIV register Reset value incorrect. register will reset with unimplemented bits equal Resets. Work around Mask unimplemented bits maintain software compatibility with future device revisions. Date Codes that pertain this issue: engineering production devices.
DS80330A-page
2007 Microchip Technology Inc.
PIC24FJ128GA010
Module: I2CDuring Slave mode transactions, Data/ Address bit, D/A, update during data frame. This affects both 10-Bit Addressing modes. slave receptions affected this issue. Work around Read/Write bit, R/W, Transmit Buffer Full Status Bit, TBF, determine whether address data information being received. more information, Figure 24-30 Figure 24-31 "Section Inter-Integrated Circuit(I2CTM)" (DS39702A). Date Codes that pertain this issue: engineering production devices.
Module: UART
auto-baud miscalculate certain baud rates clock speed combinations, resulting value that greater less than expected value. When UxBRG less than this result transmission reception failures introducing error greater than Work around Test auto-baud calculations various clock speed baud rate combinations that would used applications. inaccurate UxBRG value generated, manually correct baud rate user code. Date Codes that pertain this issue: engineering production devices.
Module:
When module operating Slave mode, after ACKSTAT when receiving NACK from master, cleared reception Start Stop bit. Work around Store value ACKSTAT immediately after receiving NACK from master. Date Codes that pertain this issue: engineering production devices.
Module: UART
When UART mode (BRGH using Stop bits (STSEL sample first Stop instead second one. This issue does affect other UART configurations. Work around baud rate option (BRGH adjust baud rate accordingly. Date Codes that pertain this issue: engineering production devices.
Module: UART
When auto-baud detected, receive interrupt occur twice. first interrupt occurs beginning Start second after reception Sync field character. Work around receive interrupt occurs, check URXDA (UxSTA<0>) ensure that valid data available. first interrupt, data will present. second interrupt will have Sync field character (55h) receive FIFO. Date Codes that pertain this issue: engineering production devices.
Module:
Master mode, Disable bit, DISSCK, disable clock. result, PIC® microcontroller must provide clock Master mode. Work around None. Date Codes that pertain this issue: engineering production devices.
2007 Microchip Technology Inc.
DS80330A-page
PIC24FJ128GA010
Module: Output Compare
mode, output compare module miss compare event when current duty cycle register (OCxRS) value 0x0000 duty cycle) OCxRS register updated with value 0x0001. compare event only missed first time value 0x0001 written OCxRS output remains period. Subsequent high times occur expected. Work around current OCxRS register value 0x0000, avoid writing value 0x0001 OCxRS. Instead, write value 0x0002. this case, however, duty cycle will slightly different from desired value. Date Codes that pertain this issue: engineering production devices.
Module: RTCC
When performing writes ALCFGRPT register, some bits become corrupted. error occurs because desynchronization between clock domain RTCC clock domain. error causes data from instruction following ALCFGRPT instruction overwrite data ALCFGRPT. Work around Always follow writes ALCFGRPT register with additional write same data dummy location. These writes performed locations, registers unimplemented space. optimal perform work around: Read ALCFGRPT into location. Modify ALCFGRPT data, required, RAM. Move value into ALCFGRPT dummy location back-to-back instructions. Date Codes that pertain this issue: engineering production devices.
Module: RTCC
RTCC alarm repeat will generate incorrect number toggles. repeat count even, will toggle alarm times. repeat count odd, less than toggles will observed Work around None this time. Date Codes that pertain this issue: engineering production devices.
Module:
FIFO overflow occurs, VWORD indicator will reset instead `0'. Further writes FIFO will cause VWORD indicator reset after seven writes performed. Work around Poll CRCFUL (CRCCON<7>) ensure that writes performed FIFO when full. Date Codes that pertain this issue: engineering production devices.
DS80330A-page
2007 Microchip Technology Inc.
PIC24FJ128GA010
Module: Pins
output, VOL, meets specifications Table below:
TABLE
CHARACTERISTICS: OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.0V 3.6V (unless otherwise stated) Operating temperature -40°C +85°C Industrial Typ(1) Units Conditions
CHARACTERISTICS Param DO10 Characteristic Output Voltage Pins
3.6V 3.6V 2.0V 2.0V
Note
Data "Typ" column 3.3V, 25°C unless otherwise stated. Parameters design guidance only tested.
Work around None.
2007 Microchip Technology Inc.
DS80330A-page
PIC24FJ128GA010
REVISION HISTORY
Document (9/2007) Initial release this document. Includes silicon issues (Core), (JTAG), (PMP), (Interrupts), (Output Compare), 6-10 (UART), 11-12 (A/D), 13-16 (SPI), (Oscillator), 18-20 (Core), (Ports), 22-23 (I2CTM), 24-26 (UART), (SPI), (Output Compare), 29-30 (RTCC), (CRC) (I/O Pins).
DS80330A-page
2007 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, rfPIC SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2007, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2007 Microchip Technology Inc.
DS80330A-page
WORLDWIDE SALES SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Address: www.microchip.com Atlanta Duluth, Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, Tel: 765-864-8360 Fax: 765-864-8387 Angeles Mission Viejo, Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 China Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256
ASIA/PACIFIC
India Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 82-2-558-5934 Malaysia Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Hsin Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
09/10/07
DS80330A-page
2007 Microchip Technology Inc.
Other recent searches
SD400C - SD400C SD400C Datasheet
LND1117 - LND1117 LND1117 Datasheet
AN-358-2 - AN-358-2 AN-358-2 Datasheet
AN1844 - AN1844 AN1844 Datasheet
2SC5868 - 2SC5868 2SC5868 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
