Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Output

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Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Output

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19-2093; 2/07
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs
Single Operation Excellent Dynamic Performance 59dB 20MHz 73dB SFDR 20MHz Power 82mA (Normal Operation) 2.8mA (Sleep Mode) (Shutdown Mode) 0.02dB Gain 0.25° Phase Matching (typ) Wide ±1VP-P Differential Analog Input Voltage Range 400MHz, -3dB Input Bandwidth On-Chip 2.048V Precision Bandgap Reference User-Selectable Output Format-Two's Complement Offset Binary 48-Pin TQFP Package with Exposed Improved Thermal Dissipation Evaluation Available
MAX1181
MAX1181 dual 10-bit, analog-to-digital converter (ADC) featuring fully-differential wideband track-and-hold (T/H) inputs, driving pipelined, ninestage ADCs. MAX1181 optimized low-power, high-dynamic performance applications imaging, instrumentation, digital communication applications. MAX1181 operates from single 2.7V 3.6V supply, consuming only 246mW, while delivering typical signal-to-noise ratio (SNR) 59dB input frequency 20MHz sampling rate 80Msps. driven input stages incorporate 400MHz (-3dB) input amplifiers. converters also operated with single-ended inputs. addition operating power, MAX1181 features 2.8mA sleep mode, well power-down mode conserve power during idle periods. internal 2.048V precision bandgap reference sets full-scale range ADC. flexible reference structure allows internal external reference, desired applications requiring increased accuracy different input voltage range. MAX1181 features parallel, CMOS-compatible three-state outputs. digital output format two's complement straight offset binary through single control pin. device provides separate output power supply 1.7V 3.6V flexible interfacing. MAX1181 available 7mm, 48-pin TQFP package, specified extended industrial (-40°C +85°C) temperature range. Pin-compatible higher lower speed versions MAX1181 also available. Please refer MAX1180 datasheet 105Msps, MAX1182 datasheet 65Msps, MAX1183 datasheet 40Msps, MAX1184 datasheet 20Msps. addition these speed grades, this family includes 20Msps multiplexed output version (MAX1185), which digital data presented time-interleaved single, parallel 10-bit output port.
Ordering Information
PART MAX1181ECM MAX1181ECM+ TEMP RANGE -40°C +85°C -40°C +85°C PIN-PACKAGE TQFP-EP* TQFP-EP*
Exposed paddle. +Denotes lead-free package.
Configuration
REFN REFP REFIN REFOUT
INA+ INAVDD INBINB+
OGND OVDD OVDD OGND
Applications
High-Resolution Imaging Channel Digitization Multichannel Undersampling Instrumentation Video Application
MAX1181
Functional Diagram appears data sheet.
NOTE: INDICATOR LEAD-FREE PACKAGES REPLACED SIGN.
Maxim Integrated Products
SLEEP
TQFP-EP
pricing, delivery, ordering information, please contact Maxim Direct 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD .-0.3V +3.6V OGND GND.-0.3V +0.3V INA+, INA-, INB+, INB- .-0.3V REFIN, REFOUT, REFP, REFN, CLK, .-0.3V (VDD 0.3V) SLEEP, T/B, D9A-D0A, D9B-D0B OGND .-0.3V (OVDD 0.3V) Continuous Power Dissipation +70°C) 48-Pin TQFP-EP (derate 30.4mW/°C above +70°C) .2430mW Operating Temperature Range .-40°C +85°C Junction Temperature .+150°C Storage Temperature Range .-60°C +150°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD OVDD 2.5V; 0.1µF 1.0µF capacitors from REFP, REFN, GND; REFOUT connected REFIN through resistor, 2VP-P (differential with respect COM), 10pF digital outputs (Note fCLK 83.333MHz, TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Note
PARAMETER ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Differential Input Voltage Range Common-Mode Input Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS Signal-to-Noise Ratio (Note Signal-to-Noise Distortion (Note Spurious-Free Dynamic Range (Note Third-Harmonic Distortion (Note fINA 7.47MHz, +25°C fINA 20MHz, +25°C fINA 39.9MHz fINA 7.47MHz, +25°C fINA 20MHz, +25°C fINA 39.9MHz fINA 7.47MHz, +25°C fINA 20MHz, +25°C fINA 39.9MHz fINA 7.47MHz fINA 20MHz fINA 39.9MHz 56.5 55.3 59.5 58.5 58.5 fCLK Clock Cycles VDIFF Switched capacitor load Differential single-ended inputs ±1.0 VDD/2 7.47MHz 7.47MHz, missing codes guaranteed ±0.6 ±0.4 ±2.2 ±1.0 Bits SYMBOL CONDITIONS UNITS
SINAD
SFDR
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
ELECTRICAL CHARACTERISTICS (continued)
(VDD OVDD 2.5V; 0.1µF 1.0µF capacitors from REFP, REFN, GND; REFOUT connected REFIN through resistor, 2VP-P (differential with respect COM), 10pF digital outputs (Note fCLK 83.333MHz, TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Note
PARAMETER Total Harmonic Distortion (First Four Harmonics) (Note Intermodulation Distortion (First Five Odd-Order IMDs) Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time Differential Gain Differential Phase Output Noise INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation REFIN Input Voltage Positive Reference Output Voltage Negative Reference Output Voltage Differential Reference Output Voltage Range REFIN Resistance Maximum REFP, Source Current Maximum REFP, Sink Current Maximum REFN Source Current Maximum REFN Sink Current REFOUT TCREF 2.048 1.25 VREFIN VREFP VREFN VREF RREFIN ISOURCE ISINK ISOURCE ISINK VREF VREFP VREFN 0.95 2.048 2.012 0.988 1.024 1.10 ppm/°C mV/mA INA+ INA- INB+ INB- FPBW full-scale input SYMBOL CONDITIONS fINA 7.47MHz, +25°C fINA 20MHz, +25°C fINA 39.9MHz fINA 38.1546MHz -6.5dBFS fINA 41.9532MHz -6.5dBFS (Note Input -20dBFS, differential inputs Input -0.5dBFS, differential inputs -73.5 ±0.25 psRMS degrees LSBRMS UNITS
BUFFERED EXTERNAL REFERENCE (VREFIN 2.048V)
UNBUFFERED EXTERNAL REFERENCE (VREFIN AGND, reference voltage applied REFP, REFN REFP, REFN Input Resistance RREFP, RREFN Measured between REFP REFN
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
ELECTRICAL CHARACTERISTICS (continued)
(VDD OVDD 2.5V; 0.1µF 1.0µF capacitors from REFP, REFN, GND; REFOUT connected REFIN through resistor, 2VP-P (differential with respect COM), 10pF digital outputs (Note fCLK 83.333MHz, TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Note
PARAMETER Differential Reference Input Voltage Input Voltage REFP Input Voltage REFN Input Voltage SYMBOL VREF VCOM VREFP VREFN CONDITIONS VREF VREFP VREFN 1.024 VCOM VREF VCOM VREF OVDD OVDD OVDD (CLK) ISINK 200µA ISOURCE 200µA OVDD OVDD Operating, fINA 20MHz -0.5dBFS Analog Supply Current IVDD Sleep mode Shutdown, clock idle, OVDD Operating, 15pF fINA 20MHz -0.5dBFS Output Supply Current IOVDD Sleep mode Shutdown, clock idle, OVDD Operating, fINA 20MHz -0.5dBFS Power Dissipation PDISS Sleep mode Shutdown, clock idle, OVDD OVDD UNITS
DIGITAL INPUTS (CLK, SLEEP, T/B) Input High Threshold SLEEP, Input Threshold SLEEP, Input Hysteresis Input Leakage Input Capacitance Output-Voltage Output-Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Range Output Supply Voltage Range OVDD VHYST ILEAK COUT
DIGITAL OUTPUTS (D9A-D0A, D9B-D0B)
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD OVDD 2.5V; 0.1µF 1.0µF capacitors from REFP, REFN, GND; REFOUT connected REFIN through resistor, 2VP-P (differential with respect COM), 10pF digital outputs (Note fCLK 83.333MHz, TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Note
PARAMETER Power Supply Rejection TIMING CHARACTERISTICS Rise Output Data Valid Output Enable Time Output Disable Time Pulse-Width High Pulse-Width Wake-Up Time (Note tENABLE tDISABLE tWAKE Figure (Note Figure Figure Figure clock period: 12ns Figure clock period: 12ns Wakeup from sleep mode Wakeup from shutdown fINA 20MHz -0.5dBFS fINA 20MHz -0.5dBFS fINA 20MHz -0.5dBFS 0.28 0.02 0.25 ±0.2 SYMBOL PSRR Offset Gain CONDITIONS ±0.2 ±0.1 UNITS mV/V
MAX1181
CHANNEL-TO-CHANNEL MATCHING Crosstalk Gain Matching Phase Matching degrees
Note Equivalent dynamic performance obtainable over full OVDD range with reduced Note Specifications +25°C guaranteed production test +25°C guaranteed design characterization. Note SNR, SINAD, THD, SFDR, based analog input voltage -0.5dBFS, referenced +1.024V full-scale input voltage range. Note Intermodulation distortion total power intermodulation products relative individual carrier. This number better, referenced two-tone envelope. Note Digital outputs settle VIH, VIL. Parameter guaranteed design. Note With REFIN driven externally, REFP, COM, REFN left floating while powered down.
Typical Operating Characteristics
(VDD OVDD 2.5V, internal reference, differential input -0.5dBFS, fCLK 80.0006MHz, 10pF. +25°C, unless otherwise noted.)
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
MAX1181 toc01
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
MAX1181 toc02
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
AMPLITUDE (dB) -100 fINA 19.9123MHz fINB 24.9123MHz fCLK 80.0006MHz AINA -0.52dBFS
MAX1181 toc03
AMPLITUDE (dB) -100 fINA 6.0449MHz fINB 7.5099MHz fCLK 80.0006MHz AINA -0.46dBFS
AMPLITUDE (dB) -100 fINA 6.0449MHz fINB 7.5099MHz fCLK 80.0006MHz AINB -0.52dBFS
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
Typical Operating Characteristics (continued)
(VDD OVDD 2.5V, internal reference, differential input -0.5dBFS, fCLK 80.0006MHz, 10pF. +25°C, unless otherwise noted.)
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
MAX1181 toc04
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
MAX1181 toc05
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
AMPLITUDE (dB) -100 fINA 40.4202MHz fINB 47.0413MHz fCLK 80.0006MHz AINB -0.53dBFS
MAX1181 toc06
AMPLITUDE (dB)
AMPLITUDE (dB) -100 fINA 40.4202MHz fINB 47.0413MHz fCLK 80.0006MHz AINA -0.52dBFS
-100
fINA 19.9123MHz fINB 24.9123MHz fCLK 80.0006MHz AINB -0.53dBFS
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE PLOT (8192-POINT RECORD, COHERENT SAMPLING)
MAX1181 toc07
SIGNAL-TO-NOISE RATIO ANALOG INPUT FREQUENCY
MAX1181 toc08
SIGNAL-TO-NOISE DISTORTION ANALOG INPUT FREQUENCY
MAX1181 toc09
AMPLITUDE (dB) -100 ORDER fIN1 38.1546MHz fIN2 41.9632MHz fCLK 80.0006MHz AIN1 AIN2 -6dBFS fIN1
(dB)
fIN2
SINAD (dB)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION ANALOG INPUT FREQUENCY
MAX1181 toc10
SPURIOUS-FREE DYNAMIC RANGE ANALOG INPUT FREQUENCY
MAX1181 toc11
FULL-POWER INPUT BANDWIDTH ANALOG INPUT FREQUENCY (SINGLE-ENDED)
MAX1181 toc12
SFDR (dBc)
(dBc)
GAIN (dB)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
1000 ANALOG INPUT FREQUENCY (MHz)
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
Typical Operating Characteristics (continued)
(VDD OVDD 2.5V, internal reference, differential input -0.5dBFS, fCLK 80.0006MHz, 10pF. +25°C, unless otherwise noted.)
SMALL-SIGNAL INPUT BANDWIDTH ANALOG INPUT FREQUENCY (SINGLE-ENDED)
100mVP-P GAIN (dB) 1000 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT POWER (dBFS) ANALOG INPUT POWER (dBFS) (dB)
MAX1181 toc13
SIGNAL-TO-NOISE RATIO ANALOG INPUT POWER (fIN 20MHz)
MAX1181 toc14
SIGNAL-TO-NOISE DISTORTION ANALOG INPUT POWER (fIN 20MHz)
MAX1181 toc15
SINAD (dB)
TOTAL HARMONIC DISTORTION ANALOG INPUT POWER (fIN 20MHz)
MAX1181 toc16
SPURIOUS-FREE DYNAMIC RANGE ANALOG INPUT POWER (fIN 20MHz)
MAX1181 toc17
INTEGRAL NONLINEARITY (BEST-STRAIGHT-LINE FIT)
(LSB) -0.2 -0.4 -0.6 -0.8 -1.0
MAX1181 toc18
-100 ANALOG INPUT POWER (dBFS)
SFDR (dBc) ANALOG INPUT POWER (dBFS)
(dBc)
1024 DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
MAX1181 toc19
GAIN ERROR TEMPERATURE, EXTERNAL REFERENCE (VREFIN 2.048V)
MAX1181 toc20
OFFSET ERROR TEMPERATURE, EXTERNAL REFERENCE (VREFIN 2.048V)
MAX11811 toc21
(LSB) -0.2 -0.4 -0.6 -0.8 -1.0
GAIN ERROR (LSB)
OFFSET ERROR (LSB)
TEMPERATURE (°C) TEMPERATURE (°C)
1024 DIGITAL OUTPUT CODE
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
Typical Operating Characteristics (continued)
(VDD OVDD 2.5V, internal reference, differential input -0.5dBFS, fCLK 80.0006MHz, 10pF. +25°C, unless otherwise noted.)
ANALOG SUPPLY CURRENT ANALOG SUPPLY VOLTAGE
MAX1181 toc22
ANALOG SUPPLY CURRENT TEMPERATURE
MAX11811 toc23
ANALOG POWER-DOWN CURRENT ANALOG POWER SUPPLY
OVDD
MAX1181 toc24
IVDD (mA)
IVDD (mA)
IVDD
2.70 2.85 3.00 3.15 3.30 3.45 3.60
TEMPERATURE (°C)
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SNR/SINAD, -THD/SFDR CLOCK DUTY CYCLE
MAX1181 toc25
INTERNAL REFERENCE VOLTAGE ANALOG SUPPLY VOLTAGE
MAX1181 toc26
SNR/SINAD, -THD/SFDR (dB, dBc) SFDR
fINA 24.9123MHz
2.075
2.065 VREFOUT
-THD CLOCK DUTY CYCLE SINAD
2.055
2.045
2.035
2.025 2.70 2.85 3.00 3.15 3.30 3.45 3.60
INTERNAL REFERENCE VOLTAGE TEMPERATURE
MAX11811 toc27
OUTPUT NOISE HISTOGRAM INPUT)
129377
MAX1181 toc28
2.10
140000 120000 100000
2.08 VREFOUT
COUNTS
2.06
80000 60000 40000
2.04
2.02 20000 2.00 TEMPERATURE (°C)
DIGITAL OUTPUT NOISE
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs
Description
NAME INA+ INAINBINB+ FUNCTION Common-Mode Voltage Input/Output. Bypass with 0.1µF capacitor. Analog Supply Voltage. Bypass each supply with 0.1µF capacitor. analog supply voltage accepts 2.7V 3.6V input range. Analog Ground Channel Positive Analog Input. single-ended operation, connect signal source INA+. Channel Negative Analog Input. single-ended operation, connect INA- COM. Channel Negative Analog Input. single-ended operation, connect INB- COM. Channel Positive Analog Input. single-ended operation, connect signal source INB+. Converter Clock Input selects digital output format. High: Two's complement. Low: Straight offset binary. Sleep Mode Input. High: Deactivates ADCs, leaves reference bias circuit active. Low: Normal operation. Power-Down Input. High: Power-down mode. Low: Normal operation. Output Enable Input. High: Digital outputs disabled. Low: Digital outputs enabled. Three-State Digital Output, (MSB), Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, (LSB), Channel Output Driver Ground Output Driver Supply Voltage. Bypass each supply OGND with 0.1µF capacitor. digital supply voltage accepts 1.7V 3.6V input range. Three-State Digital Output, (LSB), Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel
MAX1181
SLEEP
OGND OVDD
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
Description (continued)
NAME REFOUT REFIN REFP REFN Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, (MSB), Channel Internal Reference Voltage Output. connected REFIN through resistor resistor divider. Reference Input. VREFIN (VREFP VREFN). Bypass with capacitor. Positive Reference Input/Output. Conversion range ±(VREFP VREFN). Bypass with 0.1µF capacitor. Negative Reference Input/Output. Conversion range ±(VREFP VREFN). Bypass with 0.1µF capacitor. Exposed Paddle. Connect analog ground. FUNCTION
Detailed Description
MAX1181 uses nine-stage, fully-differential pipelined architecture (Figure that allows highspeed conversion while minimizing power consumption. Samples taken inputs move progressively through pipeline stages every half clock cycle. Counting delay through output latch, clockcycle latency five clock cycles. 1.5-bit (two-comparator) flash ADCs convert heldinput voltages into digital code. digital-to-analog converters (DACs) convert digitized results back into analog voltages, which then subtracted from original held-input signals. resulting error signals then multiplied two, residues passed along next pipeline stages where process repeated until signals have been processed nine stages. Digital error correction compensates comparator offsets each these pipeline stages ensures missing codes.
capacitors C2b. amplifiers used charge capacitors same values originally held C2b. These values then presented first-stage quantizers isolate pipelines from fast-changing inputs. wide input bandwidth amplifiers allow MAX1181 track sample/hold analog inputs high frequencies Nyquist). Both inputs (INA+, INB+, INA-, INB-) driven either differentially single-ended. Match impedance INA+ INA-, well INB+ INB-, common-mode voltage midsupply (VDD optimum performance.
Analog Inputs Reference Configurations
full-scale range MAX1181 determined internally generated voltage difference between REFP REFIN REFN VREFIN full-scale range both on-chip ADCs adjustable through REFIN pin, which provided this purpose. REFOUT, REFP, (VDD REFN internally buffered low-impedance outputs. MAX1181 provides three modes reference operation: Internal reference mode Buffered external reference mode Unbuffered external reference mode internal reference mode, connect internal reference output REFOUT REFIN through resistor (e.g., 10k) resistor divider, application requires reduced full-scale range.
Input Track-and-Hold (T/H) Circuits
Figure displays simplified functional diagram input track-and-hold (T/H) circuits both track-andhold mode. track mode, switches S2a, S2b, S4a, S4b, closed. fully-differential circuits sample input signals onto capacitors (C2a C2b) through switches S4b. common mode amplifier input, open simultaneously with sampling input waveform. Switches then opened before switches connect capacitors output amplifier switch closed. resulting differential voltages held
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
VOUT VOUT
FLASH BITS
FLASH BITS
2-BIT FLASH STAGE STAGE STAGE STAGE STAGE STAGE STAGE
2-BIT FLASH STAGE
DIGITAL CORRECTION LOGIC D9A-D0A
DIGITAL CORRECTION LOGIC D9B-D0B
VINA
VINB
VINA INPUT VOLTAGE BETWEEN INA+ INA- (DIFFERENTIAL SINGLE-ENDED) VINB INPUT VOLTAGE BETWEEN INB+ INB- (DIFFERENTIAL SINGLE-ENDED)
Figure Pipelined Architecture--Stage Blocks
stability noise filtering purposes, bypass REFIN with 10nF capacitor GND. internal reference mode, REFOUT, COM, REFP, REFN become lowimpedance outputs. buffered external reference mode, adjust reference voltage levels externally applying stable accurate voltage REFIN. this mode, COM, REFP, REFN become outputs. REFOUT left open connected REFIN through resistor. unbuffered external reference mode, connect REFIN GND. This deactivates on-chip reference buffers REFP, COM, REFN. With their buffers shut down, these nodes become high impedance driven through separate external reference sources.
log10 tAJ]), where represents analog input frequency time aperture jitter. Clock jitter especially critical undersampling applications. clock input should always considered analog input routed away from analog input other digital signal lines. MAX1181 clock input operates with voltage threshold Clock inputs with duty cycle other than must meet specifications high periods stated Electrical Characteristics table.
System Timing Requirements
Figure depicts relationship between clock input, analog input, data output. MAX1181 samples rising edge input clock. Output data channels valid next rising edge input clock. output data internal latency five clock cycles. Figure also determines relationship between input clock parameters valid output data channels
Clock Input (CLK)
MAX1181's input accepts CMOS-compatible clock signals. Since interstage conversion device depends repeatability rising falling edges external clock, clock with jitter fast rise fall times 2ns). particular, sampling occurs rising edge clock signal, requiring this edge provide lowest possible jitter. significant aperture jitter would limit performance on-chip ADCs follows:
Digital Output Data, Output Data Format Selection (T/B), Output Enable (OE)
digital outputs, D0A-D9A (Channel D0B-D9B (Channel TTL/CMOS logic-compatible. There
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
INTERNAL BIAS INA+ INTERNAL BIAS HOLD INTERNAL BIAS INB+ INTERNAL BIAS TRACK HOLD TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS
INA-
INB-
MAX1181
Figure MAX1181 Amplifiers
five clock cycle latency between particular sample corresponding output data. output coding chosen either straight offset binary two's complement (Table controlled single (T/B). Pull select offset binary high activate two's complement output coding. capacitive load digital outputs D0A-D9A D0B-D9B should
kept possible 15pF), avoid large digital currents that could feed back into analog portion MAX1181, thereby degrading dynamic performance. Using buffers digital outputs ADCs further isolate digital outputs from heavy capacitive loads. further improve dynamic performance
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
CLOCK-CYCLE LATENCY
ANALOG INPUT tCLK
CLOCK INPUT DATA OUTPUT D9A-D0A
DATA OUTPUT D9B-D0B
Figure System Timing Diagram
Table MAX1181 Output Codes Differential Inputs
DIFFERENTIAL INPUT VOLTAGE* VREF 511/512 VREF 1/512 -VREF 1/512 -VREF 511/512 -VREF 512/512 DIFFERENTIAL INPUT +FULL SCALE 1LSB Bipolar Zero FULL SCALE FULL SCALE STRAIGHT OFFSET BINARY 1111 1111 0000 0001 0000 0000 1111 1111 0000 0001 0000 0000 TWO'S COMPLEMENT 1111 1111 0000 0001 0000 0000 1111 1111 0000 0001 0000 0000
*VREF VREFP VREFN
MAX1181 small-series resistors (e.g., 100), digital output paths, close MAX1181. Figure displays timing relationship between output enable data output valid, well powerdown/wake-up data output valid.
value prior power-down. Pulling high, forces digital outputs into high-impedance state.
Applications Information
Figure depicts typical application circuit containing single-ended differential converters. internal reference provides output voltage levelshifting purposes. input buffered then split voltage follower inverter. lowpass filter suppresses some wideband noise associated with high-speed operational amplifiers. user select RISO values optimize filter performance suit particular application. application Figure RISO placed before capacitive load prevent ringing oscillation.
Power-Down (PD) Sleep (SLEEP) Modes
MAX1181 offers power-save modes; sleep full power-down mode. sleep mode (SLEEP only reference bias circuit active (both ADCs disabled) current consumption reduced 2.8mA. enter full power-down mode, pull high. With simultaneously low, outputs latched last
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
22pF capacitor acts small bypassing capacitor.
Using Transformer Coupling
transformer (Figure provides excellent solution convert single-ended source signal fully-differential signal, required MAX1181 optimum performance. Connecting center transformer provides level shift input. Although transformer shown, stepup transformer selected reduce drive requirements. reduced signal swing from input driver, such amp, also improve overall distortion. general, MAX1181 provides better SFDR with fully-differential input signals, than singleended drive, especially high input frequencies. differential input mode, even-order harmonics lower both inputs (INA+, INA- and/or INB+, INB-) balanced, each inputs only require half signal swing compared single-ended mode.
OUTPUT D9A-D0A
tENABLE HIGH IMPEDANCE
tDISABLE HIGH IMPEDANCE
VALID DATA
OUTPUT D9B-D0B
HIGH IMPEDANCE
VALID DATA
HIGH IMPEDANCE
Figure Output Timing Diagram
Grounding, Bypassing, Board Layout
MAX1181 requires high-speed board layout design techniques. Locate bypass capacitors close device possible, preferably same side ADC, using surface-mount devices minimum inductance. Bypass VDD, REFP, REFN, with parallel 0.1µF ceramic capacitors 2.2µF bipolar capacitor GND. Follow same rules bypass digital supply (OVDD) OGND. Multilayer boards with separate ground power planes, produce highest level signal integrity. Consider split ground plane arranged match physical location analog ground (GND) digital output driver ground (OGND) ADCs package. ground planes should joined single point, such that noisy digital ground currents interfere with analog ground plane. ideal location this connection determined experimentally point along between ground planes, which produces optimum results. Make this connection with low-value, surface-mount resistor ferrite bead, direct short. Alternatively, ground pins could share same ground plane, ground plane sufficiently isolated from noisy, digital systems ground plane (e.g., downstream output buffer ground plane). Route high-speed digital signal traces away from sensitive analog traces either channel. Make sure isolate analog input lines each respective converter minimize channelto-channel crosstalk. Keep signal lines short free degree turns.
Single-Ended AC-Coupled Input Signal
Figure shows AC-coupled, single-ended application. Amplifiers, like MAX4108, provide high-speed, high bandwidth, low-noise, distortion maintain integrity input signal.
Typical Demodulation Application
most frequently used modulation technique digital communications application Quadrature Amplitude Modulation (QAM). QAMs typically found spread-spectrum based systems. signal represents carrier frequency modulated both amplitude phase. transmitter, modulating baseband signal with quadrature outputs, local oscillator followed subsequent up-conversion generate signal. result in-phase quadrature carrier component, where component degrees phase-shifted with respect in-phase component. receiver, signal divided down into components, essentially representing modulation process reversed. Figure displays demodulation process performed analog domain, using dual-matched, 10-bit ADCs, MAX1181 MAX2451 quadrature demodulators, recover digitize baseband signals. Before being digitized MAX1181, mixed-down signal components filtered matched analog filters, such Nyquist pulse-shaping filters which remove unwanted images from mixing process, enhances overall signal-to-noise (SNR) performance, minimizes intersymbol interference.
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
0.1F LOWPASS FILTER MAX4108 0.1F INA+ RISO 22pF
0.1F
0.1F 0.1F INPUT 0.1F MAX4108 0.1F MAX4108 INARISO 0.1F 22pF LOWPASS FILTER
MAX1181
0.1F LOWPASS FILTER MAX4108 0.1F INB+ RISO 22pF
0.1F
0.1F 0.1F 0.1F LOWPASS FILTER INBRISO 0.1F 22pF
INPUT MAX4108 0.1F MAX4108
Figure Typical Application Single-Ended-to-Differential Conversion
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
INA+ 22pF 0.1F N.C. 2.2F 0.1F
Dynamic Parameter Definitions
Aperture Jitter
Figure depicts aperture jitter (tAJ), which sample-to-sample variation aperture delay.
Aperture Delay
Aperture delay (tAD) time defined between falling edge sampling clock instant when actual sample taken (Figure
MINI-CIRCUITS TT1-6 INA22pF MAX1181 INB+ 22pF 0.1F N.C. 2.2F 0.1F
Signal-to-Noise Ratio (SNR)
waveform perfectly reconstructed from digital samples, theoretical maximum ratio full-scale analog input (RMS value) quantization error (residual error). ideal, theoretical minimum analog-to-digital noise caused quantization error only results directly from ADC's resolution (N-Bits): SNR[max] 6.02 1.76 reality, there other noise sources besides quantization noise; thermal noise, reference noise, clock jitter, etc. computed taking ratio signal noise, which includes spectral components minus fundamental, first five harmonics, offset.
INB22pF
MINI-CIRCUITS TT1-6
Signal-to-Noise Plus Distortion (SINAD)
SINAD computed taking ratio signal spectral components minus fundamental offset.
Figure Transformer-Coupled Input Drive
Effective Number Bits (ENOB)
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity deviation values actual transfer function from straight line. This straight line either best straight-line line drawn between endpoints transfer function, once offset gain errors have been nullified. static linearity parameters MAX1181 measured using best straight-line method.
ENOB specifies dynamic performance specific input frequency sampling rate. ideal ADC's error consists quantization noise only. ENOB computed from: ENOB SINAD -1.76 6.02
Total Harmonic Distortion (THD)
typically ratio first four harmonics input signal fundamental itself. This expressed log10
Differential Nonlinearity (DNL)
Differential nonlinearity difference between actual step-width ideal value 1LSB. error specification less than 1LSB guarantees missing codes monotonic transfer function.
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
REFP
MAX4108
0.1F
RISO INA+ 22pF REFN 0.1F RISO
INACIN 22pF REFP
MAX1181
MAX4108
0.1F
RISO INB+ 22pF
REFN
0.1F RISO
INBCIN 22pF
Figure Using Single-Ended, AC-Coupled Input Drive
MAX2451
INA+ INA0°
MAX1181 INB+ INB-
POST PROCESSING
DOWNCONVERTER
Figure Typical Application, Using MAX1181
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
where fundamental amplitude, through amplitudes 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range (SFDR)
ANALOG INPUT SAMPLED DATA (T/H)
SFDR ratio expressed decibels amplitude fundamental (maximum signal component) value next largest spurious component, excluding offset.
Intermodulation Distortion (IMD)
two-tone ratio expressed decibels either input tone worst 3rd-order higher) intermodulation products. individual input tone levels -6.5dB full scale.
TRACK
HOLD
TRACK
Figure Aperture Timing
Functional Diagram
INA+ INAPIPELINE OUTPUT DRIVERS D9A-D0A OGND OVDD
CONTROL
INB+ INB-
PIPELINE
OUTPUT DRIVERS
D9B-D0B
REFERENCE
MAX1181
REFOUT REFN REFP REFIN
SLEEP
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
48L,TQFP.EPS
MAX1181
PACKAGE OUTLINE, TQFP, 7x7x1.0mm OPTION
21-0065
Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Outputs MAX1181
Package Information (continued)
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
PACKAGE OUTLINE, TQFP, 7x7x1.0mm OPTION
21-0065
Revision History
Pages changed 1-19
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2007 Maxim Integrated Products registered trademark Maxim Integrated Products, Inc.

Dual 10-Bit, 80Msps, Low-Power with Internal Reference Parallel Output

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