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TLC555C, TLC555I, TLC555M, TLC555Y LinCMOS TIMERS

D, DB, JG, P, OR PW PACKAGE (TOP VIEW)

TLC555C, TLC555I, TLC555M, TLC555Y LinCMOS TIMERS
SLFS043 - SEPTEMBER 1983 - REVISED OCTOBER 1993
D, DB, JG, P, OR PW PACKAGE (TOP VIEW)
GND TRIG OUT RESET
VDD DISCH THRES CONT
FK PACKAGE (TOP VIEW)
NC TRIG NC OUT NC
NC GND NC VDD NC NC DISCH NC THRES NC NC RESET NC
description
The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS process. The NC - No internal connection timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage. Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering. While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555. The TLC555C is characterized for operation from 0°C to 70°C. The TLC555I is characterized for operation from - 40°C to 85°C. The TLC555M is characterized for operation over the full military temperature range of - 55°C to 125°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015 however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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CONT NC
TLC555C, TLC555I, TLC555M, TLC555Y LinCMOS TIMERS
SLFS043 - SEPTEMBER 1983 - REVISED OCTOBER 1993
AVAILABLE OPTIONS PACKAGED DEVICES TA 0°C to 70°C - 40°C to 85°C - 55°C to 125°C VDD RANGE 2 V to 15 V 3 V to 15 V 5 V to 15 V SMALL OUTLINE (D) TLC555CD TLC555ID TLC555MD SSOP (DB) TLC555CDBLE - - CHIP CARRIER (FK) - - TLC555MFK CERAMIC DIP (JG) - - TLC555MJG PLASTIC DIP (P) TLC555CP TLC555IP TLC555MP TSSOP (PW) TLC555CPWLE - - TLC555Y CHIP FORM (Y)
functional block diagram
Pin numbers are for all packages except the FK package. RESET can override TRIG, which can override THRES.
POST OFFICE BOX 655303
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TLC555C, TLC555I, TLC555M, TLC555Y LinCMOSTMTIMERS
SLFS043 - SEPTEMBER 1983 - REVISED OCTOBER 1993
DISCH
COMPONENT COUNT
Transistors Resistors
GND TRIG RESET
equivalent schematic (each channel)
THRES
POST OFFICE BOX 655303 · DALLAS, TEXAS 75265
TLC555Y LinCMOS TIMERS
SLFS043 - D2784, SEPTEMBER 1983 - REVISED OCTOBER 1993
chip information
This chip, when properly assembled, displays characteristics similar to the TLC555. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS CONT VDD (5) (8) THRES (6) R RESET (4)
R TRIG
R (1) GND 64
DISCH
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TLC555C, TLC555I, TLC555M LinCMOS TIMERS
SLFS043 - D2784, SEPTEMBER 1983 - REVISED OCTOBER 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network GND.
recommended operating conditions
MIN Supply voltage, VDD TLC555C Operating f p g Op i g free-air temperature range, TA i TLC555I TLC555M 2 0 - 40 - 55 MAX 15 70 85 125 °C UNIT V
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TLC555C, TLC555I LinCMOS TIMERS
SLFS043 - D2784, SEPTEMBER 1983 - REVISED OCTOBER 1993
Full range is 0°C to 70°C for the TLC555C and - 40°C to 85°C for the TLC555I. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
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TLC555C, TLC555I, TLC555M LinCMOS TIMERS
SLFS043 - D2784, SEPTEMBER 1983 - REVISED OCTOBER 1993
IIT VI(TRIG)
Threshold voltage
II(TRIG)
VI(RESET)
II(RESET)
25°C Full range 25°C MAX 25°C Full range 25°C Full range 25°C Full range 25°C Full range 25°C Full range 4.1 4.1
V 0.4 0.6
Supply current
See Note 2
Full range is 0°C to 70°C the for TLC555C, - 40°C to 85°C for the TLC555I, and - 55°C to 125°C for the TLC555M. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.
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· DALLAS, TEXAS 75265
TLC555C, TLC555I, TLC555M LinCMOS TIMERS
SLFS043 - D2784, SEPTEMBER 1983 - REVISED OCTOBER 1993
PARAMETER TEST CONDITIONS TA 25°C Full range 25°C MAX 25°C Full range 25°C MAX 25°C Full range 25°C MAX 0.4 0.3 10 75 4.65 4.55 10 75 1.1 1.5 1.8 0.4 0.3 10 150 TLC555C MIN 9.45 9.35 10 75 5 5.35 5.45 4.65 4.55 10 150 1.1 1.5 1.8 0.4 0.3 10 5000 pA TYP 10 MAX 10.55 10.65 MIN 9.45 9.35 10 150 5 5.35 5.45 4.65 4.55 10 5000 1.1 1.5 1.8 V pA TLC555I TYP 10 MAX 10.55 10.65 MIN 9.45 9.35 10 5000 5 5.35 5.45 V pA TLC555M TYP 10 MAX 10.55 10.65 V UNIT
VIT IIT VI(TRIG) II(TRIG) VI(RESET) II(RESET)
Threshold voltage
Threshold current
Trigger voltage
Trigger current
Reset voltage
MAX 25°C Full range 25°C MAX 25°C Full range 25°C Full range 25°C Full range 25°C Full range 25°C Full range 25°C Full range 25°C Full range 12.5 12.5 13.5 13.5 14.2 14.2
1.7 1.8 V
0.1 120 14.2 nA
High level t t High-level output Hi h l l voltage
14.6 V 14.9
Low level t t Low-level output L l l voltage
Supply current
See Note 2
Full range is 0°C to 70°C for TLC555C, - 40°C to 85°C for TLC555I, and - 55°C to 125°C for TLC555M. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.
fmax Maximum frequency in astable mode
Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. NOTE 3: RA, RB, and CT are as defined in Figure 1.
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TLC555Y LinCMOS TIMER
SLFS043 - D2784, SEPTEMBER 1983 - REVISED OCTOBER 1993
VI(RESET) Reset voltage II(RESET) Reset current Control voltage (open circuit) as a percentage of supply voltage Discharge switch on-state voltage Discharge switch off-state current VOH VOL High-level output voltage Low-level output voltage
IDD Supply current See Note 2 170 350 NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIMES TO DISCHARGE OUTPUT FROM TRIGGER AND THRESHOLD SHORTED TOGETHER vs SUPPLY VOLTAGE
DISCHARGE SWITCH ON-STATE RESISTANCE vs FREE-AIR TEMPERATURE
tPHL tPLH
0 0 2 4 6 8 10 12 14 16 18 20 VDD - Supply Voltage - V The effects of the load resistance on these values must be taken into account separately.
TA - Free-Air Temperature - °C
Figure 1
Figure 2
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TLC555C, TLC555I, TLC555M LinCMOS TIMERS
SLFS043 - D2784, SEPTEMBER 1983 - REVISED OCTOBER 1993
APPLICATION INFORMATION
0.1 µF RA 0.1 µF 4 7 RB 6 THRES 2 CT TRIG GND 1 GND tPLH TRIGGER AND THRESHOLD VOLTAGE WAVEFORM VDD tPHL RL 3 Output CL 1 / 3 VDD 2 / 3 VDD tc(L)
tc(H)
5 8 CONT VDD RESET TLC555 DISCH OUT
Pin numbers shown are for all packages except the FK package. CIRCUIT
Figure 3. Astable Operation Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor CT charges through RA and RB to the trigger voltage level (approximately 0.67 VDD) and then discharges through RB only to the value of the threshold voltage level (approximately 0.33 VDD). The output is high during the charging cycle (tc(H)) and low during the discharge cycle (tc(L)). The duty cycle is controlled by the values of RA, RB, and CT as shown in the equations below. t
CT (RA ) RB) In 2 (In 2 + 0.693) CT RB In 2 + tc(H) ) tc(L) CT (RA ) 2RB) In 2 t R c(L) Output driver duty cycle + 1 - R )B2R t ) tc(L) c(H) A B
c(H) t c(L) Period Output waveform duty cycle
t c(H)
c(H) t
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· DALLAS, TEXAS 75265
TLC555C, TLC555I, TLC555M LinCMOS TIMERS
SLFS043 - D2784, SEPTEMBER 1983 - REVISED OCTOBER 1993
APPLICATION INFORMATION
The equations below provide better agreement with measured values. t
) ron)
) tPHL ) tPLH
+ CT (RB ) ron) In c(L)
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