DIT40 SBOS225 DECEMBER 2001 96kHz DIGITAL AUDIO TRANSMITTER

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DIT40 SBOS225 DECEMBER 2001 96kHz DIGITAL AUDIO TRANSMITTER

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DIT4096
DIT40
SBOS225 DECEMBER 2001
96kHz DIGITAL AUDIO TRANSMITTER
FEATURES
COMPLIANT WITH AES-3, IEC-60958, EIAJ CP1201 INTERFACE STANDARDS SUPPORTS SAMPLING RATES 96kHz SUPPORTS MONO-MODE OPERATION ON-CHIP DIFFERENTIAL LINE DRIVER FLEXIBLE AUDIO SERIAL INTERFACE: -Master Slave Mode Operation -Supports I2S, Left-Justified, Right-Justified Data Formats SOFTWARE MODE SERIAL CONTROL INTERFACE: -Block Sized Buffer Channel Status Data -Auto Increment Mode Block Sized Write Read Operations HARDWARE MODE ALLOWS OPERATION WITHOUT MICROCONTROLLER CODE GENERATION PROFESSIONAL MODE MASTER CLOCK RATE: 256fS, 384fS, 512fS SINGLE POWER SUPPLY PACKAGE: TSSOP-28
APPLICATIONS
DIGITAL MIXING CONSOLES DIGITAL MICROPHONES DIGITAL AUDIO WORKSTATIONS BROADCAST STUDIO EQUIPMENT EFFECTS PROCESSORS SURROUND-SOUND DECODERS ENCODERS RECEIVERS DVD, DAT, PLAYERS AUDIO TEST EQUIPMENT
DESCRIPTION
DIT4096 digital audio transmitter designed both professional consumer audio aplications. Transmit data rates 96kHz supported. DIT4096 supports both software hardware operation, which makes suitable applicaitons with without microcontroller. flexible serial audio interface provided, supporting standard audio data formats easy interfacing audio serial ports.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2001, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage, +6.5V Input Current ±10mA Digital Input Voltage -0.2V +5.5V Digital Output Voltage -0.2V (VDD 0.2V) Power Dissipation 300mW Operating Temperature Range -40°C 85°C Storage Temperature -55°C +125°C Lead Temperature (soldering, seconds) +260°C Package Temperature re-flow, seconds) +235°C
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT DIT4096 PACKAGE-LEAD TSSOP-28 PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE -40°C +85°C PACKAGE MARKING DIT4096IPW ORDERING NUMBER(2) DIT4096IPW DIT4096IPWR TRANSPORT MEDIA, QUANTITY Rails, Tape Reel, 2000
NOTE: most current specifications package information, refer site www.ti.com.
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ELECTRICAL CHARACTERISTICS
specifications +25°C unless otherwise noted. DIT4096IPW PARAMETER DIGITAL CHARACTERISTICS Applies digital except High-Level Input Voltage, Low-Level Input Voltage, High-Level Output Voltage, Low-Level Output Voltage, Input Leakage Current OUTPUT DRIVER CHARACTERISTICS Applies only High-Level Output Voltage, Low-Level Output Voltage, SWITCHING CHARACTERISTICS Master Clock Reset Master Clock (MCLK) Frequency Master Clock (MCLK) Duty Cycle Reset (RST) Active Pulse Width Serial Control Port Timing CCLK Frequency Stereo Mode Mono Mode Serial Control Data Setup Time, tSDS Serial Control Data Hold Time, tSDH Falling CCLK Rising, tCSCR CCLK Falling Rising, tCFCS CCLK Falling CDOUT Data Valid, tCFDO Rising CDOUT High Impedance, tCSZ Audio Serial Interface Timing SYNC Frequency Frame Rate) SYNC Clock Period tSYNCP SYNC High/Low Pulse Width, tSYNCHL SCLK Frequency SCLK Clock Period, tSCLKP SCLK High/Low Pulse Width, tSCLKHL SYNC Edge SCLK Edge, tSYSK Audio Data Setup Time, tADS Audio Data Hold Time, tADH Input Timing C/U/V Data Setup Time, tCUVS C/U/V Data Hold Time, tCUVH POWER-SUPPLY Operating Voltage Supply Current IDD, Quiescent IDD, Power-Down Mode IDD, Dynamic 96kHz operation) Power Dissipation Quiescent Power-Down Mode Dynamic(at 96kHz operation) TEMPERATURE RANGE Operating Range Storage Range CONDITIONS UNITS
-4mA +4mA
+0.8
-30mA +30mA
Sampling Frequency Sampling Frequency
97.6525 10.24 5.12 12.5
+4.5
+5.5
+125
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CONFIGURATION: Software Mode (MODE
View TSSOP-28
CONFIGURATION: Hardware Mode (MODE
View TSSOP-28
CDOUT CCLK CDIN MCLK DGND SCLK SYNC SDATA
DIT4096
MODE DGND
COPY/C CLK1 CLK0 MCLK DGND FMT0 FMT1 SCLK SYNC SDATA
DIT4096
MODE BLSM EMPH AUDIO MONO MDAT DGND
DESCRIPTIONS: Software Mode
NAME CDOUT CCLK CDIN MCLK DGND SCLK SYNC SDATA DGND MODE DESCRIPTION Connection Control Port Data Output, Tri-State Control Port Data Clock Input Control Port Serial Data Input Control Port Chip Select Input, Active Master Clock Input Digital Power Supply, Nominal Digital Ground AES-3 Encoded Data Input Connection Audio Serial Port Data Clock Audio Serial Port Frame SYNC Clock Audio Serial Port Data Input Connection Reset Input, Active Digital Ground Transmitter Line Driver Output Transmitter Line Driver Output Digital Power Supply, Nominal Connection Connection Open Drain Interrupt Output, Active LOW. Requires pull-up resistor VDD. Connection Conneciton Block Start Connection User Data Input Control Mode Input. MODE Software Mode operation.
DESCRIPTIONS: Hardware Mode
NAME COPY/C CLK1 CLK0 MCLK DGND FMT0 FMT1 SCLK SYNC SDATA DGND MDAT MONO AUDIO EMPH BLSM MODE DESCRIPTION Channel Status Data Mode Input Copy Protect Input Channel Status Serial Data Input Generation Status Input Master Clock Rate Selection Input Master Clock Rate Selection Input Master Clock Input Digital Power Supply, Nominal Digital Ground Audio Data Format Control Input Audio Data Format Control Input Audio Serial Port Data Clock Audio Serial Port Frame SYNC Clock Audio Serial Port Data Input Audio Serial Port Master/Slave Control Input Reset Input, Active Digital Ground Transmitter Line Driver Output Transmitter Line Driver Output Digital Power-Supply, Nominal Mono Mode Channel Data Selection Input Mono Mode Enable Input, Active HIGH Audio Data Valid Control Input, Active Pre-Emphasis Status Input, Active Block Start Mode Control Input Block Start Validity Data Input User Data Input Control Mode Input. MODE Hardware Mode Operation.
DIT4096
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GENERAL DESCRIPTION
DIT4096 complete digital audio transmitter, suitable both professional consumer audio applications. Sampling rates 96kHz supported. DIT4096 complies with requirements AES-3, IEC-60958, EIAJ CP1201 interface standards. Figures show block diagrams DIT4096 when used Software Hardware control modes. MODE input (pin determines control model used configure DIT4096 internal functions. Software mode, serial control port used write read on-chip control registers status buffers. Hardware mode, dedicated control pins provided configuration status inputs. DIT4096 includes audio serial port, which used interface standard digital audio sources, such
Analog-to-Digital (A/D) converters, digital signal processors, audio decoders. Support left-justified, right-justified, data formats provided. AES-3 encoder creates multiplexed stream, containing audio, status, user data. Figure multiplexed data format. data then Bi-Phase Mark encoded output differential line driver. line driver outputs connected transmission medium, cable fiber optics. case twisted pair coaxial cable, transformer commonly used couple driver outputs transmission line. This provides both isolation improved common mode rejection. optical transmission, (pin driver output connected optical transmitter module. Applications Information section this data sheet details regarding output driver circuit configurations.
SYNC SCLK SDATA Audio Serial Port Line Driver
AES-3 Encoder
Reset Logic
Serial Control Interface, Control Registers, Channel Status Data Buffers
Clock Generator
MCLK
Control Port
FIGURE Software Mode Block Diagram.
SYNC SCLK SDATA FMT0 FMT1
Audio Serial Port
AES-3 Encoder
Line Driver
MCLK Reset Logic Data Buffer Clock Generator CLK0 CLK1 COPY/C AUDIO EMPH BLSM MONO MDAT
FIGURE Hardware Mode Block Diagram.
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Start Channel Status Block
Frame191
Frame
Frame
Channel
Channel
Channel
Channel
Channel
Channel
Sub-Frame Bits: Preamble Data Audio Data
Validity Data User Data Channel Status Data Parity
FIGURE AES-3 Frame Format.
MASTER CLOCK
DIT4096 requires master clock operation. This clock must supplied MCLK input (pin maximum master clock frequency that supplied MCLK 25MHz. Table shows master clock rates common input sampling frequencies.
SAMPLING FREQUENCY (kHz) 22.05 44.1 88.2 MASTER CLOCK FREQUENCY (MHz) 5.6448 6.144 8.192 11.2896 12.288 22.5792 24.576 8.4672 9.216 12.288 16.9344 18.432 11.2896 12.288 16.384 22.5792 24.576
RESET POWER DOWN OPERATION
DIT4096 includes reset input, (pin 15), which used force reset sequence. When DIT4096 first powered user must assert low, start reset sequence. input must minimum nanoseconds. input then forced high enable normal operation. software mode, reset sequence will force internal registers their default settings. addition, reset sequence will force channel status bits Software mode. While input low, transmitter outputs, (pin (pin 18), forced ground. Upon setting high, outputs will remain until rising edge SYNC clock detected Once this occurs, outputs will become active driven output AES-3 encoder. Software mode, DIT4096 also includes software reset power down bits, located control register 02HEX. software reset bit, RST, software power-down bit, PDN, both active high.
TABLE Master Clock Frequencies Common Sampling Rates.
Software mode, master clock frequency selection programmed using CLK0 CLK1 bits Control Register 02HEX. Hardware mode, CLK0 (pin CLK1 (pin inputs used select master clock frequency. Table shows available MCLK frequency selections.
CONTROL BITS INPUT PINS MASTER CLOCK (MCLK) SELECTION CLK1 CLK0 Unused
AUDIO SERIAL PORT
audio serial port three-wire interface used connect DIT4096 audio source, such converter DSP. port supports sampling frequencies 96kHz. port signals include SDATA (pin 13), SYNC (pin 12), SCLK (pin 11). SDATA serial data input port. SCLK either input output, used clock serial data into port. SYNC either input output, provides frame synchroni-
TABLE Master Clock Rate Selection Software Hardware Modes.
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zation clock port. SYNC also used data latch clock channel status, user, validity data inputs Hardware mode, user data input Software mode.
SYNC SCLK FREQUENCIES
SYNC clock rate same sampling frequency, This holds true both Slave Master modes. DIT4096 supports SYNC frequencies 96kHz. SCLK frequency Slave mode must provide least clock cycle each data that input SDATA. maximum SCLK frequency 12.288MHz 96kHz. SCLK frequency Master mode DIT4096 itself. Software mode operation, SCLK rate programmed either using SCLKR Control Register 03HEX. Hardware mode, SCLK frequency fixed Master mode.
SLAVE MASTER MODE OPERATION
audio serial port supports both Slave Master mode operation. Slave mode, both SYNC SCLK configured inputs. audio source device must generate both SYNC SCLK clocks Slave mode. Master mode, both SYNC SCLK configured outputs. audio serial port generates SYNC SCLK clocks Master mode, deriving both from master clock (MCLK) input. Software mode, Master/Slave mode selection performed using Control Register 03HEX (defaults Slave mode). Hardware mode, input (pin used select audio serial port mode. This shown Table III.
CONTROL BITS INPUT MASTER/SLAVE MODE SELECTION Slave Mode, both SYNC SCLK inputs. Master Mode, both SYNC SCLK outputs.
AUDIO DATA FORMATS
DIT4096 supports standard audio data formats, including Philips I2S, left justified, right justified data. Software mode provides most flexible format selection, while Hardware mode supports limited subset Software mode formats. Linear audio data SDATA input typically presented Two's Complement, first format. Encoded non-audio data provided required encoding scheme use. Figure shows common data formats used audio serial port.
TABLE III. Master/Slave Mode Selection Software Hardware Mode.
Left Channel SYNC (ISYNC SYNC (ISYNC
Right Channel
SDATA
Right Justified Left Justified SCLK Delay
SDATA
SDATA SCLK (ISCLK SCLK (ISCLK
Left Justified SCLK Delay (I2S)
tSYNCHL SYNC tSYSK
tSYNCHL
SCLK tSYSKHL tSCLKHL tSCLKP SDATA tADS tADH
FIGURE Audio Data Formats Timing.
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CONTROL REGISTER 03HEX SETTINGS AUDIO DATA FORMATS Phillips Left Justifed Right Justified Justification Left Justified Left Justified Right Justified DELAY SCLK Delay SCLK Delay SCLK Delay SCLK Delay ISCLK Sampling Edge Rising Edge Rising Edge Rising Edge ISYNC Phase Inverted Non-Inverted Non-Inverted Name Function Name Function Name Function Name Function
TABLE Audio Data Format Selection Software Mode. Software mode, Control Register 03HEX used audio data format selection. Data word length 16-, 18-, 20-, 24-bits using WLEN0 WLEN1 bits. Several format parameters, including SCLK sampling edge, data delay from start frame, SYNC polarity programmed using this register. Table shows examples register settings three standard audio formats. SCLK sampling edges SYNC polarity differ from system implementation next. Always consult audio source device datasheet technical reference details regarding it's output data formatting. Hardware mode, FMT0 (pin FMT1 (pin inputs utilized select four audio data formats. Refer Table available format selections.
INPUT PINS FMT1 FMT0
falling edge SYNC when ISYNC high when sampled, then block start condition indicated. When configured output ISYNC will high every 192nd falling edge SYNC Stereo mode, every 384th falling edge SYNC Mono mode. will then following falling edge. ISYNC then transitions rising edge SYNC. Hardware mode operation similar Software mode operation, with exception that there only limited number data formats available audio serial port. left right justified formats, behaves would Software mode with ISYNC data format, behaves would Software mode with ISYNC
FORMAT SELECTIONS 24-Bit Left Justified 24-Bit 24-Bit Right-Justified 16-Bit Right Justified
CHANNEL STATUS DATA INPUT
Channel status data input determined control mode use. Software mode, channel status data buffer accessed through serial control port. Buffer operations described detail section this data sheet entitled "Channel Status Buffer Operation (Software Mode Only)". Hardware mode, channel status data input accomplished user selectable methods.
TABLE Audio Data Format Selection Hardware Mode.
AES-3 ENCODER OPERATION
AES-3 encoder performs multiplexing audio, channel status, user, validity data. also performs BiPhase Mark encoding multiplexed data stream. This section describes channel status, user, validity data input encoder function.
INPUT
Hardware mode, state input (pin determines function dedicated channel status inputs. When COPY (pin (pin AUDIO (pin EMPH (pin inputs used associated channel status data bits. COPY inputs used setup copy protection consumer operation, indicate that transmitter operating professional mode, without copy protection. AUDIO input utilized indicate whether data being transmitted audio data, non-audio data. EMPH input used indicate whether audio data been pre-emphasized using 50/15us standard. Table available options these dedicated channel status inputs. When channel status data input serial fashion input (pin Data clocked rising falling edges SYNC input (pin 12). channel status data bits written this mode, allowing greater flexibility than previous Hardware mode case with Figure input timing diagram.
BLOCK START INPUT/OUTPUT
block start used indicate start channel status data block, which starts with Frame AES-3 data stream. DIT4096, block start signal, (pin 25), either input output. Software mode, direction using BLSM control register 01HEX (defaults input). Hardware mode, direction BLSM input (pin 24). BLSM input. BLSM output. Software mode operation, block start signal synchronized audio serial port frame sync clock, SYNC (pin 12). When configured input pin, sampled rising edge SYNC when ISYNC control register 03HEX Otherwise, sampled
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INPUT COPY
FUNCTION Copy Status Generation Status COPY Status Consumer Mode, Consumer Mode, Consumer Mode, Professional Mode, COPY COPY COPY Copy Protection
AUDIO
Audio Data Status AUDIO Status Digital Linear PCM) Audio Data Non-Audio Encoded Audio Data
EMPH
Pre-Emphasis Status EMPH Status Pre-emphasis bits indicate 50/15µs Pre-emphasis been applied. Pre-emphasis bits indicate that Pre-emphasis been applied.
TABLE Channel Status Data Input Hardware Mode with
Block Start
Frame
Frame
SYNC(1)
(Input)
(Output) 192nd 384th Falling Edge(1) Data Data Data Data Data
tCUVS NOTE: Assumes ISYNC
tCUVH
FIGURE Data Timing.
USER VALIDITY DATA INPUT
user data bits AES-3 data stream allow convenient transfer user-defined application specific data another device containing AES-3 receiver. input (pin used both Software Hardware mode input user data serial fashion. Figure shows input timing diagram. Validity data used indicate that sample error free audio data, that sample defective suitable
further processing. Software mode, control register 01HEX utilized write validity data. Hardware mode, input (pin used input validity data serial fashion. Refer Figure input timing Hardware Mode. When this indicates that audio data valid suitable further processing. When then audio sample defective should used.
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LINE DRIVER OUTPUTS
DIT4096 includes balanced line driver. line driver outputs (pin (pin 18). Software mode, line driver input taken from either output onchip AES-3 encoder, from external AES-3 encoded source input (pin input source selected using BYPASS control register 01HEX (defaults on-chip AES-3 encoder). Hardware mode, line driver source always on-chip AES-3 encoder. outputs line driver will follow AES-3 encoded data source normal operation. During hardware software reset, when device power down mode, line driver outputs will forced ground. outputs also forced ground time Software mode setting TXOFF control register 01HEX.
CCLK data clock serial control interface. Data clocked CDIN rising edge CCLK, while data clocked CDOUT falling edge CCLK. Data clocked first both CDIN CDOUT.
WRITE OPERATION
Figure illustrates write operation control port. write register buffer address time, auto-increment capability built into control port perform block writes. register buffer data preceded 16-bit header, with first byte being used configure control port operation starting register buffer address. second byte header comprised "don't care" bits, which either without affecting port operation. first byte header contains control bits, STEP, followed 6-bit address. write operations, STEP determines address step size auto-increment operation. When STEP address incremented When STEP address incremented Incrementing useful when writing multiple control registers sequence, when writing both left right channel status data sequence. Incrementing useful when writing just channel status data sequence. third byte contains 8-bit data register buffer address pointed first byte header. write single address location, brought high after least significant third byte clocked into port. auto increment mode, kept write successive register buffer addresses.
CONTROL PORT OPERATION (SOFTWARE MODE ONLY)
Software mode operation, DIT4096 includes serial control port, which used write read control registers channel status data buffer. Port signals include (pin CDIN (pin CDOUT (pin CCLK (pin active chip select. This signal must driven order write read control registers channel status data buffer. CDIN serial data input, while CDOUT serves serial data output. CDOUT tri-state output, which high impedance state when performing Read operation, when
here write register buffer location Header CDIN Byte Byte
Keep enable auto-increment mode
Register Buffer Data Byte Byte Byte
CCLK
BYTE DEFINITION BYTE STEP
Register Buffer Address Auto-Increment Address Step Size: Increment Address Increment Address Read/Write Control: Read Operation Byte bits Don't Care. Bytes through 8-bit Register Buffer data.
FIGURE Write Operation Format.
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READ OPERATION
Figure illustration read operation control port. read register buffer address time, auto-increment capability built into control port perform block reads. 16-bit header first written port, with first byte being used configure control port operation starting register buffer address. second byte header comprised "don't care" bits, which either without affecting port operation. first byte header contains control bits, STEP, followed 6-bit address. read operations, STEP determines address step size auto-increment operation. When STEP address
incremented When STEP address incremented Incrementing useful when reading multiple control registers sequence, when reading both left right channel status data sequence. Incrementing useful reading just channel status data sequence. first output data byte occurs immediately after 16-bit header been written. This byte contains 8-bit data register buffer address pointed first byte header. read single address location, brought high after least significant first data byte clocked port. auto increment mode, kept read successive register buffer addresses.
here read register buffer location Header CDIN Byte Byte
Keep enable auto-increment mode
Ignore Until Next High-to-Low Transition Register Buffer Data
CDOUT
High Impedance
Byte
Byte
Byte
CCLK
BYTE DEFINITION BYTE STEP
Register Buffer Address Auto-Increment Address Step Size: Increment Address Increment Address Read/Write Control: Read Operation Byte bits Don't Care. Bytes through 8-bit Register Buffer data.
FIGURE Read Operation Format.
tCSCR CCLK
tSDS
tCFCS
tSDH
CDIN
CDOUT
tCFDO
tCSZ
FIGURE Serial Port Timing.
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CONTROL REGISTER DEFINITIONS (SOFTWARE MODE ONLY)
This section defines control registers used configure DIT4096, well status register used indicate interrupt source. BLSM Block Start Mode (Defaults When (pin configured input pin. When (pin configured output pin. Audio Data Valid (Defaults When valid Linear audio data indicated. When invalid audio data non-PCM data indicated. Register 00HEX: Reserved Factory
(MSB) (LSB)
When MONO MCSD MDAT used select source Audio data. When MONO MCSD MDAT used select source both Audio Channel Status data. MCSD Channel Status Data Selection (Defaults When Channel data used sub-frame, while Channel data used sub-frame. When same channel status data both sub-frames. Channel status data source selected using MDAT bit. TXOFF Transmitter Output Disable (Defaults When line driver outputs, TX(pin (pin enabled. When line driver outputs forced ground. Register 02HEX: Power-Down Clock Control Register
(MSB) CLK1 CLK0 (LSB)
Register 01HEX: Transmitter Control Register
(MSB) TXOFF MCSD MDAT MONO BYPAS MUTE (LSB) BLSM
Power-Down (Defaults When DIT4096 operates normally. When DIT4096 powered down, with line driver outputs forced ground.
MUTE
Transmitter Mute (Defaults When mute function disabled. When mute function enabled, with Channel audio data 0's. CLK[1:0]
MCLK Rate Selection These bits used select master clock frequency applied MCLK input (pin CLK1 CLK0 MCLK Rate Unused (default)
BYPASS
Transmitter Bypass AES-3 Data Source Output Driver (Defaults When AES-3 encoded data taken from output on-chip encoder. When (pin used source AES-3 encoded data.
MONO
Mono Mode Control (Defaults When transmitter Stereo mode. When transmitter Mono mode.
Software Reset (Defaults When DIT4096 operates normally. When DIT4096 reset.
Register 03HEX: Audio Serial Port Control Register
(MSB) ISCLK DELAY WLEN1 WLEN0 SCLKR (LSB) ISYNC
MDAT
Data Selection (Defaults Left Channel, Right Channel) When MONO MCSD MDAT ignored. When MONO MCSD MDAT used select source Channel Status data.
Master/Slave Mode (Defaults When audio serial port Slave operation. When audio serial port Master operation.
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SCLKR
Master Mode SCLK Frequency (Defaults When SCLK frequency When SCLK frequency
Buffer Transfer Interrupt Status Active High When User Access (UA) Transmitter Access (TA) buffer transfers enabled, interrupt unmasked, this will High when buffer transfer completed. This will also cause output (pin driven Low, indicating that interrupt occurred.
WLEN[1:0]
Audio Data Word Length These bits used audio data word length both Left Right channels. WLEN1 WLEN0 Length 24-Bits (default) 20-Bits 18-Bits 16-Bits
TSLIP
Transmitter Source Data Slip Interrupt Status Active High This will High when either Data Slip Block Start condition detected, TSLIP interrupt unmasked. This will also cause output (pin driven Low, indicating that interrupt occurred. function this selected using BSSL control register 05HEX (defaults Data Slip). MBTI MTSLIP bits used mask TSLIP interrupts. When masked, these interrupt sources disabled.
Audio Data Justification (Defaults When audio data Left Justified with respect SYNC edges. When audio data Right Justified with respect SYNC edges.
DELAY
Audio Data Delay from Start Frame (Defaults This applies primarily frame formats, which Left Justified audio data. When audio data starts with SCLK period immediately following SYNC edge which starts frame. This referred zero SCLK delay. When audio data starts with second SCLK period following SYNC edge which starts frame. This referred SCLK delay. This used primarily data format.
Register 05HEX: Interrupt Mask Register
(MSB) BSSL MTSLIP (LSB) MBTI
MBTI MTSLIP
Interrupt Mask. mask (Defaults TSLIP Interrupt Mask. mask TSLIP (Defaults TSLIP Interrupt Select (Defaults When Data Slip condition used trigger TSLIP interrupt. When Block Start condition used trigger TSLIP interrupt.
BSSL
ISCLK
SCLK Sampling Edge (Defaults When audio serial data SDATA (pin sampled rising edge SCLK. When audio serial data SDATA (pin sampled falling edge SCLK.
Register 06HEX: Interrupt Mode Register
(MSB) BTIM1 (LSB) BTIM0 TSLIPM1 TSLIPM0
ISYNC
SYNC Polarity (Defaults When Left channel data occurs when SYNC clock High. When Left channel data occurs when SYNC clock Low. both cases, Left channel data always precedes Right channel data audio frame. BTIM[1:0] Interrupt Mode These bits used select active state interrupt operation. BTIM1 BTIM0 TSLIPM1
TSLIP (LSB)
TSLIPM[1:0] TSLIP Interrupt Mode
TSLIPM0
Interrupt Operation Rising Edge Active (default) Falling Edge Active Level Active Reserved
Register 04HEX: Interrupt Status Register
(MSB)
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Buffer Transfer Disable (Defaults When User Access (UA) Transmitter Access (TA) Buffer transfers enabled. When User Access (UA) Transmitter Access (TA) Buffer transfers disabled.
AES-3 encoder internally accesses buffer obtain channel status data that multiplexed into AES-3 data stream. user accesses buffer through control port order update channel status data when needed. transfer data from buffer buffer managed internally DIT4096, enabled disabled user control register. channel status data buffers driven internal clock, which requires that master clock active MCLK input (pin proper operation. buffers also disabled when power-down mode activated.
Register 07HEX: Channel Status Buffer Control Register
(MSB) (LSB)
UPDATING CHANNEL DATASTATUS BUFFER
CHANNEL STATUS DATA BUFFER OPERATION (SOFTWARE MODE ONLY)
DIT4096 contains buffers channel status data. These referred transmitter access (TA) buffer, user access (UA) buffer. Each buffer bytes long, containing bytes each channels bytes channel correspond channel status block defined AES-3 IEC-60958 specifications. Channel data interleaved within buffers, shown Tables VIII.
Updating channel status data buffer involves disabling enabling buffer transfer using control register 07HEX. Figure shows proper flow updating buffer. normally which enables buffer transfer. order update channel status data, user must write buffer. avoid data transfer while buffer being updated, which disables buffer transfers. While user writes channel status data buffer control port. Once buffer update complete, reset buffer transfer will occur during frames through 191,
DISABLE BUFFER TRANSFER Control Register
UPDATE DATA Write Channel Status Data Buffer
ENABLE BUFFER TRANSFER Control Register
Buffer Transfer Interrupt (BTI) Masked?
Assume that Buffer Transfer completed that Channel Status data been updated.
output Low?
Read Register verify that
Host verified that Buffer Transfer Complete, which completes Channel Status Data update.
FIGURE Flowchart Updating Channel Status Buffer.
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ADDRESS (HEX)
Byte
MODE MODE reserved reserved reserved reserved
AUDIO AUDIO MODE MODE reserved reserved reserved reserved
EMPH EMPH MODE MODE reserved reserved reserved reserved reserved reserved
EMPH EMPH MODE MODE WLEN WLEN reserved reserved reserved reserved reserved reserved
EMPH EMPH WLEN WLEN reserved reserved reserved reserved reserved reserved
LOCK LOCK WLEN WLEN reserved reserved reserved reserved reserved reserved
reserved reserved reserved reserved reserved reserved reserved reserved
reserved reserved reserved reserved reserved reserved reserved reserved
Alphanumeric Channel Origin Data (7-Bit ASCII0) Channel Alphanumeric Channel Origin Data (7-Bit ASCII0) Channel Alphanumeric Channel Origin Data (7-Bit ASCII0) Channel Alphanumeric Channel Origin Data (7-Bit ASCII0) Channel Alphanumeric Channel Origin Data (7-Bit ASCII0) Channel Alphanumeric Channel Origin Data (7-Bit ASCII0) Channel Alphanumeric Channel Origin Data (7-Bit ASCII0) Channel Alphanumeric Channel Origin Data (7-Bit ASCII0) Channel Alphanumeric Channel Destination Data (7-Bit ASCII) Channel Alphanumeric Channel Destination Data (7-Bit ASCII) Channel Alphanumeric Channel Destination Data (7-Bit ASCII) Channel Alphanumeric Channel Destination Data (7-Bit ASCII) Channel Alphanumeric Channel Destination Data (7-Bit ASCII) Channel Alphanumeric Channel Destination Data (7-Bit ASCII) Channel Alphanumeric Channel Destination Data (7-Bit ASCII) Channel Alphanumeric Channel Destination Data (7-Bit ASCII) Channel Local Sample Address Code (32-Bit Binary) Channel Local Sample Address Code (32-Bit Binary) Channel Local Sample Address Code (32-Bit Binary) Channel Local Sample Address Code (32-Bit Binary) Channel Local Sample Address Code (32-Bit Binary) Channel Local Sample Address Code (32-Bit Binary) Channel Local Sample Address Code (32-Bit Binary) Channel Local Sample Address Code (32-Bit Binary) Channel Time Code (32-Bit Binary) Channel Time Code (32-Bit Binary) Channel Time Code (32-Bit Binary) Channel Time Code (32-Bit Binary) Channel Time Code (32-Bit Binary) Channel Time Code (32-Bit Binary) Channel Time Code (32-Bit Binary) Channel Time Code (32-Bit Binary) Channel reserved reserved reserved reserved reserved reserved reserved reserved Flags Flags Flags Flags Flags Flags Flags Flags
Check Character Channel Check Character Channel
TABLE VII. Channel Status Buffer Professional Mode (PRO
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ADDRESS (HEX)
Byte
CODE CODE SOURCE SOURCE reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
AUDIO AUDIO CODE CODE SOURCE SOURCE reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
COPY COPY CODE CODE SOURCE SOURCE reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
EMPH EMPH CODE CODE SOURCE SOURCE reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
EMPH EMPH CODE CODE reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
EMPH EMPH CODE CODE reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
MODE MODE CODE CODE reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
MODE MODE reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
TABLE VIII. Channel Status Buffer Consumer Mode (PRO whichever first frame occur after reset Once buffer transfer completed, buffer transfer interrupt (BTI) will occur, long unmasked. transmitter will ignore attempt access buffer during buffer transfer. addition, stop buffer transfer that maybe progress, desired.
INTERRUPT SOURCES (SOFTWARE MODE ONLY)
DIT4096 programmed generate interrupts three predefined conditions. interrupt output, (pin 22), when valid interrupt occurs. interrupt status register, 04HEX, then read determine source interrupt. Status register bits output remain active until status register read. Once read, status bits cleared pulled high external pull-up resistor. Interrupts masked using control register 05HEX. When masked, interrupt mechanism associated with particular status disabled.
CHANNEL STATUS BUFFER
channel status buffer organized accordance with AES-3 IEC-60958 standards. Table memory user access (UA) channel status data buffer Professional mode. Table VIII memory user access (UA) channel status data buffer Consumer mode.
DIT4096
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SBOS225
CHANNEL STATUS BUFFER TRANSFER INTERRUPT
This interrupt occurs when channel status buffer transfer been completed. buffer transfer process described detail previous section this data sheet. This interrupt used host trigger event occur after channel status buffer update. status register 04HEX used indicate occurrence buffer transfer. bit, like other status bits, active high remains until status register read.
block start condition occurs when block start signal generated either internally DIT4096, when external block start received input (pin 25).
APPLICATIONS INFORMATION
This section provides practical information pertinent designing DIT4096 into target application. Circuit schematics provided needed.
DATA SLIP BLOCK START INTERRUPTS
Unlike interrupt, which only function, TSLIP interrupt modes. This accomplished using BSSL control register 05HEX. When BSSL TSLIP interrupt indicate data slip condition. When BSSL TSLIP interrupt indicate block start condition. TSLIP bit, like other status bits, active high remains until status register read. data slip condition occur cases where master clock, MCLK (pin asynchronous audio data source. When BSSL TSLIP will every time data sample dropped repeated.
TYPICAL APPLICATION DIAGRAMS
Figures illustrate typical application schematics DIT4096 when used Software Hardware modes. Figure shows typical Software mode application, where microprocessor interface used communicate with DIT4096 serial control port. Figure shows typical Hardware mode configuration, where control pins either hardwired driven digital logic stand-alone application. recommended component values power supply bypass capacitors shown Figures These capacitors should located close DIT4096 power supply pins physically possible.
From AES-3 Encoded Data Source (Optional) Digital Audio Source (A/D, DSP)
DIT4096 SCLK SYNC SDATA (See Figs. 12-14) Output Circuit Cable Fiber Optics
Audio Master Clock
CCLK CDIN CDOUT MCLK MODE DGND DGND 0.1µF
FIGURE Typical Circuit Configuration, Software Mode.
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DIT4096 Digital Audio Source (A/D, DSP) SCLK SYNC SDATA FMT0 FMT1 COPY/C AUDIO EMPH BLSM MONO MDAT MCLK CLK0 CLK1 MODE
Output Circuit Cable Fiber Optics
(See Figs. 12-14)
Hardwired Control Dedicated Logic Host Controlled
DGND DGND 0.1µF
Audio Master Clock Generator
FIGURE Typical Circuit Configuration, Hardware Mode. line driver outputs connected cable fiber optic transmission media target application. Figures show typical connections driving either balanced twisted pair unbalanced coaxial cable. Either these connections will support rates 96kHz. Figure illustrates connection optical transmitter module, used primarily consumer applications, such players. optical transmitter data rate limited 6Mb/s, will support 96kHz data rates. optical interface typically reserved lower rate transmission, such 44.1kHz 48kHz.
DIT4096
T1(1)
Toshiba TOTX173 Optical Transmitter 8.2k TOSLINK Interconnect
DIT4096
NOTE: Shielded Digital Audio Transformer Scientific conversion SC937-02 equivilent
FIGURE Recommended Transmitter Output Circuit Balanced, Twested Pair Transmission.
DIT4096
90.9
T1(1)
FIGURE Recommended Transmitter Output Circuit TOSLINK Optical Transmission Over Plastic Fiber (APF).
DUAL WIRE OPERATION USING MONO MODE
order support stereo 96kHz transmission legacy systems, which utilize AES-3 receivers that operate maximum 48kHz, necessary DIT4096 transmitters what referred Dual Wire configuration. Each transmitter carries data only channel this configuration.
NOTE: Shielded Digital Audio Transformer Scientific conversion SC937-02 equivilent
FIGURE Recommended transmitter Output Circuit Unbalanced, Coaxial Calble Transmission.
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Dual Wire operation requires that each DIT4096 operate Mono mode, which supported both Software Hardware control modes. Mono mode, DIT4096 transmits consecutive samples single channel both Channel Channel sub-frames, effectively doubling sampling rate. audio serial port channel used sampling audio channel status data selectable both Software Hardware control modes. Software mode, MONO, MDAT, MCSD bits control register 01HEX used select mono mode, well
INPUT MONO FUNCTION Stereo/Mono Mode Selection MONO MDAT Status Stereo Mode Mono Mode
source channel audio channel status data. Refer register definition details regarding setting these bits. Hardware mode, MONO (pin MDAT (pin inputs used enable mono mode, well selecting source channel audio channel status data. Table shows available options MONO MDAT selection. Figure illustrates simple Hardware mode configuration implementing Dual Channel operation using DIT4096 transmitters.
Mono Mode Audio Channel Status Data Selection MDAT Status Source Left Channel Audio data, Channel data Source Right Channel Audio data, Channel data
TABLE Mono Mode Configuration Settings Hardware Mode Operation.
PCM1804 DATA LRCK SCLK SYNC DIT4096 SDATA MONO MDAT Output Circuit Right Channel Output
(See Figs. 12-14)
SDATA SYNC DIT4096 SCLK MONO MDAT Output Circuit Left Channel Output
Master Clock Generator
Devices
(See Figs. 12-14)
NOTE: simplify drawing, pins shown here.
FIGURE Hardware Mode Example Dual Channel Transmitter Operation.
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PACKAGE DRAWING
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
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Copyright 2001, Texas Instruments Incorporated

DIT40 SBOS225 DECEMBER 2001 96kHz DIGITAL AUDIO TRANSMITTER

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