PRADEEP BARDIA (903)-868-5110 msg-id PKBA APPLICATIONS ADAM

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PRADEEP BARDIA (903)-868-5110 msg-id PKBA APPLICATIONS ADAM

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JTAG Boundary Scan Logic CONTACTS MARKETING
PRADEEP BARDIA (903)-868-5110 msg-id PKBA
APPLICATIONS
ADAM (903)-868-5761 msg-id ALEY JANDHYALA (903)-868-5818 msg-id SRIJ
Foil-1
Semiconductor Group Advanced System Logic
JTAG Boundary Scan Logic Devices TERMS JTAG Joint Test Action Group SCOPE System Controllability
Observability Partitioning Environment
Boundary Scan Logic
Foil-2
Semiconductor Group Advanced System Logic
Boundary Scan Agenda
What JTAG Boundary Scan Idea Typical Applications Interconnect Testing Logic Cluster Testing Memory Testing System-Level Test Design Considerations TI's JTAG Boundary Scan Devices
minutes) minutes) minutes)
Foil-3
minutes) minutes) minutes)
Semiconductor Group Advanced System Logic
Standard Approach Test
JTAG IEEE 1149.1
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Developed over vendors/ATE end-equipment manufacturers '80's Sanctioned IEEE 1990 Primary focus board-level manufacturing defects Solution: Place test points within silicon Ensure compatibility between IEEE 1149.1 compliant devices tools
Semiconductor Group Advanced System Logic
JTAG Supports Board Test More
Developed board interconnect test Tester "speaks" board JTAG port Execute variety functional tests Benefits product phases Design verification/debug Hardware/software integration Manufacturing Field support Tests reused Chip, board, system
Semiconductor Group Advanced System Logic
JTAG PORT
Foil-5
Increasing Problem Board Test
incredible shrinking board results loss test access
Yesterday
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Today
Tomorrow
Semiconductor Group Advanced System Logic
Increasing Problem Board Test
Increasing integration chip level complicates controllability
Yesterday
Foil-7
Today
Semiconductor Group Advanced System Logic
What Does Offer IEEE 1149.1 (JTAG) Silicon Solutions?
commercially released devices
IEEE 1149.1 (JTAG) Boundary-Scan Logic Devices Octal (8-bit) Widebus(18/20-bit) Scan-Support Functions
ABT/ ABTH* (5V) LVTH* (3.3V)
LVT8980 (eTBC)
Hold option
Foil-8
Semiconductor Group Advanced System Logic
Conventional Methods Board Test
Functional Test (`Edge-Connector' Test)
Based board function, rather than structure Test generation primarily manual Test access limited primary only
Foil-9
Semiconductor Group Advanced System Logic
Boundary Scan Idea
CORE CORE
Scan provides means arbitrarily observe test results source test stimulus Scan method requires minimal chip/board resources (pins/nets)
Foil-10
Semiconductor Group Advanced System Logic
Boundary Scan Method Board Test
CORE CORE
CORE
CORE
Based board structure; limited chip function/ complexity Test access limited board physical factors
CORE CORE
Foil-11
Semiconductor Group Advanced System Logic
Benefits Boundary Scan
Controllability observability physical access Reduced number test points needed Reduced number pins needed `Bed-of-Nails' testers Eliminates need models JTAG parts Allows quick identification isolation defects Industry standard ensures inter-operability between vendors
Semiconductor Group Advanced System Logic
Foil-12
Can't Afford Test
Cost will increase factor fault finding moves from level complexity next. result:
Reduced Profit Margins Delayed Product Introduction Dissatisfied Customers
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Device level Board level System level Field level
unit cost units cost units cost 1,000 units cost
Semiconductor Group Advanced System Logic
Boundary Scan Success Stories
"We've (AT&T) reduced number test
points some boards from down four shortened test-debug time some products from weeks days."
Hewlett Packard printers reduced drawing
board production time from four half years years.
Test program development time Intel '386
Intel '486 with JTAG: Intel '386 Intel '486 Seven weeks hours (two hours vendor supplied BSDL) programmable logic devices with boundary scan were able cost tester with ATPG ($25K) instead standard system ($750K) that would have been used without boundary scan.
Controller design company using
Computer Design, January 1994, "Testing Dilemmas Corporate Alliances Fuel Boundary Scan's Acceptance" Test Measurement World, October 1992, "Concurrent Engineering Common Sense" Computer Design, November 1992, "Design Test Engineers Alter Rules Facilitate Test" EDN, December 1992, 'Accounting' Boundary Scan Test"
Foil-14
Semiconductor Group Advanced System Logic
Equipment Designing with JTAG Boundary-Scan
Military Networking
Telecom
High Fault Tolerant' Computers Imaging Systems Medical Conferencing Consumer Copiers
Mid-Range `Server' Computers
Avionics
Foil-15
Semiconductor Group Advanced System Logic
Contact More Information JTAG Devices
Texas Instruments Marketing P.O. Sherman, 75090
Product Info. Center (972) 644-5580
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Semiconductor Group Advanced System Logic

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