Author: Peter Forstner Date: 03.02.93 Rev.: This report begins wi
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210E Digital Monitor SN74ACT8994
Author: Peter Forstner Date: 03.02.93 Rev.:
This report begins with description hardware realization DIGITAL MONITOR SN74ACT8994. nine registers used programming, which compatible with IEEE 1149.1, then described tabular form; these followed eight execution protocols, which explained with both pulse diagrams also form flow diagrams. Lastly, reader introduced programming procedure making practical examples, which also demonstrate typical applications.
Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safe-guards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1995, Texas Instruments Incorporated
210E
Inhaltsverzeichnis
Contents
Introduction. Hardware. Connections Cascading Architecture Signals Programming. Registers 3.1.1 INSTRUCTION REGISTER 3.1.1.1 Instructions 3.1.1.2 INSTRUCTION REGISTER STATUS WORD 3.1.2 CONTROL REGISTER 3.1.3 EVENT QUALIFICATION REGISTER 3.1.4 EVENT QUALIFICATION REGISTER 3.1.5 REGISTER 3.1.6 HEADER REGISTER 3.1.7 TEST CELL REGISTER 3.1.8 BYPASS REGISTER 3.1.9 BOUNDARY SCAN REGISTER Protocols 3.2.1 Protocol 3.2.2 Protocol 3.2.3 Protocol 3.2.4 Protocol 3.2.5 Protocol 3.2.6 Protocol 3.2.7 Protocol 3.2.8 Protocol Typical Program Sequence Examples. Basic Functions 4.1.1 Writing into 4.1.2 Reading 4.1.3 Writing into with 4.1.4 Reading with 4.1.5 Filling 4.1.6 Writing into EQR2 4.1.7 Reading EQR2 4.1.8 Writing into EQR2 with 4.1.9 Reading EQR2 with 4.1.10 Read Status during RUNN 4.1.11 Read Address Counter
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4.1.12 Address Counter Protocols 4.2.1 Protocol 4.2.2 Protocol 4.2.3 Protocol 4.2.4 Protocol 4.2.5 Protocol 4.2.6 Protocol 4.2.7 Protocol 4.2.8 Protocol 4.3.1 4.3.2 Real-Time 4.3.3 with three cascaded DBMs Tips Tricks 4.4.1 Self test 4.4.2 Three Clock Inputs 4.4.3 Post Triggering 4.4.4 Vertical Cascading Summary.
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Introduction
Introduction
ever-increasing integration density semiconductor components, packaging techniques (SMD) which allow assembly components both sides circuit boards, have tremendous increases complexity electronic systems. However, higher component density circuit boards aggravates problems testability, since number test vectors needed increases more than proportionally with complexity. making nail adapters, possible segment system tested, reduce dramatically number test vectors, although high component density double-sided boards reduces number possible contact areas nail adapters. escalating problems testability therefore only solved with completely test concept. Back 1985, leading electronic manufacturers founded JOINT TEST ACTION GROUP (JTAG), order develop cost-effective test concept. result this IEEE 1149.1 Standard. This Standard requires special test-circuits inputs outputs selected semiconductor components, together with logic control such test-circuits. 4-pole serial test combines test-circuits into complete test-group, which controlled test bus; this way, with only lines complete system segmented tested. Application Report from TEXAS INSTRUMENTS describes these test methods detail, presents IEEE 1149.1-compatible SCOPEbus drivers from TEXAS INSTRUMENTS. Application Report 203, control IEEE 1149.1 test explained with help TEST-BUSCONTROLLER SN74ACT8990. This Application Report assumes understanding test-methods according IEEE 1149.1. further very interesting component JTAG family from TEXAS INSTRUMENTS DIGITAL-BUS-MONITOR (DBM) SN74ACT8994. This features logic analyzer chip which controlled entirely IEEE 1149.1 test bus. With help integrated static memory, store 1024 words data with width bits. addition, data compression provided, making Parallel Signature Analysis (PSA). triggering data storage takes place with predetermined succession events bus. this case, perform data storage either synchronization with clock pulse JTAG bus, synchronized external clock pulse, example system clock tested board. extension word width realized without difficulty cascading several components. spite these various options, needs very little area circuit board, thanks 28-Pin PLCC package.
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Hardware
Hardware
SN74ACT8994 DIGITAL MONITOR developed order either observe store data, perform both these functions, with having width bits. this purpose, connected parallel with under observation Figure 2-1). data entered into internal memory, then read JTAG (IEEE 1149.1). desired, will also generate Parallel Signature Analysis from input data from content memory. this way, designer control signature large number samples, and, should error occur, then examine 1024 words data.
Figure 2-1: Connection Data Microcomputer operate either ON-LINE OFF-LINE mode. ON-LINE mode, synchronized more external clock signals. three external clock signals (CLK1, CLK2, CLK3) test clock such case connected, making PROGRAMMABLE CLOCK INTERFACE (PCI). This permits real time measurements, while using system clock signal device under test. When OFF-LINE mode, operated synchronously with test clock signal TCK, accordance with IEEE Standard 1149.1. this case, input data from TEST ACCESS PORT (TAP) processed state RUN-TEST/IDLE (see Figure 2-2). store single words data (SAMPLE), succession 1024 words (TRACE). Parallel Signature Analysis bits possible, either separately parallel SAMPLE TRACE. user selects eight protocols, order achieve desired succession operations SAMPLE, TRACE PSA. Each protocol individual order events, n-time occurrence expected data word data inputs D15.D00, which must awaited before beginning completing processing data. result option masking individual bits, each operation also limited
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Hardware fewer than bits. protocols permit change masks each event while they being implemented.
Figure 2-2: State Diagram TEST ACCESS PORT (TAP) 1024x16 memory read written either word-by-word, using (DIRECT MEMORY ACCESS). latter increases access speed very significantly, whereas word-by-word access offers high degree flexibility. contains nine IEEE 1149.1-compatible shift registers, which connected JTAG scanning path between terminations (TEST DATA INPUT) (TEST DATA OUTPUT). These registers permit control complete component. Commands data loaded, status, memory content results read.
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Hardware
Connections
Despite wide variety functions which offers, needs little area circuit board result being packaged compact 28-pin PLCC (PLASTIC LEADLESS CHIP CARRIER). pinning shown Figure 2-3.
Figure 2-3: Pinning SN74ACT8994 inputs outputs provide following signals: VCC: Supply Voltage GND: Ground D15.D00: signals these data inputs stored, used PSA. Each individually excluded from storage means masking. CLK3.CLK1: clock inputs synchronizing operations. EQO: Event output EVENT QUALIFYING OUTPUT EQI: Event input EVENT QUALIFYING INPUT PIO: Bi-directional signal cascading POLYNOMINAL INPUT OUTPUT) TMS: IEEE 1149.1 signal TEST MODE SELECT TCK: IEEE 1149.1 clock signal TEST CLOCK TDI: IEEE 1149.1 data input TEST DATA INPUT TDO: IEEE 1149.1 data output TEST DATA OUTPUT
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Hardware
Cascading
easily cascaded order increase word length. Figure shows connections necessary cascade SAMPLE TRACE functions; similarly, cascading function shown Figure 2-5. both cases there limit word length.
Figure 2-4: Cascading Increase Analyzer Word Length Bits
Figure 2-5: Cascading Increase Word Length Bits When cascading increase word length, attention must paid both correct programming device (MOST SIGNIFICANT DEVICE, MIDDLE DEVICE, LEAST SIGNIFICANT DEVICE), also sequence JTAG scanning path, since latter also used implement PSA.
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Hardware block VOTE Figure most cases simple gate. This gate only causes triggering event which being sought (e.g. whether expected data input data identical) occurs DBMs simultaneously. using gate, example, triggering could initiated only DBMs. Further options occur user, implement them according individual requirements.
Architecture
Figure shows internal construction DIGITAL-BUS-MONITOR, consisting eight functional blocks: (PROGRAMMABLE CLOCK INTERFACE) (EVENT QUALIFICATION MODULE) (1024 static memory) TEST CELL REGISTER CONTROL BYPASS INSTRUCTION REGISTER BOUNDARY SCAN REGISTER (TDO Multiplexer)
provides user with number various options connecting clock signals CLK1, CLK2, CLK3 TCK, order generate clock signal OCLK (ON-LINE CLOCK) Table 2-1. OCLK internal signal, rising edge which data comparison, data registration generation take place. EVENT QUALIFICATION MODULE (EQM) responsible event control DBM. Events have considerable influence test program, since they determine beginning test, sometimes also end. this case three events from control test program: EVENT with identical data appearing inputs D15.D00, input shows event Table 2-2); EVENT COUNTER (ECNT) reached minimum count value LOOP COUNTER (LCNT) reached minimum count value
Both event recognition (Table 2-2) backwards counter EVENT COUNTER LOOP COUNTER part EQM. Data appearing input pins D15.D00 stored internal RAM, extracted (Parallel Signature Analysis). performed TEST CELL REGISTER (Figure 2-7); this shift register having feedback, which turn again into shift chain, together with bits input data, EXOR gates. user decide which points feedback signal should into chain.
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Hardware JTAG standard IEEE 1149.1 requires blocks INSTRUCTION REGISTER, CONTROL BYPASS, BOUNDARY SCAN REGISTER MUX. They control complete JTAG logic, allow implementation required basic functions circuit which compatible with IEEE 1149.1: namely, EXTEST, BYPASS SAMPLE.
Figure 2-6: Block Diagram
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Hardware
POLSEL SELD SELC SELB SELA Clock Signal RUNN TCK* CLK1* CLK2* CLK3* CLK1 CLK2 CLK1 CLK2 CLK1 CLK2 CLK1 CLK2 CLK1 CLK3 CLK1 CLK3 CLK1 CLK2 CLK3 CLK1 CLK2 CLK3 CLK1 CLK3 CLK1 CLK3 CLK1 CLK2 CLK3 CLK1 CLK2 CLK3 CLK1 CLK2 CLK3 CLK1 CLK2 CLK1 CLK2 CLK1 CLK2 CLK1 CLK2 CLK1 CLK2 CLK3 CLK1 CLK2 CLK3 CLK1 CLK2+ CLK3 CLK1 CLK2+ CLK3 CLK1 CLK2 CLK3 CLK1 CLK2 CLK3 CLK1 CLK2+ CLK3 CLK1 CLK2+ CLK3
available both RUNN RUNT
Table 2-1: Interconnection Options Generating ON-LINE CLOCK (OCLK).
EQISELC EQISELB EQISELA EVENT Input Signal CTERM DCTERM DEQI (EQI synchronized with DEQI
Table 2-2: Signals which extracted Events.
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Hardware
Figure 2-7: Circuit 210E
Hardware
Signals
functions controlled certain internal external signals. user should aware function following signals: OCLK: ON-LINE-CLOCK clock signal generated (PROGRAMMABLE CLOCK INTERFACE). rising edge this signal, data compared, both data storage generation take place. END-OF-TEST shows test protocol. active during implementation protocol. active when data being transferred from inputs D15.D00 into internal RAM, being used PSA.
EOT: RUN: TGATE:
CTERM: This signal active when data bits inputs identical with expected data bits which were kept EVENT QUALIFICATION REGISTER DCTERM: CTERM signal, synchronized with rising edge OCLK. EQO: EQI: Output signal EVENT QUALIFICATION OUT). Input signal EVENT QUALIFICATION IN).
Figure shows wave forms typical test sequence, showing signals mentioned above. this case, waits event occur three times before subsequently storing words data. When after this event occurs twice, transmits further words data RAM, before test protocol process completed.
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Hardware
Figure 2-8: Signals 210E
Programming
Programming
Registers
Nine serial shift registers contain data which needed control various tests. These registers consist INSTRUCTION REGISTER, data registers. Figure Table give reader overview registers DBM. significance individual bits will explained later detail. should mentioned here that (MOST SIGNIFICANT BIT) always closest input, whereas closest output.
Figure 3-9: Registers Scan Internal Symbol Length Register (Bits) Size
CTRL EQR1 EQR2 Bits Bits Bits Bits
Register Name
INSTRUCTION CONTROL EVENT QUALIFICATION EVENT QUALIFICATION
Function
Loads commands, supplies status Various control signals; feedback masks Control signals event control LOOP COUNTER. EVENT COUNTER, expected data with appropriate masks. storing data words inputs. samples controlling start. Register pins DBM, without JTAG pins. Removes from scan path
HEADER TEST CELL BOUNDARY SCAN BYPASS
RAMR
1024 Bits Bits Bits Bits
Table
Overview Registers
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Programming
3.1.1 INSTRUCTION REGISTER
3.1.1.1 Instructions
Binary OPCODE
00000000 10000001 10000010 10000011 10001000 00001001 10001110 00010001 0110000 11100001 11100010 01100011 11100100 01100101 01100110 11100111 11101000 01101001 01101010 11101011 01101100 11101101 Others
OPCODE
Command
EXTEST BYPASS SAMPLE PRELOAD BYPASS RUNN RUNT SCANCN SCANEQN READFILE WRITEFILE READRAM WRITERAM DMAFOUT DMAFIN DMAROUT DMARIN SCANTCR READTCR INITRAM TOGRAM PSARAM SCANHDR BYPASS
Chosen Data Register
BOUNDARY SCAN BYPASS BOUNDARY SCAN BYPASS BYPASS BYPASS CONTROL EVENT QUALIFICATION EVENT QUALIFICATION EVENT QUALIFICATION EVENT QUALIFICATION EVENT QUALIFICATION TEST CELL TEST CELL BYPASS BYPASS BYPASS HEADER BYPASS
Table 3-4: Commands SN74ACT8994. commands will described briefly. EXTEST: BOUNDARY SCAN REGISTER selected during DR-SCAN, signals input pins read, pattern which have been shifted appear outputs. SAMPLE PRELOAD: Almost same command EXTEST, with however difference that remains normal operating mode, that output pins controlled BOUNDARY SCAN REGISTER. BYPASS: BYPASS REGISTER selected during DR-SCAN; other registers remain unchanged. RUNN: protocol selected with bits OP3.OP0 CONTROL REGISTER implemented. processing command takes place synchronously with clock signal selected bits SELD.SELA CONTROL REGISTER. RUNN command ends either when protocol reaches state END-OF-TEST, when different command from RUNN shifted into INSTRUCTION REGISTER.
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Programming RUNT: protocol selected CONTROL REGISTER with bits OP3.OP0 implemented according IEEE 1149.1, state RUNTEST/IDLE. bits SELD.SELA CONTROL REGISTER must chosen clock signal TCK, that actions performed RUNTEST/IDLE state. SCANCN: CONTROL REGISTER selected during DR-SCAN, read written into. SCANEQN: EVENT QUALIFICATION REGISTER (EQR1) selected during DR-SCAN, read written into. READFILE: EVENT QUALIFICATION REGISTER (EQR2) configured register scan path, extension addresses. this possible address read desired data words. WRITEFILE: EVENT QUALIFICATION REGISTER (EQR2) configured register scan path, extension addresses. this possible address write desired data words. READRAM: 1024 data memory (RAM) configured register scan path, extension address. this possible address read desired data words. WRITERAM: 1024 data memory (RAM) configured register scan path with extension address. this way, possible address write desired data words. DMAFOUT: EVENT QUALIFICATION REGISTER (EQR2) configured register scan path. this way, possible read data words using techniques. DMAFIN: EVENT QUALIFICATION REGISTER (EQR2) configured register scan path. this way, possible write data words using techniques. DMAROUT: 1024 data memory (RAM) configured register scan path. this way, possible read data words using techniques. DMARIN: 1024 data memory (RAM) configured register scan path. this way, possible write data words using techniques. SCANTCR: TEST CELL REGISTER selected during DR-SCAN, read written into. During CAPTURE-DR state, this register loaded with signals inputs D15.D00. This register used (Parallel Signature Analysis) operations. READTCR: TEST CELL REGISTER selected during DR-SCAN, read written into. During CAPTURE-DR state, this register remains unhighlighted. This register used (Parallel Signature Analysis) operations.
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Programming INITRAM: During RUN-TEST/IDLE state, contents address copied following addresses, beginning with address this way, 1024 data memory rapidly filled with constant value. TOGRAM: During RUN-TEST/IDLE state, contents address copied uneven addresses (beginning with address copied inverted even addresses. this way, 1024 data memory rapidly filled with Checkerboard Pattern. PSARAM: During RUN-TEST/IDLE state, TEST CELL REGISTER from pre-selected part 1024 data memory. SCANHDR: HEADER REGISTER selected during DR-SCAN, read written into. This register needed possible techniques.
3.1.1.2 INSTRUCTION REGISTER STATUS WORD
Signal IRERR
INSTRUCTION REGISTER STATUS WORD
command loaded INSTRUCTION REGISTER error. This invalid command causes implementation command BYPASS. command loaded INSTRUCTION REGISTER error-free address counter OVERFLOW. address counter incremented maximum value 3FFh value 000h. this time protocol being implemented. protocol process. protocol execution begun, process. protocol execution finished TEST).
Table 3-5: Bits INSTRUCTION REGISTER STATUS WORD command shifted into means IR-SCAN, then INSTRUCTION REGISTER STATUS WORD will received output. Important information about internal state deduced from this status word. This particularly necessary during implementation RUNN command; noted that repeated shifting RUNN command does influence execution RUNN command which process.
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Programming
3.1.2 CONTROL REGISTER
Signal
CONTROL REGISTER
RUNN OPCODE FUNCTION Sample Sample Sample Sample PSA, cascaded PSA, cascaded PSA, cascaded PSA, cascaded Trace Trace Trace Trace TRACE PSA, cascaded TRACE PSA, cascaded TRACE PSA, cascaded TRACE PSA, cascaded inputs used directly input data register memory. inputs used register memory only after they have been loaded intermediate register. address counter reaches value 3FFh while writing, then begins again from 000h. address counter reaches value 3FFh while writing, then writing process will stopped. shows parity error with instructions (IRERR). parity error with instructions (IRERR) will shown during state Pause-IR. comparison inputs with expected data takes place directly. input data will used comparison register only after they have been loaded into intermediate register. clock signal selected with SELD.SELA used directly OCLK. clock signal selected with SELD.SELA used inverted OCLK. SELD SELC SELB SELA Clock Signal with RUNN CLK1 CLK2 CLK3 CLK1 CLK2 CLK1 CLK2 CLK1 CLK2 CLK1 CLK2 CLK1 CLK2 CLK3 CLK1 CLK2 CLK3 CLK1 CLK2 CLK3 CLK1 CLK2 CLK3 CLK1 CLK2 CLK3 CLK1 CLK2 CLK3 CLK1 CLK2 CLK3 CLK1 CLK2 CLK3 available both RUNN RUNT. making POLSEL bit, clock signal selected here also used inverted OCLK.
SELDP
HAL
PARENA
CMPSEL
POLSEL SELD SELC SELB SELA
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Programming
Signal PTAP15 PTAP14 PTAP13 PTAP12 PTAP11 PTAP10 PTAP9 PTAP8 PTAP7 PTAP6 PTAP5 PTAP4 PTAP3 PTAP2 PTAP1 PTAP0 DATMSK15 DATMSK14 DATMSK13 DATMSK12 DATMSK11 DATMSK10 DATMSK9 DATMSK8 DATMSK7 DATMSK6 DATMSK5 DATMSK4 DATMSK3 DATMSK2 DATMSK1 DATMSK0
CONTROL REGISTER (Continued)
mask programming feedback with PSA: feedback used with this bit. Feedback used this bit.
mask order suppress bits with signature analysis. taken account with signature analysis. used with signature analysis.
Table 3-6: Bits CONTROL REGISTER Binary OPCODE
10001110
OPCODE
Command
SCANCN
Selected Data Register
CONTROL
Table 3-7: Command CONTROL REGISTER
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Programming
3.1.3 EVENT QUALIFICATION REGISTER
Signal CMD2 CMD1 CMD0
EVENT QUALIFICATION REGISTER
CMD2 CMD1 CMD0 Choice protocol Protocol Protocol Protocol Protocol Protocol Protocol Protocol Protocol (End-Of-Test) signal reset synchronously i.e. when execution protocol begins. Reset End-Of-Test) signal takes place asynchronously i.e. when internal signal becomes inactive. address starts beginning protocol with value 000h. address reset beginning protocol. EQOSELD EQOSELC EQOSELB EQOSELA Output Signal TGATE TGATE CTERM CTERM DCTERM DCTERM EQISELC EQISELB EQISELA EVENT Input Signal CTERM DCTERM Input Input DEQI (EQI synchronized with DEQI loop counter LCNT active. loop counter LCNT switche never decrements. event counter ECNT active. event counter ECNT switched never decrements. data loaded before each protocol change. current data remain active after protocol change. signal CTERM selected with EQOSELD.EQOSELA becomes active soon protocol implementation begins becomes active soon expected data found.
SYNEOT
RACDIS
EQOSELD EQOSELC EQOSELB EQOSELA
EQISELC EQISELB EQISELA
LCNTDIS ECNTDIS POPDIS ENACMP
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Programming
Signal LCNT15 LCNT14 LCNT13 LCNT12 LCNT11 LCNT10 LCNT09 LCNT08 LCNT07 LCNT06 LCNT05 LCNT04 LCNT03 LCNT02 LCNT01 LCNT00
EVENT QUALIFICATION REGISTER (Continued)
loop counter
Table 3-8: Bits EVENT QUALIFICATION REGISTER Binary OPCODE
00010001
OPCODE
Command
SCANEQN
Selected Data Register
EVENT QUALIFICATION
Table 3-9: Command EVENT QUALIFIC ATION REGISTER
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Programming
3.1.4 EVENT QUALIFICATION REGISTER
Signal EVCNT15 EVCNT14 EVCNT13 EVCNT12 EVCNT11 EVCNT10 EVCNT09 EVCNT08 EVCNT07 EVCNT06 EVCNT05 EVCNT04 EVCNT03 EVCNT02 EVCNT01 EVCNT00 EVADR3 EVADR2 EVADR1 EVADR0 EXPDAT15 EXPDAT14 EXPDAT13 EXPDAT12 EXPDAT11 EXPDAT10 EXPDAT09 EXPDAT08 EXPDAT07 EXPDAT06 EXPDAT05 EXPDAT04 EXPDAT03 EXPDAT02 EXPDAT01 EXPDAT00 MSKDAT15 MSKDAT14 MSKDAT13 MSKDAT12 MSKDAT11 MSKDAT10 MSKDAT09 MSKDAT08 MSKDAT07 MSKDAT06 MSKDAT05 MSKDAT04 MSKDAT03 MSKDAT02 MSKDAT01 MSKDAT00 EMADR3 EMADR2 EMADR1 EMADR0
EVENT QUALIFICATION REGISTER
data event counter
address event counter
expected data
bits masking data inputs: compared with expected data. used comparison.
address expected data masking bits
Table 3-10: Bits EVENT QUALIFICATION REGISTER during commands READFILE WRITEFILE
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Programming
Signal EVCNT15 EVCNT14 EVCNT13 EVCNT12 EVCNT11 EVCNT10 EVCNT09 EVCNT08 EVCNT07 EVCNT06 EVCNT05 EVCNT04 EVCNT03 EVCNT02 EVCNT01 EVCNT00 EXPDAT15 EXPDAT14 EXPDAT13 EXPDAT12 EXPDAT11 EXPDAT10 EXPDAT09 EXPDAT08 EXPDAT07 EXPDAT06 EXPDAT05 EXPDAT04 EXPDAT03 EXPDAT02 EXPDAT01 EXPDAT00 MSKDAT15 MSKDAT14 MSKDAT13 MSKDAT12 MSKDAT11 MSKDAT10 MSKDAT09 MSKDAT08 MSKDAT07 MSKDAT06 MSKDAT05 MSKDAT04 MSKDAT03 MSKDAT02 MSKDAT01 MSKDAT00
EVENT QUALIFICATION REGISTER
data event counter
expected data.
bits masking data inputs: compared with expected data. used comparison.
Table 3-11: Bits EVENT QUALIFICATION REGISTER during commands DMAFIN DMAFOUT Binary OPCODE
0110000 11100001 11100100 01100101
OPCODE
Command
READFILE WRITEFILE DMAFOUT DMAFIN
Selected Data Register
EVENT QUALIFICATION EVENT QUALIFICATION EVENT QUALIFICATION EVENT QUALIFICATION
Table 3-12: Commands EVENT QUALIFICATION REGISTER
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Programming
3.1.5 REGISTER
Signal RAMDAT15 RAMDAT14 RAMDAT13 RAMDAT12 RAMDAT11 RAMDAT10 RAMDAT09 RAMDAT08 RAMDAT07 RAMDAT06 RAMDAT05 RAMDAT04 RAMDAT03 RAMDAT02 RAMDAT01 RAMDAT00 RAMADR9 RAMADR8 RAMADR7 RAMADR6 RAMADR5 RAMADR4 RAMADR3 RAMADR2 RAMADR1 RAMADR0
REGISTER
data
address
Table 3-13: Bits REGISTER during commands READRAM WRITERAM.
Signal RAMDAT15 RAMDAT14 RAMDAT13 RAMDAT12 RAMDAT11 RAMDAT10 RAMDAT09 RAMDAT08 RAMDAT07 RAMDAT06 RAMDAT05 RAMDAT04 RAMDAT03 RAMDAT02 RAMDAT01 RAMDAT00
REGISTER
data
Table 3-14: Bits REGISTER during commands DMARIN DMAROUT.
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Programming Binary OPCODE
11100010 01100011 01100110 11100111 01101010 11101011
OPCODE
Command
READRAM WRITERAM DMAROUT DMARIN INITRAM TOGRAM
Selected Data Register
BYPASS BYPASS
Table 3-15: Commands REGISTER
3.1.6 HEADER REGISTER
Signal
HEADER REGISTER
HEADER REGISTER
Table 3-16: Bits HEADER REGISTER. Binary OPCODE
11101101
OPCODE
Command
SCANHDR
Selected Data Register
HEADER
Table 3-17: Command HEADER REGISTER
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Programming
3.1.7 TEST CELL REGISTER
Signal
TEST CELL REGISTER
TEST CELL REGISTER (PARALLEL SIGNATURE ANALYSIS)
Table 3-18: Bits TEST CELL REGISTER. Binary OPCODE
11101000 01101001
OPCODE
Command
SCANTCR READTCR
Selected Data Register
TEST CELL TEST CELL
Table 3-19: Commands TEST CELL REGISTER
3.1.8 BYPASS REGISTER
Signal
BYPASS REGISTER
BYPASS REGISTER
Table 3-20: Bits BYPASS REGISTER. Binary OPCODE
10000001 10001000 00001001 01101010 11101011 01101100 otherwise unused OPCODEs
OPCODE
Command
BYPASS RUNN RUNT INITRAM TOGRAM PSARAM BYPASS
Selected Data Register
BYPASS BYPASS BYPASS BYPASS BYPASS BYPASS BYPASS
Table 3-21: Commands BYPASS REGISTER
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Programming
3.1.9 BOUNDARY SCAN REGISTER
Signal CLK3 CLK2 CLK1 PIO_IN PIO_OUT ENPOI
BOUNDARY SCAN REGISTER
data inputs
CLOCK inputs input/output: input signal output signal signal direction: output input (EVENT QUALIFICATION INPUT) EVENT QUALIFICATION OUTPUT)
Table 3-22: Bits BOUNDARY SCAN REGISTER. Binary OPCODE
00000000 10000010
OPCODE
Command
EXTEST SAMPLE PRELOAD
Selected Data Register
BOUNDARY SCAN BOUNDARY SCAN
Table 3-23: Commands BOUNDARY SCAN REGISTER
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Programming
Protocols
exact time when data from inputs D15.D00 loaded into internal memory, time which data used PSA, shown below test; determined protocol EVENT QUALIFICATION REGISTER (bits 32.30). provides this purpose eight different protocols, which further influenced LOOP COUNTER EVENT COUNTER. LOOP COUNTER function determining number complete runs (protocols partial runs (protocols protocol; EVENT COUNTER registers number events, counts incoming clock signals during pause cycles, determines number tests which have conducted. LOOP COUNTER specific value with help bits 15.00 (LCNT15.LCNT00) EVENT QUALIFICATION REGISTER decremented according protocol selected. terminates protocol when counter reaches count Decrementing stopped with (LCNTDIS) EVENT QUALIFICATION REGISTER this case, LOOP COUNTER never reaches count protocol only stops when JTAG command shifted into INSTRUCTION REGISTER, LOOP COUNTER preloaded with count EVENT COUNTER reloaded during protocol implementation with data from EVENT QUALIFICATION REGISTER Since this register store words data, possible load EVENT COUNTER during protocol with different values, after other. protocol implementation influences decrementing EVENT COUNTER attaining count state with loop counter, EVENT COUNTER also switched (bit EVENT QUALIFICATION REGISTER Since however start data processing protocols always controlled EVENT COUNTER, switched-off event counter prevents implementation protocol. However, with switched-off event counter internal signals observed pin, example agreement between expected data input signals D15.D00. address counters EVENT QUALIFICATION REGISTER also have indirect influence implementation protocol. first these selects data words EVENT COUNTER, while second selects expected input data mask input data. soon either EVENT COUNTER, data which fact expected together with mask loaded, appropriate address counter automatically incremented accordingly. data stored EVENT QUALIFICATION REGISTER remain unchanged, also used again during implementation protocol. counters reaches count (Fh), then will incremented count zero.
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Programming subsequent sections, following definitions abbreviations will used present eight protocols: EVENT event EVENT QUALIFICATION REGISTER occurs, which selected with bits 22.20 (EQISELC.EQISELA). TEST Load word data from inputs D15.D00 into memory, and/or execute cycle with this data word. operation performed selected with bits 44.41 (OP3.OP0) CONTROL REGISTER. POLL Compare data inputs D15.D00 with expected data. ECNT EVENT COUNTER LCNT LOOP COUNTER Register which stores data expected input pins D15.D00, together with associated mask. <REG> decrement register <REG> load <REG> load value register <REG> from EVENT QUALIFICATION REGISTER increment associated address counter. event occurs several successive pulse edges, then treated single event. This represented blocks Figure 3-10 flow chart with protocol description.
Figure 3-10:Flow Chart Event Waiting Loops Protocols
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Programming
3.2.1 Protocol
Figure 3-11:Example Wave Forms Protocol Protocol shown Figure 3-11 wave forms Figure 3-12 flow chart. After event occurred times, data word will transferred into RAM, used PSA. This procedure repeated several times. When repeated twice, represented example Figure 3-11, then EVENT QUALIFICATION REGISTER should following: Address Event Counter Number Number Expected Data Event Data Event Data Data Mask Event Data Mask Event Data Mask
Should events come from input data D15.D00 from input pin, output also input data D15.D00, then values expected data data mask without significance.
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Programming
Figure 3-12:Flow Chart Protocol
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Programming
3.2.2 Protocol
Figure 3-13:Examples Wave Forms Protocol Protocol represented Figure 3-13 wave forms, Figure 3-14 flow chart. After event occurred times, data words transferred used PSA, long event active. This process repeated several times. When repeated twice, shown example Figure 3-13, then EVENT QUALIFICATION REGISTER should following: Address Event counter Number Number Expected Data Event Data Event Data Data Mask Event Data Mask Event Data Mask
events come from input data D15.D00 instead from input pin, output does also input data D15.D00, then values expected data data mask without significance.
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Programming
Figure 3-14:Flow Chart Protocol
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Programming
3.2.3 Protocol
Figure 3-15:Examples Wave Forms Protocol Protocol shown Figure 3-15 wave forms Figure 3-16 flow chart. Protocol operates with Start-Event Stop-Event. After Start-Event occurred times, words data will transferred into RAM, used PSA, until Stop-Event occurred times. This process repeated several times. When occurs once, shown example Figure 3-15, EVENT QUALIFICATION REGISTER should following: Address Event counter Number Number Expected Data Event Data Event Data Data Mask Event Data Mask Event Data Mask
events come from input data D15.D00 instead from input output does also input data D15.D00, then values expected data data mask without significance.
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Programming
Figure 3-16:Flow Chart Protocol 210E
Programming
3.2.4 Protocol
Figure 3-17:Examples Wave Forms Protocol Protocol shown Figure 3-17 wave forms, Figure 3-18 flow chart. This protocol identical with protocol with difference that after event occurred times, number further data words will processed. This process repeated several times. When occurs once, shown example Figure 3-17, then EVENT QUALIFICATION REGISTER should following: Address Event counter Number Number Number Expected Data Event Data Event Data without significance Data Mask Event Data Mask Event Data Mask without significance
events come from input data D15.D00 instead from input pin, output does also input data D15.D00, then values expected data data mask without significance.
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Programming
Figure 3-18:Flow Chart Protocol 210E
Programming
3.2.5 Protocol
Figure 3-19:Examples Wave Forms Protocol Protocol shown Figure 3-19 wave forms, Figure 3-20 flow chart. After event occurred times, number words transferred RAM, used PSA. This process repeated several times. When occurs once, shown example Figure 3-19, then EVENT QUALIFICATION REGISTER should following: Address Event counter Number Number Expected Data Event Data without significance Data Mask Event Data Mask without significance
events come from input data D15.D00, instead from input pin, output also does input data D15.D00, then values expected data data mask without significance.
210E
Programming
Figure 3-20:
Flow Chart Protocol
210E
Programming
3.2.6 Protocol
Figure 3-21:Examples Wave Forms Protocol Protocol shown Figure 3-21 wave forms, Figure 3-22 flow chart. Protocol conforms Protocol however extended pause between events data processing. After event occurred times, pause cycles inserted then number data words transferred RAM, used PSA. This process repeated several times. When occurs once, shown example Figure 3-21, EVENT QUALIFICATION REGISTER should following: Address Event counter Number Number Number Expected Data Event Data without significance without significance Data Mask Event Data Mask without significance without significance
events come from input data D15.D00 instead from input pin, output also does input data D15.D00, then values expected data data mask without significance.
210E
Programming
Figure 3-22:Flow Chart Protocol
210E
Programming
3.2.7 Protocol
Figure 3-23:Examples Wave Forms Protocol Protocol shown Figure 3-23 wave forms, Figure 3-24 flow chart. After Event occurred times, data words transferred RAM, used PSA, followed pause cycles. processing data subsequent pause cycles repeated several times; however, waiting event longer included this loop. implementation protocol already ends before last pause cycle. When repeated twice, shown example Figure 3-23, then EVENT QUALIFICATION REGISTER should following: Address Event counter Number Number Number Number Expected Data Event Data without significance without significance without significance Data Mask Event Data Mask without significance without significance without significance
events come from input data D15.D00 instead from input pin, output does also input data D15.D00, then values expected data data mask without significance.
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Programming
Figure 3-24:Flow Chart Protocol
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Programming
3.2.8 Protocol
Figure 3-25:
Examples Wave Forms Protocol
Protocol shown Figure 3-25 wave forms, Figure 3-26 flow chart. Protocol conforms basically protocol with difference that order pause cycles data processing reversed comparison with protocol After event occurred times, pause cycles inserted lastly number data words transferred RAM, used PSA. pause cycles subsequent data processing repeated several times; waiting event however, included this loop. When repeated twice, shown example Figure 3-25, EVENT QUALIFICATION REGISTER should with following: Address Event counter Number Number Number Number Number Expected Data Event Data without significance without significance without significance without significance Data Mask Event Data Mask without significance without significance without significance without significance
events come from input data D15.D00 instead from input pin, output does also input data D15.D00, then values expected data data mask without significance.
210E
Programming
Figure 3-26:Flow Chart Protocol
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Programming
Typical Program Sequence
order logic analyzer, following sequence register programming status control with JTAG typical: Reset 1024 memory Select desired logic analyzer function with CONTROL REGISTER, EVENT QUALIFICATION REGISTER EVENT QUALIFICATION REGISTER Start analyzer function with JTAG command RUNN. Request status DBM, order recognize operation. Read JTAG bus.
Similarly logic analyzer function, following programming sequence typical Parallel Signature Analysis (PSA): Loading TEST CELL REGISTER with desired initial state PSA. Select desired function with CONTROL REGISTER, EVENT QUALIFICATION REGISTER EVENT QUALIFICATION REGISTER Start function with JTAG command RUNN. Request status DBM, order recognize operation. Read result from TEST CELL REGISTER JTAG bus.
Further details given here programming sequence JTAG basic functions EXTEST, BYPASS SAMPLE, which needed order implement interconnection other similar tests. These done with similar fashion usual with every other JTAG component, example SCOPEOCTALs.
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Examples
Examples
examples which follow arranged four sections follows: Basic Functions, Protocols, PSA, Tips Tricks. Writing into reading EQR2 (EVENT QUALIFICATION REGISTER together with requesting status during RUNN command, essential parts basic functions. second part, example program shown each eight protocols. section "Tips Tricks" shows additional functions which achieved making appropriate programming.
Basic Functions
4.1.1 Writing into
Aim: Write word data 1024 16-Bit memory. this example word data 0011001111001100 should stored under memory address =2CFh). Write JTAG command WRITERAM with IR-SCAN. Transfer with DR-SCAN address associated word data. Programming:
SCAN-TYPE Input data IR-SCAN WRITERAM DR-SCAN 0011001111001100 1011001111 Output data 10000001 ???????????????? ??????????
Method:
4.1.2 Reading
Aim: Read word data from specific address 1024 memory. this example, word data 0011001111001100 should read from memory address (=2CFh). Enter JTAG command READRAM with IR-SCAN. Transfer with DR-SCAN address. Read with further DR-SCAN address data. 210E
Method:
Examples Programming:
SCAN-TYPE IR-SCAN DR-SCAN DR-SCAN Input data READRAM 0000000000000000 1011001111 0000000000000000 1011010000 Output data 10000001 ???????????????? ?????????? 0011001111001100 1011001111
With first DR-SCAN receives output word data some address other. Only second DR-SCAN supplies address being sought associated word data. this point already enter next address which read this case: 720).
4.1.3 Writing into with
Aim: Write into complete 1024 memory. into status PAUSE-DR Change SHIFT-DR EXIT2-DR (see Figure 2-2) start DRSCAN. reads words data, after another, from memory addresses 1023, from input TDI. output data undefined. Programming:
SCAN-TYPE IR-SCAN DR-SCAN Input data Output data DMARIN enter PAUSE-DR 0000010001000000 0001000100000000 0001010000010000 0001101100100111 10000001 ???????????????? ???????????????? ???????????????? ????????????????
Method Enter JTAG command DMARIN means IR-SCAN.
Method Enter JTAG command SCANHDR with IR-SCAN. Load pattern with DR-SCAN into HEADER REGISTER. Enter JTAG command DMARIN with IR-SCAN. into status SHIFT-DR. soon recognizes pattern loaded input into HEADER REGISTER, begins read words data from input into memory addresses 1023. output data undefined.
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Examples Programming:
SCAN-TYPE IR-SCAN DR-SCAN IR-SCAN DR-SCAN Input data SCANHDR 00111100 DMARIN 00111100 0000010001000000 0001000100000000 0001010000010000 0001101100100111 Output data 10000001 ???????? 10000001 ???????? ???????????????? ???????????????? ???????????????? ????????????????
4.1.4 Reading with
Aim: read complete 1024 data memory. into status PAUSE-DR Change SHIFT-DR EXIT2-DR (see Figure 2-2), implement DR-SCAN. outputs words data from memory address 1023, after other. input data ignored. Programming:
SCAN-TYPE IR-SCAN DR-SCAN Input data Output data DMAROUT enter PAUSE-DR 0000000000000000 0000000000000000 0000000000000000 0000000000000000 10000001 0000010001000000 0001000100000000 0001010000010000 0001101100100111
Method Enter JTAG command DMAROUT with IR-SCAN.
Method Enter JTAG command SCANHDR with IR-SCAN. Load pattern with DR-SCAN into HEADER REGISTER. Enter JTAG command DMAROUT with IR-SCAN. status SHIFT-DR. soon recognizes input pattern loaded into HEADER REGISTER, begins output, after another, words data from memory addresses 1023 TDO. From this moment, input data ignored.
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Examples Programming:
SCAN-TYPE IR-SCAN DR-SCAN IR-SCAN DR-SCAN Input data SCANHDR 11000011 DMAROUT 11000011 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Output data 10000001 ???????? 10000001 ???????? 0000010001000000 0001000100000000 0001010000010000 0001101100100111
4.1.5 Filling
Aim: Method: 1024 memory should filled with zeroes. OCLK should programmed with help CONTROL REGISTER. filling word, this case 00h, should sent address Enter JTAG command INITRAM with IR-SCAN. Wait 1024 clock cycles RUN-TEST/IDLE status, order copy filling word into memory cells addresses 1023. Programming:
SCAN-TYPE IR-SCAN DR-SCAN IR-SCAN DR-SCAN IR-SCAN Input data Output data SCANCN 0000 0000 0000000000000000 0000000000000000 WRITERAM 0000000000000000 0000000000 INITRAM 1024 Clock Cycles RUN-TEST/IDLE 10000001 ???? ???? ???????????????? ???????????????? 10000001 ???????????????? ?????????? 10000001
When using command TOGRAM instead INITRAM, data bits will each invert when they copied into cells, can, example, then fill memory with Checkerboard Sample.
4.1.6 Writing into EQR2
Aim: Write word data into EVENT QUALIFICATION REGISTER this example, following values should stored under memory address event counter: expected data: bit-mask: 0000000100100011 1234h) 0110011110001001 6789h) 1100110111101111 CDEFh)
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Examples Method: Enter JTAG command WRITEFILE with IR-SCAN. Transfer addresses associated words data with DR-SCAN. Programming:
SCAN-TYPE Input data IR-SCAN WRITEFILE DR-SCAN 0000000100100011 0010 0110011110001001 1100110111101111 0010 Output data 10000001 ???????????????? ???? ???????????????? ???????????????? ????
With first DR-SCAN, words data some EQR2 address other received output DBM. Only second DR-SCAN supplies addresses which have been sought, corresponding words data. this point already enter next EQR2 addresses which have read this case each. address event counter address expected data masks have identical.
4.1.7 Reading EQR2
Aim: Read word data from defined address EVENT QUALIFICATION REGISTER this example following values from memory address should read: event counter: expected data: mask: Method: 0000000100100011 1234h) 0110011110001001 6789h) 1100110111101111 CDEFh)
Enter JTAG command READFILE with IR-SCAN. Transfer both addresses with DR-SCAN. Read addresses data with further DR-SCAN.
Programming:
SCAN-TYPE IR-SCAN DR-SCAN Input data Output data READFILE 0000000000000000 0010 0000000000000000 0000000000000000 0010 0000000000000000 0011 0000000000000000 0000000000000000 0011 10000001 ???????????????? ???? ???????????????? ???????????????? ???? 0000000100100011 0010 0110011110001001 1100110111101111 0010
DR-SCAN
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Examples
4.1.8 Writing into EQR2 with
Aim: Write into complete EQR2. status PAUSE-DR. Change SHIFT-DR EXIT2-DR (see Figure 2-2), implement DR-SCAN. reads words data input successively from memory address output data undefined. Programming:
SCAN-TYPE IR-SCAN DR-SCAN Input data Output data DMAFIN PAUSE-DR 0000010001000000 0001000100000000 0001010000010000 0001101100100111 10000001 ???????????????? ???????????????? ???????????????? ????????????????
Method Enter JTAG command DMAFIN with IR-SCAN.
Method Enter JTAG command SCANHDR with IR-SCAN. Load pattern into HEADER REGISTER with DR-SCAN. Enter JTAG command DMAFIN with IR-SCAN. into status SHIFT-DR. soon input recognizes pattern loaded HEADER REGISTER, begins read words data, after other, from input into memory addresses output data undefined time. Programming:
SCAN-TYPE IR-SCAN DR-SCAN IR-SCAN DR-SCAN Input data Output data SCANHDR 00111100 DMAFIN 00111100 0000010001000000 0001000100000000 0001010000010000 0001101100100111 10000001 ???????? 10000001 ???????? ???????????????? ???????????????? ???????????????? ????????????????
210E
Examples
4.1.9 Reading EQR2 with
Aim: Read total 1024 memory. status PAUSE-DR Change SHIFT-DR EXIT2-DR (see Figure 2-2), implement DR-SCAN. outputs successively words data from memory addresses input data ignored. Programming:
SCAN-TYPE IR-SCAN DR-SCAN Input data Output data DMAFOUT PAUSE-DR 0000000000000000 0000000000000000 0000000000000000 0000000000000000 10000001 0000010001000000 0001000100000000 0001010000010000 0001101100100111
Method Enter JTAG command DMAFOUT with IR-SCAN.
Method Enter JTAG comman SCANHDR with IR-SCAN. Load pattern with DR-SCAN into HEADER REGISTER. Enter JTAG command DMAFOUT with IR-SCAN. into status SHIFT-DR. soon recognizes pattern loaded into HEADER REGISTER input, begins successively output words data from memory addresses From this moment input data ignored. Programming:
SCAN-TYPE IR-SCAN DR-SCAN IR-SCAN DR-SCAN Input data Output data SCANHDR 11000011 DMAFOUT 11000011 0000000000000000 0000000000000000 0000000000000000 0000000000000000 10000001 ???????? 10000001 ???????? 0000010001000000 0001000100000000 0001010000010000 0001101100100111
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Examples
4.1.10 Read Status during RUNN
Aim: Method: current status should established while JTAG command RUNN active. Enter JTAG command RUNN repeatedly with IR-SCAN, evaluate INSTRUCTION REGISTER STATUS WORD.
Input data Output data
Programming:
SCAN-TYPE IR-SCAN IR-SCAN IR-SCAN IR-SCAN IR-SCAN
RUNN RUNN RUNN RUNN RUNN
10000001 00000001 10100001 11100001 10010001
IR-SCAN successful, test begun, memory overflow. IR-SCAN successful, that command BYPASS active. IR-SCAN successful, test begun, memory overflow. IR-SCAN successful, test begun, memory overflow i.e. address counter incremented from 3FFh 000h. IR-SCAN successful, test finished, memory overflow.
repeated entry JTAG command RUNN does interrupt implementation already running command RUNN. RUNN occurs only when command RUNN been successfully completed, command other than RUNN made active.
4.1.11 Read Address Counter
Aim: Method: Read current status address counter. Enter JTAG command READRAM with IR-SCAN. Read current counter status with DR-SCAN. Programming:
SCAN-TYPE IR-SCAN DR-SCAN Input data Output data READRAM 0000000000000000 0000000000 10000001 ???????????????? AAAAAAAAAA
With first DR-SCAN status address counter received output DBM. This will however immediately overwritten with execution commands READRAM WRITERAM.
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Examples
4.1.12 Address Counter
Aim: Method: address counter should particular value this case, 2CFh. Enter JTAG command READRAM with R-SCAN. counter with DR-SCAN. Programming:
SCAN-TYPE IR-SCAN DR-SCAN Input data Output data READRAM 0000000000000000 1011001111 10000001 ???????????????? AAAAAAAAAA
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Examples
Protocols
this section, examples will used demonstrate programmed order implement eight protocols. These examples intended introduction protocol programming DBM.
4.2.1 Protocol
Aim: first waits appearance twice data word ???5h, i.e. least significant bits must have value whereas most significant bits tested. loads word data into internal memory. then waits times data word 0006h. this case bits extracted testing. loads further word data into internal memory. Method: CONTROL REGISTER RUNN OPCODE TRACE; inputs loaded directly into RAM; address counter stops maximum value 3FFh; Parity errors JTAG commands will outputted EQO; inputs compared directly with expected data; RUNN Clock Signal CLK1; feedback mask here without significance; Mask here without significance; EVENT QUALIFICATION REGISTER Protocol Synchronous signal, simplified status interrogation; addresses begin with output signal here compulsory); triggering event DCTERM used; loop counter LCNT active; event counter ECNT active; data loaded according Protocol ENACMP here without significance, since CTERM; loop counter LCNT value EVENT QUALIFICATION REGISTER
Address EVENT COUNTER Expected Data Mask Data 1111111111110000 0000000000000000
Activate RUNN command wait until test finished.
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Examples Programming:
SCAN-TYPE Input Data IR-SCAN SCANCN DR-SCAN 1000 0001 0000000000000000 1111111111111111 IR-SCAN SCANEQN DR-SCAN 0010 0000000000000010 IR-SCAN WRITEFILE DR-SCAN 0000000000000010 0000 0000000000000101 1111111111110000 0000 DR-SCAN 0000000000000011 0001 0000000000000110 0000000000000000 0001 IR-SCAN RUNN IR-SCAN RUNN IR-SCAN RUNN
Output Data 10000001 ???? ???? ???????????????? ???????????????? 10000001 ???? ???????????????? 10000001 ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? 10000001 10100001 10010001
DBM-Status: IR-SCAN successful, RUNN begun. DBM-Status: RUNN execution begun. DBM-Status: RUNN execution finished.
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Examples
4.2.2 Protocol
Aim: first waits appearance twice data word ???5h, i.e. least significant bits must have value whereas most significant bits tested. starts load data into internal memory, until least significant bits longer show value then waits times data word 12??h i.e. least significant bits tested, whereas most significant bits must show value 12h. loads data words into internal memory, until most significant bits longer show value 12h. Method: CONTROL REGISTER RUNN OPCODE TRACE; inputs loaded directly into RAM; address counter stops maximum value 3FFh; Parity errors JTAG commands will outputted EQO; inputs compared directly with expected data; RUNN Clock Signal CLK1; feedback mask here without significance; Mask here without significance; EVENT QUALIFICATION REGISTER Protocol Synchronous signal, simplified status interrogation; addresses begin with output signal here compulsory); triggering event DCTERM used; loop counter LCNT active; event counter ECNT active; data loaded according Protocol ENACMP here without significance, since CTERM; loop counter LCNT value EVENT QUALIFICATION REGISTER
Address EVENT COUNTER Expected Data 1200h Mask Data 1111111111110000 0000000011111111
Activate RUNN command wait until test finished. counter state address counter must read order find number read values.
210E
Examples Programming:
SCAN-TYPE Input Data IR-SCAN SCANCN DR-SCAN 1000 0001 0000000000000000 1111111111111111 IR-SCAN SCANEQN DR-SCAN 0010 0000000000000010 IR-SCAN WRITEFILE DR-SCAN 0000000000000010 0000 0000000000000101 1111111111110000 0000 DR-SCAN 0000000000000011 0001 0001001000000000 0000000011111111 0001 IR-SCAN RUNN IR-SCAN RUNN IR-SCAN RUNN IR-SCAN READRAM DR-SCAN 0000000000000000 0000000000
Output Data 10000001 ???? ???? ???????????????? ???????????????? 10000001 ???? ???????????????? 10000001 ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? 10000001 10100001 10010001 10000001 ???????????????? AAAAAAAAAA
DBM-Status: IR-SCAN successful, RUNN begun. DBM-Status: RUNN execution begun. DBM-Status: RUNN execution finished. AAAAAAAAAA count state address counter. filled with data address area from AAAAAAAAAA
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Examples
4.2.3 Protocol
Aim: first waits appearance twice data word ???5h, i.e. least significant bits must have value whereas most significant bits tested. begins transfer words data into internal memory. During transfer, waits times data word 00?6h i.e. least significant bits must show value most significant bits must show value 00h. stops storing words data. Method: CONTROL REGISTER RUNN OPCODE TRACE; inputs loaded directly into RAM; address counter stops maximum value 3FFh; Parity errors JTAG commands will outputted EQO; inputs compared directly with expected data; RUNN Clock Signal CLK1; feedback mask here without significance; Mask here without significance; EVENT QUALIFICATION REGISTER Protocol Synchronous signal, simplified status interrogation; addresses begin with output signal TGATE here compulsory); triggering event DCTERM used; loop counter LCNT active; event counter active; data loaded according Protocol ENACMP here without significance, since CTERM; loop counter LCNT value EVENT QUALIFICATION REGISTER
Address EVENT COUNTER Expected Data 0006h Mask Data 1111111111110000 0000000011110000
Activate RUNN command wait until test finished. counter state address counter must read order find number read values.
210E
Examples Programming:
SCAN-TYPE Input Data IR-SCAN SCANCN DR-SCAN 1000 0001 0000000000000000 1111111111111111 IR-SCAN SCANEQN DR-SCAN 0110 0000000000000001 IR-SCAN WRITEFILE DR-SCAN 0000000000000010 0000 0000000000000101 1111111111110000 0000 DR-SCAN 0000000000000011 0001 0000000000000110 0000000011110000 0001 IR-SCAN RUNN IR-SCAN RUNN IR-SCAN RUNN IR-SCAN READRAM DR-SCAN 0000000000000000 0000000000
Output Data 10000001 ???? ???? ???????????????? ???????????????? 10000001 ???? ???????????????? 10000001 ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? 10000001 10100001 10010001 10000001 ???????????????? AAAAAAAAAA
DBM-Status: IR-SCAN successful, RUNN begun. DBM-Status: RUNN execution begun. DBM-Status: RUNN execution finished. AAAAAAAAAA count state address counter. filled with data address area from AAAAAAAAAA
210E
Examples
4.2.4 Protocol
Aim: first waits appearance twice data word ???5h, i.e. least significant bits must have value whereas most significant bits tested. begins transfer into internal memory. During transfer, waits times data word 00?6h i.e. least significant bits must show value most significant bits must show value 00h. stores further words data before finishes data acquisition. Method: CONTROL REGISTER RUNN OPCODE TRACE; inputs loaded directly into RAM; address counter stops maximum value 3FFh; Parity errors JTAG commands will outputted EQO; inputs compared directly with expected data; RUNN Clock Signal CLK1; feedback mask here without significance; Mask here without significance; EVENT QUALIFICATION REGISTER Protocol Synchronous signal, simplified status interrogation; addresses begin with output signal TGATE here compulsory); triggering event DCTERM used; loop counter LCNT active; event counter ECNT active; data loaded according Protocol ENACMP here without significance, since CTERM; loop counter LCNT value EVENT QUALIFICATION REGISTER
Address EVENT COUNTER Expected Data 0006h used Mask Data 1111111111110000 0000000011110000 used
Activate RUNN command wait until test finished. counter state address counter must read order find number read values.
210E
Examples Programming:
SCAN-TYPE Input Data IR-SCAN SCANCN DR-SCAN 1000 0001 0000000000000000 1111111111111111 IR-SCAN SCANEQN DR-SCAN 0110 0000000000000001 IR-SCAN WRITEFILE DR-SCAN 0000000000000010 0000 0000000000000101 1111111111110000 0000 DR-SCAN 0000000000000011 0001 0000000000000110 0000000011110000 0001 DR-SCAN 0000000000000111 0010 0000000000000000 0000000000000000 0010 IR-SCAN RUNN IR-SCAN RUNN IR-SCAN RUNN IR-SCAN READRAM DR-SCAN 0000000000000000 0000000000
Output Data 10000001 ???? ???? ???????????????? ???????????????? 10000001 ???? ???????????????? 10000001 ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? 10000001 10100001 10010001 10000001 ???????????????? AAAAAAAAAA
DBM-Status: IR-SCAN successful, RUNN begun. DBM-Status: RUNN execution begun. DBM-Status: RUNN execution finished. AAAAAAAAAA count state address counter. filled with data address area from AAAAAAAAAA
210E
Examples
4.2.5 Protocol
Aim: first waits appearance twice data word ???5h, i.e. least significant bits must have value whereas most significant bits tested. loads words data into internal memory. Method: CONTROL REGISTER RUNN OPCODE TRACE; inputs loaded directly into RAM; address counter stops maximum value 3FFh; Parity errors JTAG commands will outputted EQO; inputs compared directly with expected data; RUNN Clock Signal CLK1; feedback mask here without significance; Mask here without significance; EVENT QUALIFICATION REGISTER Protocol Synchronous signal, simplified status interrogation; addresses begin with output signal here compulsory); triggering event DCTERM used; loop counter LCNT active; event counter ECNT active; data loaded according Protocol ENACMP here without significance, since CTERM; loop counter LCNT value EVENT QUALIFICATION REGISTER
Address EVENT COUNTER Expected Data used Mask Data 1111111111110000 used
Activate RUNN command wait until test finished.
210E
Examples Programming:
SCAN-TYPE Input Data IR-SCAN SCANCN DR-SCAN 1000 0001 0000000000000000 1111111111111111 IR-SCAN SCANEQN DR-SCAN 0100 0000000000000001 IR-SCAN WRITEFILE DR-SCAN 0000000000000010 0000 0000000000000101 1111111111110000 0000 DR-SCAN 0000000000000011 0001 0000000000000000 0000000000000000 0001 IR-SCAN RUNN IR-SCAN RUNN IR-SCAN RUNN
Output Data 10000001 ???? ???? ???????????????? ???????????????? 10000001 ???? ???????????????? 10000001 ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? 10000001 10100001 10010001
DBM-Status: IR-SCAN successful, RUNN begun. DBM-Status: RUNN execution begun. DBM-Status: RUNN execution finished.
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Examples
4.2.6 Protocol
Aim: first waits appearance twice data word ???5h, i.e. least significant bits must have value whereas most significant bits tested. waits clock cycles. loads words data into internal memory. Method: CONTROL REGISTER RUNN OPCODE TRACE; inputs loaded directly into RAM; address counter stops maximum value 3FFh; Parity errors JTAG commands will outputted EQO; inputs compared directly with expected data; RUNN Clock Signal CLK1; feedback mask here without significance; Mask here without significance; EVENT QUALIFICATION REGISTER Protocol Synchronous signal, simplified status interrogation; addresses begin with output signal here compulsory); triggering event DCTERM used; loop counter LCNT active; event counter active; data loaded according Protocol ENACMP here without significance, since CTERM; loop counter LCNT value EVENT QUALIFICATION REGISTER
Address EVENT COUNTER Expected Data used used Mask Data 1111111111110000 used used
Activate RUNN command wait until test finished.
210E
Examples Programming:
SCAN-TYPE Input Data IR-SCAN SCANCN DR-SCAN 1000 0001 0000000000000000 1111111111111111 IR-SCAN SCANEQN DR-SCAN 0100 0000000000000001 IR-SCAN WRITEFILE DR-SCAN 0000000000000010 0000 0000000000000101 1111111111110000 0000 DR-SCAN 0000000000000100 0001 0000000000000000 0000000000000000 0001 DR-SCAN 0000000000000011 0010 0000000000000000 0000000000000000 0010 IR-SCAN RUNN IR-SCAN RUNN IR-SCAN RUNN
Output Data 10000001 ???? ???? ???????????????? ???????????????? 10000001 ???? ???????????????? 10000001 ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? 10000001 10100001 10010001
DBM-Status: IR-SCAN successful, RUNN begun. DBM-Status: RUNN execution begun. DBM-Status: RUNN execution finished.
210E
Examples
4.2.7 Protocol
Aim: first waits appearance twice data word ???5h, i.e. least significant bits must have value whereas most significant bits tested. loads words data into internal memory. waits clock cycles. Lastly, loads words data into internal memory. Method: CONTROL REGISTER RUNN OPCODE TRACE; inputs loaded directly into RAM; address counter stops maximum value 3FFh; Parity errors JTAG commands will outputted EQO; inputs compared directly with expected data; RUNN Clock Signal CLK1; feedback mask here without significance; Mask here without significance; EVENT QUALIFICATION REGISTER Protocol Synchronous signal, simplified status interrogation; addresses begin with output signal here compulsory); triggering event DCTERM used; loop counter LCNT active; event counter ECNT active; data loaded according Protocol ENACMP here without significance, since CTERM; loop counter LCNT value EVENT QUALIFICATION REGISTER
Address EVENT COUNTER Expected Data used used used Mask Data 1111111111110000 used used used
Activate RUNN command wait until test finished.
210E
Examples Programming:
SCAN-TYPE Input Data IR-SCAN SCANCN DR-SCAN 1000 0001 0000000000000000 1111111111111111 IR-SCAN SCANEQN DR-SCAN 0100 0000000000000010 IR-SCAN WRITEFILE DR-SCAN 0000000000000010 0000 0000000000000101 1111111111110000 0000 DR-SCAN 0000000000000100 0001 0000000000000000 0000000000000000 0001 DR-SCAN 0000000000000011 0010 0000000000000000 0000000000000000 0010 DR-SCAN 0000000000000101 0011 0000000000000000 0000000000000000 0011 IR-SCAN RUNN IR-SCAN RUNN IR-SCAN RUNN
Output Data 10000001 ???? ???? ???????????????? ???????????????? 10000001 ???? ???????????????? 10000001 ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? 10000001 10100001 10010001
DBM-Status: IR-SCAN successful, RUNN begun. DBM-Status: RUNN execution begun. DBM-Status: RUNN execution finished.
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Examples
4.2.8 Protocol
Aim: first waits appearance twice data word ???5h, i.e. least significant bits must have value whereas most significant bits tested. waits clock cycles. loads words data into internal memory. waits further clock cycles. Lastly, loads again data words into internal memory. Method: CONTROL REGISTER RUNN OPCODE TRACE; inputs loaded directly into RAM; address counter stops maximum value 3FFh; Parity errors JTAG commands will outputted EQO; inputs compared directly with expected data; RUNN Clock Signal CLK1; feedback mask here without significance; Mask here without significance; EVENT QUALIFICATION REGISTER Protocol Synchronous signal, simplified status interrogation; addresses begin with output signal here compulsory); triggering event DCTERM used; loop counter LCNT active; event counter ECNT active; data loaded according Protocol ENACMP here without significance, since CTERM; loop counter LCNT value EVENT QUALIFICATION REGISTER
Address EVENT COUNTER Expected Data used used used used Mask Data 1111111111110000 used used used used
Activate RUNN command wait until test finished.
210E
Examples Programming:
SCAN-TYPE Input Data IR-SCAN SCANCN DR-SCAN 1000 0001 0000000000000000 1111111111111111 IR-SCAN SCANEQN DR-SCAN 0100 0000000000000010 IR-SCAN WRITEFILE DR-SCAN 0000000000000010 0000 0000000000000101 1111111111110000 0000 DR-SCAN 0000000000000100 0001 0000000000000000 0000000000000000 0001 DR-SCAN 0000000000000011 0010 0000000000000000 0000000000000000 0010 DR-SCAN 0000000000000101 0011 0000000000000000 0000000000000000 0011 DR-SCAN 0000000000000111 0100 0000000000000000 0000000000000000 0100 IR-SCAN RUNN IR-SCAN RUNN IR-SCAN RUNN
Output Data 10000001 ???? ???? ???????????????? ???????????????? 10000001 ???? ???????????????? 10000001 ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? 10000001 10100001 10010001
Status: IR-SCAN successful, RUNN begun. Status: RUNN execution begun. Status: RUNN execution finished.
Parallel Signature Analysis (PSA) made both inputs D15.D00, also from content RAM. both cases user must chose length shift register, bits used PSA, both number, location, feedback loops.
also performed parallel with loading RAM.
210E
Examples
4.3.1
Aim: should made from addresses initial state PSA, FFFFh used. Feedback should available bits With command SCANTCR, initial value this case: 1111111111111111) should shifted into TEST CELL REGISTER. command READRAM initializes start address value CONTROL REGISTER RUNN OPCODE PSA, cascaded; inputs used directly PSA; address counter stops 3FFh (here without significance); Parity errors JTAG commands outputted EQO; inputs compared directly with expected data (here without significance); RUNN clock signal TCK; feedback mask 1100110011001100; mask 0000000000000000 (all bits used); Shift JTAG command PSARAM with IR-SCAN. Wait clock cycles TEST/IDLE state, order pass three words data from addresses PSA. With command READTCR, result read from TEST CELL REGISTER. Programming:
SCAN-TYPE IR-SCAN DR-SCAN IR-SCAN DR-SCAN IR-SCAN DR-SCAN IR-SCAN IR-SCAN DR-SCAN
Method:
Input Data
Output Data
SCANTCR 1111111111111111 READRAM 0000000000000000 0000000101 SCANCN 0100 0000 1100110011001100 0000000000000000 PSARAM Clock cycles RUN-TEST/IDLE READTCR 0000000000000000
10000001 ???????????????? 10000001 ???????????????? ?????????? 10000001 ???? ???? ???????????????? ???????????????? 10000001 10000001 EEEEEEEEEEEEEEEE
EEEEEEEEEEEEEEEE bits resulting from PSA.
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Examples
4.3.2 Real-Time
Real-Time will demonstrated here using protocol example; performed with each protocols. Aim: first waits appearance twice word data ???5h, i.e. least significant bits must show value whereas most significant value bits tested. performs from next words data TEST CELL REGISTER. Method: With command SCANTCR, initial value this case: 1111111111111111) shifted into TEST CELL REGISTER. CONTROL REGISTER RUNN OPCODE PSA, cascaded; inputs used directly PSA; address counter stops 3FFh (here without significance); Parity errors JTAG command will outputted EQO; inputs compared directly with expected data; RUNN clock signal CLK1; feedback mask 1100110011001100; mask 0000000000000000 (all bits used); EVENT QUALIFICATION REGISTER Protocol Synchronous signal simple status request; address begins (here without significance); output signal (not compulsory here); DCTERM used triggering event; loop counter LCNT active; event counter active; data loaded according Protocol ENACMP without significance, since CTERM; loop counter LCNT value EVENT QUALIFICATION REGISTER
Address EVENT COUNTER Expected Data used Mask Data 1111111111110000 used
Activate RUNN command, wait until test finished. result read with command READTCR from TEST CELL REGISTER.
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Examples Programming:
SCAN-TYPE IR-SCAN DR-SCAN IR-SCAN DR-SCAN IR-SCAN DR-SCAN IR-SCAN DR-SCAN Input Data SCANTCR 1111111111111111 SCANCN 0100 0001 1100110011001100 0000000000000000 SCANEQN 0100 0000000000000001 WRITEFILE 0000000000000010 0000 0000000000000101 1111111111110000 0000 0000000000000011 0001 0000000000000000 0000000000000000 0001 RUNN RUNN RUNN READTCR 0000000000000000 Output Data 10000001 ???????????????? 10000001 ???? ???? ???????????????? ???????????????? 10000001 ???? ???????????????? 10000001 ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? 10000001 10100001 10010001 10000001 EEEEEEEEEEEEEEEE
DR-SCAN
IR-SCAN IR-SCAN IR-SCAN IR-SCAN DR-SCAN
status: IR-SCAN successful. RUNN begun. status: RUNN execution begun. status: RUNN execution finished. EEEEEEEEEEEEEEEE resulting bits PSA.
4.3.3 with three cascaded DBMs
real-time with three cascaded DBMs will shown here using protocol example. performed with each protocols. With cascaded PSA, attention must paid both correct programming components (MOST SIGNIFICANT DEVICE, MIDDLE DEVICE, LEAST SIGNIFICANT DEVICE), also sequence JTAG scanning path; reason this that JTAG path used also performing (Figure Page Aim: DBMs first wait appearance twice word data ???????????5h, i.e. least significant bits must have value whereas most significant bits tested. DBMs perform from next data words TEST CELL REGISTER. Method: With command SCANTCR initial value this case: FFFFFFFFFFFFh shifted into TEST CELL REGISTER.
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Examples CONTROL REGISTER DBM1 RUNN OPCODE PSA, LSD; DBM2 RUNN OPCODE PSA, MID; DBM3 RUNN OPCODE PSA, MSD; inputs used directly PSA; address counter stops 3FFh (here without significance); Parity errors JTAG commands outputted EQO; inputs compared directly with expected data; RUNN clock signal CLK1; feedback mask each case 1100110011001100; mask each case 0000000000000000 (all bits used); EVENT QUALIFICATION REGISTER Protocol Synchronous signal, simple status request; address begins (here without significance); output signal CTERM; input used triggering event; loop counter LCNT active; event counter active; data loaded according Protocol becomes active soon expected data have been found; loop counter LCNT each case value EVENT QUALIFICATION REGISTER DBM1:
Address EVENT COUNTER Expected Data used Mask Data 1111111111110000 used
DBM2 DBM3:
Address EVENT COUNTER Expected Data used used Mask Data 1111111111111111 used
Activate RUNN command, wait until test finished. result read with command READTCR from three TEST CELL REGISTERs.
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Examples Programming:
SCAN-TYPE Input Data IR-SCAN SCANTCR SCANTCR SCANTCR DR-SCAN 1111111111111111 1111111111111111 1111111111111111 IR-SCAN SCANCN SCANCN SCANCN DR-SCAN 0101 0001 1100110011001100 0000000000000000 0110 0001 1100110011001100 0000000000000000 0111 0001 1100110011001100 0000000000000000 IR-SCAN SCANEQN SCANEQN SCANEQN DR-SCAN 1010 0000000000000001 1010 0000000000000001 1010 0000000000000001 IR-SCAN WRITEFILE WRITEFILE WRITEFILE DR-SCAN 0000000000000010 0000 0000000000000000 1111111111111111 0000 0000000000000010 0000 0000000000000000 1111111111111111 0000 0000000000000010 0000 0000000000000101 1111111111110000 0000 DR-SCAN 0000000000000011 0001 0000000000000000 0000000000000000 0001 0000000000000011 0001 0000000000000000 0000000000000000 0001 0000000000000011 0001 0000000000000000 0000000000000000 0001 IR-SCAN RUNN RUNN RUNN IR-SCAN RUNN RUNN RUNN IR-SCAN RUNN RUNN RUNN IR-SCAN READTCR DR-SCAN 0000000000000000 0000000000000000 0000000000000000
Output Data 10000001 10000001 10000001 ???????????????? ???????????????? ???????????????? 10000001 10000001 10000001 ???? ???? ???????????????? ???????????????? ???? ???? ???????????????? ???????????????? ???? ???? ???????????????? ???????????????? 10000001 10000001 10000001 ???? ???????????????? ???? ???????????????? ???? ???????????????? 10000001 10000001 10000001 ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? 10000001 10000001 10000001 10100001 10100001 10100001 10010001 10010001 10010001 10000001 10000001 10000001 EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEE
status: IR-SCAN successful; RUNN started. status: RUNN execution begun. status: RUNN execution finished. bits result PSA.
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Examples
Tips Tricks
4.4.1 Self test
This example extension basic functions which have already been demonstrated. this reason, only test starting from basic functions will shown, however details register programming. Aim: Method: internal functions should tested. first filled with data. this purpose, command either INITRAM TOGRAM used. then performed. test repeated several times with various contents RAM. Some results PSA:
Command fill INITRAM INITRAM INITRAM INITRAM TOGRAM TOGRAM TOGRAM TOGRAM Content addresses: 0000h addresses: FFFFh addresses: 5555h addresses: AAAAh Address 000h: 0000h Address 001h: FFFFh Address 000h: FFFFh Address 001h: 0000h Address 000h: 5555h Address 001h: AAAAh Address 000h: AAAAh Address 001h: 5555h Initial value TEST CELL REGISTER 1111111111111111 1111111111111111 1111111111111111 1111111111111111 1111111111111111 1111111111111111 1111111111111111 1111111111111111 Result after 1024 RUNTEST/IDLE cycles, beginning with address 000h 0110111110110101 0000011101001110 0100100000011100 0010000011100111 0010000011100111 0100100000011100 0000011101001110 0110111110110101
4.4.2 Three Clock Inputs
clock inputs, CLK1, CLK2 CLK3. used judiciously, these clock inputs significantly simplify programming DBM. example, possibility offered connecting these three clock inputs following signals microprocessor system which needs tested (see Figure 4-27): CLK1: CLK2: CLK3: System clock microprocessor WRITE ENABLE signal microprocessor READ ENABLE signal microprocessor
OCLK CLK1 (POLSEL,SELD.SELA 00001), then cycles processor clock included test. OCLK programmed with CLK1 CLK2 (POLSEL, SELD.SELA 00101), then occupies itself exclusively with write cycles processor, whereas
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Examples generation OCLK with CLK1 CLK2 CLK3 (POLSEL, SELD.SELA 01011) draws attention exclusively read cycle. This example well inspire development engineer devise additional application possibilities which make these three clock inputs.
Figure 4-27:Possible utilization three clock inputs CLK1, CLK2 CLK3, where OCLK1, OCLK2 OCLK3 represent three possible programming options.
4.4.3 Post Triggering
With (HALTM), made continue accepting data address when full. this way, possible protocol discontinue further storage input data when event occurs (for example, arrival error signal), read 1023 words data which occurred before event. such case, protocol allows storage several words data both before after event. Aim: first waits signal arrive input before beginning accept data. begins transfer words data into internal memory. When memory full, starts again with address During this transfer, waits data word ???5h occur times: i.e. least significant bits must have value most significant bits ignored.
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Examples stores further data words before ceases accepting data. memory contains data words from before event, from after Method: CONTROL REGISTER RUNN OPCODE TRACE; inputs directly loaded into RAM; address counter starts after maximum value 3FFh, again 000h; Parity errors JTAG commands outputted EQO; inputs directly compared with expected data; RUNN clock signal CLK1; feedback mask here without significance; mask here also without significance. EVENT QUALIFICATION REGISTER Protocol synchronous signal, simple status request; address begins output signal TGATE (here mandatory); DCTERM used triggering event; loop counter LCNT active; event counter ECNT active; data loaded according protocol ENACMP here without meaning, since CTERM; loop counter LCNT value EVENT QUALIFICATION REGISTER
Address EVENT COUNTER Expected Data 8000h 0005h used Mask Data 0111111111111111 1111111111110000 used
Activate RUNN command, wait until test finished. INSTRUCTION REGISTER STATUS WORD advises whether more than 1024 data words were processed. count state address counter must read, order find address last word data which read.
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Examples Programming:
SCAN-TYPE Input Data IR-SCAN SCANCN DR-SCAN 1000 0001 0000000000000000 1111111111111111 IR-SCAN SCANEQN DR-SCAN 0110 0000000000000001 IR-SCAN WRITEFILE DR-SCAN 0000000000000001 0000 0000000000000101 1111111111110000 0000 DR-SCAN 0000000000000011 0001 0000000000000101 1111111111110000 0001 DR-SCAN 0000000010000000 0010 0000000000000000 0000000000000000 0010 IR-SCAN RUNN IR-SCAN RUNN IR-SCAN RUNN IR-SCAN RUNN IR-SCAN READRAM DR-SCAN 0000000000000000 0000000000
Output Data 10000001 ???? ???? ???????????????? ???????????????? 10000001 ???? ???????????????? 10000001 ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? ???????????????? ???? ???????????????? ???????????????? ???? 10000001 10100001 11100001 11010001 10000001 ???????????????? AAAAAAAAAA
status: IR-SCAN successful, RUNN begun. status: RUNN begun. status: RUNN will continued, more than 1024 words data have been processed. status: RUNN finished, more than 1024 bits data have been processed. AAAAAAAAAA counter state address counter. last stored word data address AAAAAAAAAA
advisable bypass necessary start signal, triggering start protocol execution masking bits data with event which always true. characteristic such that same events which appear successive pulse edges treated like single event, giving result that, when data bits masked, event does occur immediately, that never ends. implementation protocol therefore remains suspense, never brought end.
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Examples
4.4.4 Vertical Cascading
Cascading order increase memory depth more than 1024 data words envisaged with DBM. However, some cases same result with vertical cascading achieved making suitable program. following example based protocol intended suggest lines approach similar applications. Aim: Both DBMs first wait occurrence times data word ???5h, i.e. least significant bits must have value account taken most significant bits. DBM1 begins transfer 1024 data words internal memory; DBM2 then takes over, with storage further 1024 words data. Method: order reach intended result, first take DBM1 recognize event, then data word ???5h occur three times. event recognized, then must outputted EQO, both DBMs triggered their inputs EQI. Both DBMs begin with data storage. After 1024 data words DBM1 stops, DBM2 continues with data storage, starting with address After further 1024 data words DBM2 also stops, protocol implementation finished. DBM2 this been programmed store 2048 data words, necessary overflow data. CONTROL REGISTER RUNN OPCODE TRACE; inputs directly loaded into RAM; DBM1: address counter stops after maximum value 3FFh; DBM2: address counter starts again 000h after maximum value 3FFh; Parity errors JTAG commands outputted EQO; inputs directly compared with expected data; RUNN clock signal CLK1; feedback mask here without significance; mask also without significance. EVENT QUALIFICATION REGISTER Protocol Synchronous signal, simplified status request; address begins with DBM1: output signal CTERM; DBM2: output signal input used triggering event; loop counter LCNT active; event counter ECNT active; data loaded accordance with protocol ENACMP here without meaning, since CTERM; loop counter LCNT value
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Examples DBM1 EVENT QUALIFICATION REGISTER
Address EVENT COUNTER 1024 Expected Data 0005h used Mask Data 1111111111110000 used
DBM2 EVENT QUALIFICATION REGISTER
Address EVENT COUNTER 2048 Expected Data used used Mask Data used used
Activate RUNN command, wait until test finished.
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Examples Programming:
SCAN-TYPE Input Data IR-SCAN SCANCN SCANCN DR-SCAN 1000 0001 0000000000000000 1111111111111111 1000 0001 0000000000000000 1111111111111111 IR-SCAN SCANEQN SCANEQN DR-SCAN 0000 0000000000000001 1000 0000000000000001 IR-SCAN WRITEFILE WRITEFILE DR-SCAN 0000000000000010 0000 0000000000000000 1111111111111111 0000 0000000000000010 0000 0000000000000101 1111111111110000 0000 DR-SCAN 0000100000000000 0001 0000000000000000 0000000000000000 0001 0000010000000000 0001 0000000000000000 0000000000000000 0001 IR-SCAN RUNN RUNN IR-SCAN RUNN RUNN IR-SCAN RUNN RUNN IR-SCAN RUNN RUNN
Output Data 10000001 10000001 ???? ???? ???????????????? ???????????????? ???? ???? ???????????????? ???????????????? 10000001 10000001 ???? ???????????????? ???? ???????????????? 10000001 10000001 ???????????????? ???? ???????????????? ???????????????? ????
???????????????? ???? ???????????????? ???????????????? ????
10000001 10000001 10100001 10100001 11100001 10010001 11010001 10010001
DBM1 status: IR-SCAN successful, RUNN begun. DBM2 status: IR-SCAN successful, RUNN begun. DBM1 status: RUNN begun. DBM2 status: RUNN begun. DBM1 status: DBM2 status: DBM1 status: DBM2 status: RUNN finished. more than 1024 data words were processed (RAM overflow). RUNN finished. RUNN finished.
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Summary
Summary
JOINT TEST ACTION GROUP (JTAG) developed uniform test concept based BOUNDARY SCAN techniques, whose specification embodied IEEE standard 1149.1. This allows cost-effective testing complex electronic systems. Analyses which beyond interconnection tests are, however, either impossible limited application with most components which have been available until now. remedy this situation, DIGITAL MONITOR SN74ACT8994 provides function JTAG-controlled single-chip logic analyzer: 1024 words bits stored, parallel signature analysis performed, with very little requirement extra area circuit board. Additional features include easy programming flexible triggering with eight different protocols. This makes possible first time integrate logic analyzer into subassembly, example connect telephone line service center. Also, possible operate logic analyzer temperature controlled chamber, under other special environmental conditions. There doubt that DIGITAL MONITOR SN74ACT8994 represents practical extension range components compatible with IEEE 1149.1 which available.
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